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Proper name 16 bit libcalls
[llvm/msp430.git] / lib / Target / Alpha / AlphaISelLowering.cpp
blob10011125cf852f5ab48d5dcfaddb9f1d589ec8fa
1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AlphaISelLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CommandLine.h"
27 using namespace llvm;
28
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
31 /// register for it.
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
36 MF.getRegInfo().addLiveIn(PReg, VReg);
37 return VReg;
38 }
39
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setBooleanContents(ZeroOrOneBooleanContent);
45
46 setUsesGlobalOffsetTable(true);
47
48 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
49 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
50 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51
52 // We want to custom lower some of our intrinsics.
53 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
54
55 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
57
58 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
60
61 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
64
65 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
66 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
67 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
69
70 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
71
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FREM, MVT::f64, Expand);
74
75 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
76 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
77 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
78 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79
80 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
81 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
83 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 }
85 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
86 setOperationAction(ISD::ROTL , MVT::i64, Expand);
87 setOperationAction(ISD::ROTR , MVT::i64, Expand);
88
89 setOperationAction(ISD::SREM , MVT::i64, Custom);
90 setOperationAction(ISD::UREM , MVT::i64, Custom);
91 setOperationAction(ISD::SDIV , MVT::i64, Custom);
92 setOperationAction(ISD::UDIV , MVT::i64, Custom);
93
94 setOperationAction(ISD::ADDC , MVT::i64, Expand);
95 setOperationAction(ISD::ADDE , MVT::i64, Expand);
96 setOperationAction(ISD::SUBC , MVT::i64, Expand);
97 setOperationAction(ISD::SUBE , MVT::i64, Expand);
98
99 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
100 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
101
102
103 // We don't support sin/cos/sqrt/pow
104 setOperationAction(ISD::FSIN , MVT::f64, Expand);
105 setOperationAction(ISD::FCOS , MVT::f64, Expand);
106 setOperationAction(ISD::FSIN , MVT::f32, Expand);
107 setOperationAction(ISD::FCOS , MVT::f32, Expand);
108
109 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
110 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
111
112 setOperationAction(ISD::FPOW , MVT::f32, Expand);
113 setOperationAction(ISD::FPOW , MVT::f64, Expand);
114
115 setOperationAction(ISD::SETCC, MVT::f32, Promote);
116
117 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
118
119 // We don't have line number support yet.
120 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
121 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
122 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
123 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
124
125 // Not implemented yet.
126 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
127 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
128 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
129
130 // We want to legalize GlobalAddress and ConstantPool and
131 // ExternalSymbols nodes into the appropriate instructions to
132 // materialize the address.
133 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
134 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
135 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
136 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
137
138 setOperationAction(ISD::VASTART, MVT::Other, Custom);
139 setOperationAction(ISD::VAEND, MVT::Other, Expand);
140 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
141 setOperationAction(ISD::VAARG, MVT::Other, Custom);
142 setOperationAction(ISD::VAARG, MVT::i32, Custom);
143
144 setOperationAction(ISD::RET, MVT::Other, Custom);
145
146 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
148
149 setStackPointerRegisterToSaveRestore(Alpha::R30);
150
151 addLegalFPImmediate(APFloat(+0.0)); //F31
152 addLegalFPImmediate(APFloat(+0.0f)); //F31
153 addLegalFPImmediate(APFloat(-0.0)); //-F31
154 addLegalFPImmediate(APFloat(-0.0f)); //-F31
155
156 setJumpBufSize(272);
157 setJumpBufAlignment(16);
158
159 computeRegisterProperties();
160 }
161
162 MVT AlphaTargetLowering::getSetCCResultType(MVT VT) const {
163 return MVT::i64;
164 }
165
166 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
167 switch (Opcode) {
168 default: return 0;
169 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
170 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
171 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
172 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
173 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
174 case AlphaISD::RelLit: return "Alpha::RelLit";
175 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
176 case AlphaISD::CALL: return "Alpha::CALL";
177 case AlphaISD::DivCall: return "Alpha::DivCall";
178 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
179 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
180 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
181 }
182 }
183
184 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
185 MVT PtrVT = Op.getValueType();
186 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
187 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
188 SDValue Zero = DAG.getConstant(0, PtrVT);
189 // FIXME there isn't really any debug info here
190 DebugLoc dl = Op.getDebugLoc();
191
192 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
193 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
194 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
195 return Lo;
196 }
197
198 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
199 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
200
201 //For now, just use variable size stack frame format
202
203 //In a standard call, the first six items are passed in registers $16
204 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
205 //of argument-to-register correspondence.) The remaining items are
206 //collected in a memory argument list that is a naturally aligned
207 //array of quadwords. In a standard call, this list, if present, must
208 //be passed at 0(SP).
209 //7 ... n 0(SP) ... (n-7)*8(SP)
210
211 // //#define FP $15
212 // //#define RA $26
213 // //#define PV $27
214 // //#define GP $29
215 // //#define SP $30
216
217 static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
218 int &VarArgsBase,
219 int &VarArgsOffset) {
220 MachineFunction &MF = DAG.getMachineFunction();
221 MachineFrameInfo *MFI = MF.getFrameInfo();
222 std::vector<SDValue> ArgValues;
223 SDValue Root = Op.getOperand(0);
224 DebugLoc dl = Op.getDebugLoc();
225
226 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
227 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
228
229 unsigned args_int[] = {
230 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
231 unsigned args_float[] = {
232 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
233
234 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
235 SDValue argt;
236 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
237 SDValue ArgVal;
238
239 if (ArgNo < 6) {
240 switch (ObjectVT.getSimpleVT()) {
241 default:
242 assert(false && "Invalid value type!");
243 case MVT::f64:
244 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
245 &Alpha::F8RCRegClass);
246 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
247 break;
248 case MVT::f32:
249 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
250 &Alpha::F4RCRegClass);
251 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
252 break;
253 case MVT::i64:
254 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
255 &Alpha::GPRCRegClass);
256 ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64);
257 break;
258 }
259 } else { //more args
260 // Create the frame index object for this incoming parameter...
261 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
262
263 // Create the SelectionDAG nodes corresponding to a load
264 //from this parameter
265 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
266 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
267 }
268 ArgValues.push_back(ArgVal);
269 }
270
271 // If the functions takes variable number of arguments, copy all regs to stack
272 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
273 if (isVarArg) {
274 VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
275 std::vector<SDValue> LS;
276 for (int i = 0; i < 6; ++i) {
277 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
278 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
279 SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64);
280 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
281 if (i == 0) VarArgsBase = FI;
282 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
283 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
284
285 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
286 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
287 argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64);
288 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
289 SDFI = DAG.getFrameIndex(FI, MVT::i64);
290 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
291 }
292
293 //Set up a token factor with all the stack traffic
294 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
295 }
296
297 ArgValues.push_back(Root);
298
299 // Return the new list of results.
300 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
301 &ArgValues[0], ArgValues.size());
302 }
303
304 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
305 DebugLoc dl = Op.getDebugLoc();
306 SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26,
307 DAG.getNode(AlphaISD::GlobalRetAddr,
308 DebugLoc::getUnknownLoc(),
309 MVT::i64),
310 SDValue());
311 switch (Op.getNumOperands()) {
312 default:
313 assert(0 && "Do not know how to return this many arguments!");
314 abort();
315 case 1:
316 break;
317 //return SDValue(); // ret void is legal
318 case 3: {
319 MVT ArgVT = Op.getOperand(1).getValueType();
320 unsigned ArgReg;
321 if (ArgVT.isInteger())
322 ArgReg = Alpha::R0;
323 else {
324 assert(ArgVT.isFloatingPoint());
325 ArgReg = Alpha::F0;
326 }
327 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
328 Op.getOperand(1), Copy.getValue(1));
329 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
330 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
331 break;
332 }
333 case 5: {
334 MVT ArgVT = Op.getOperand(1).getValueType();
335 unsigned ArgReg1, ArgReg2;
336 if (ArgVT.isInteger()) {
337 ArgReg1 = Alpha::R0;
338 ArgReg2 = Alpha::R1;
339 } else {
340 assert(ArgVT.isFloatingPoint());
341 ArgReg1 = Alpha::F0;
342 ArgReg2 = Alpha::F1;
343 }
344 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
345 Op.getOperand(1), Copy.getValue(1));
346 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
347 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
348 == DAG.getMachineFunction().getRegInfo().liveout_end())
349 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
350 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
351 Op.getOperand(3), Copy.getValue(1));
352 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
353 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
354 == DAG.getMachineFunction().getRegInfo().liveout_end())
355 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
356 break;
357 }
358 }
359 return DAG.getNode(AlphaISD::RET_FLAG, dl,
360 MVT::Other, Copy, Copy.getValue(1));
361 }
362
363 std::pair<SDValue, SDValue>
364 AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
365 bool RetSExt, bool RetZExt, bool isVarArg,
366 bool isInreg, unsigned CallingConv,
367 bool isTailCall, SDValue Callee,
368 ArgListTy &Args, SelectionDAG &DAG,
369 DebugLoc dl) {
370 int NumBytes = 0;
371 if (Args.size() > 6)
372 NumBytes = (Args.size() - 6) * 8;
373
374 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
375 std::vector<SDValue> args_to_use;
376 for (unsigned i = 0, e = Args.size(); i != e; ++i)
377 {
378 switch (getValueType(Args[i].Ty).getSimpleVT()) {
379 default: assert(0 && "Unexpected ValueType for argument!");
380 case MVT::i1:
381 case MVT::i8:
382 case MVT::i16:
383 case MVT::i32:
384 // Promote the integer to 64 bits. If the input type is signed use a
385 // sign extend, otherwise use a zero extend.
386 if (Args[i].isSExt)
387 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
388 MVT::i64, Args[i].Node);
389 else if (Args[i].isZExt)
390 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
391 MVT::i64, Args[i].Node);
392 else
393 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
394 break;
395 case MVT::i64:
396 case MVT::f64:
397 case MVT::f32:
398 break;
399 }
400 args_to_use.push_back(Args[i].Node);
401 }
402
403 std::vector<MVT> RetVals;
404 MVT RetTyVT = getValueType(RetTy);
405 MVT ActualRetTyVT = RetTyVT;
406 if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
407 ActualRetTyVT = MVT::i64;
408
409 if (RetTyVT != MVT::isVoid)
410 RetVals.push_back(ActualRetTyVT);
411 RetVals.push_back(MVT::Other);
412
413 std::vector<SDValue> Ops;
414 Ops.push_back(Chain);
415 Ops.push_back(Callee);
416 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
417 SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
418 RetVals, &Ops[0], Ops.size());
419 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
420 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
421 DAG.getIntPtrConstant(0, true), SDValue());
422 SDValue RetVal = TheCall;
423
424 if (RetTyVT != ActualRetTyVT) {
425 ISD::NodeType AssertKind = ISD::DELETED_NODE;
426 if (RetSExt)
427 AssertKind = ISD::AssertSext;
428 else if (RetZExt)
429 AssertKind = ISD::AssertZext;
430
431 if (AssertKind != ISD::DELETED_NODE)
432 RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
433 DAG.getValueType(RetTyVT));
434
435 RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
436 }
437
438 return std::make_pair(RetVal, Chain);
439 }
440
441 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
442 SDValue &DataPtr, SelectionDAG &DAG) {
443 Chain = N->getOperand(0);
444 SDValue VAListP = N->getOperand(1);
445 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
446 DebugLoc dl = N->getDebugLoc();
447
448 SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
449 SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
450 DAG.getConstant(8, MVT::i64));
451 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
452 Tmp, NULL, 0, MVT::i32);
453 DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
454 if (N->getValueType(0).isFloatingPoint())
455 {
456 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
457 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
458 DAG.getConstant(8*6, MVT::i64));
459 SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
460 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
461 DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
462 }
463
464 SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
465 DAG.getConstant(8, MVT::i64));
466 Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
467 MVT::i32);
468 }
469
470 /// LowerOperation - Provide custom lowering hooks for some operations.
471 ///
472 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
473 DebugLoc dl = Op.getDebugLoc();
474 switch (Op.getOpcode()) {
475 default: assert(0 && "Wasn't expecting to be able to lower this!");
476 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
477 VarArgsBase,
478 VarArgsOffset);
479
480 case ISD::RET: return LowerRET(Op,DAG);
481 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
482
483 case ISD::INTRINSIC_WO_CHAIN: {
484 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
485 switch (IntNo) {
486 default: break; // Don't custom lower most intrinsics.
487 case Intrinsic::alpha_umulh:
488 return DAG.getNode(ISD::MULHU, dl, MVT::i64,
489 Op.getOperand(1), Op.getOperand(2));
490 }
491 }
492
493 case ISD::SINT_TO_FP: {
494 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
495 "Unhandled SINT_TO_FP type in custom expander!");
496 SDValue LD;
497 bool isDouble = Op.getValueType() == MVT::f64;
498 LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
499 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
500 isDouble?MVT::f64:MVT::f32, LD);
501 return FP;
502 }
503 case ISD::FP_TO_SINT: {
504 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
505 SDValue src = Op.getOperand(0);
506
507 if (!isDouble) //Promote
508 src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
509
510 src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
511
512 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
513 }
514 case ISD::ConstantPool: {
515 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
516 Constant *C = CP->getConstVal();
517 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
518 // FIXME there isn't really any debug info here
519
520 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
521 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
522 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
523 return Lo;
524 }
525 case ISD::GlobalTLSAddress:
526 assert(0 && "TLS not implemented for Alpha.");
527 case ISD::GlobalAddress: {
528 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
529 GlobalValue *GV = GSDN->getGlobal();
530 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
531 // FIXME there isn't really any debug info here
532
533 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
534 if (GV->hasLocalLinkage()) {
535 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
536 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
537 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
538 return Lo;
539 } else
540 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
541 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
542 }
543 case ISD::ExternalSymbol: {
544 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
545 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
546 ->getSymbol(), MVT::i64),
547 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
548 }
549
550 case ISD::UREM:
551 case ISD::SREM:
552 //Expand only on constant case
553 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
554 MVT VT = Op.getNode()->getValueType(0);
555 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
556 BuildUDIV(Op.getNode(), DAG, NULL) :
557 BuildSDIV(Op.getNode(), DAG, NULL);
558 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
559 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
560 return Tmp1;
561 }
562 //fall through
563 case ISD::SDIV:
564 case ISD::UDIV:
565 if (Op.getValueType().isInteger()) {
566 if (Op.getOperand(1).getOpcode() == ISD::Constant)
567 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
568 : BuildUDIV(Op.getNode(), DAG, NULL);
569 const char* opstr = 0;
570 switch (Op.getOpcode()) {
571 case ISD::UREM: opstr = "__remqu"; break;
572 case ISD::SREM: opstr = "__remq"; break;
573 case ISD::UDIV: opstr = "__divqu"; break;
574 case ISD::SDIV: opstr = "__divq"; break;
575 }
576 SDValue Tmp1 = Op.getOperand(0),
577 Tmp2 = Op.getOperand(1),
578 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
579 return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
580 }
581 break;
582
583 case ISD::VAARG: {
584 SDValue Chain, DataPtr;
585 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
586
587 SDValue Result;
588 if (Op.getValueType() == MVT::i32)
589 Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
590 NULL, 0, MVT::i32);
591 else
592 Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
593 return Result;
594 }
595 case ISD::VACOPY: {
596 SDValue Chain = Op.getOperand(0);
597 SDValue DestP = Op.getOperand(1);
598 SDValue SrcP = Op.getOperand(2);
599 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
600 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
601
602 SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
603 SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
604 SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
605 DAG.getConstant(8, MVT::i64));
606 Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
607 NP, NULL,0, MVT::i32);
608 SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
609 DAG.getConstant(8, MVT::i64));
610 return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
611 }
612 case ISD::VASTART: {
613 SDValue Chain = Op.getOperand(0);
614 SDValue VAListP = Op.getOperand(1);
615 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
616
617 // vastart stores the address of the VarArgsBase and VarArgsOffset
618 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
619 SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
620 SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
621 DAG.getConstant(8, MVT::i64));
622 return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
623 SA2, NULL, 0, MVT::i32);
624 }
625 case ISD::RETURNADDR:
626 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
627 MVT::i64);
628 //FIXME: implement
629 case ISD::FRAMEADDR: break;
630 }
631
632 return SDValue();
633 }
634
635 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
636 SmallVectorImpl<SDValue>&Results,
637 SelectionDAG &DAG) {
638 DebugLoc dl = N->getDebugLoc();
639 assert(N->getValueType(0) == MVT::i32 &&
640 N->getOpcode() == ISD::VAARG &&
641 "Unknown node to custom promote!");
642
643 SDValue Chain, DataPtr;
644 LowerVAARG(N, Chain, DataPtr, DAG);
645 SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0);
646 Results.push_back(Res);
647 Results.push_back(SDValue(Res.getNode(), 1));
648 }
649
650
651 //Inline Asm
652
653 /// getConstraintType - Given a constraint letter, return the type of
654 /// constraint it is for this target.
655 AlphaTargetLowering::ConstraintType
656 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
657 if (Constraint.size() == 1) {
658 switch (Constraint[0]) {
659 default: break;
660 case 'f':
661 case 'r':
662 return C_RegisterClass;
663 }
664 }
665 return TargetLowering::getConstraintType(Constraint);
666 }
667
668 std::vector<unsigned> AlphaTargetLowering::
669 getRegClassForInlineAsmConstraint(const std::string &Constraint,
670 MVT VT) const {
671 if (Constraint.size() == 1) {
672 switch (Constraint[0]) {
673 default: break; // Unknown constriant letter
674 case 'f':
675 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
676 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
677 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
678 Alpha::F9 , Alpha::F10, Alpha::F11,
679 Alpha::F12, Alpha::F13, Alpha::F14,
680 Alpha::F15, Alpha::F16, Alpha::F17,
681 Alpha::F18, Alpha::F19, Alpha::F20,
682 Alpha::F21, Alpha::F22, Alpha::F23,
683 Alpha::F24, Alpha::F25, Alpha::F26,
684 Alpha::F27, Alpha::F28, Alpha::F29,
685 Alpha::F30, Alpha::F31, 0);
686 case 'r':
687 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
688 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
689 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
690 Alpha::R9 , Alpha::R10, Alpha::R11,
691 Alpha::R12, Alpha::R13, Alpha::R14,
692 Alpha::R15, Alpha::R16, Alpha::R17,
693 Alpha::R18, Alpha::R19, Alpha::R20,
694 Alpha::R21, Alpha::R22, Alpha::R23,
695 Alpha::R24, Alpha::R25, Alpha::R26,
696 Alpha::R27, Alpha::R28, Alpha::R29,
697 Alpha::R30, Alpha::R31, 0);
698 }
699 }
700
701 return std::vector<unsigned>();
702 }
703 //===----------------------------------------------------------------------===//
704 // Other Lowering Code
705 //===----------------------------------------------------------------------===//
706
707 MachineBasicBlock *
708 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
709 MachineBasicBlock *BB) const {
710 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
711 assert((MI->getOpcode() == Alpha::CAS32 ||
712 MI->getOpcode() == Alpha::CAS64 ||
713 MI->getOpcode() == Alpha::LAS32 ||
714 MI->getOpcode() == Alpha::LAS64 ||
715 MI->getOpcode() == Alpha::SWAP32 ||
716 MI->getOpcode() == Alpha::SWAP64) &&
717 "Unexpected instr type to insert");
718
719 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
720 MI->getOpcode() == Alpha::LAS32 ||
721 MI->getOpcode() == Alpha::SWAP32;
722
723 //Load locked store conditional for atomic ops take on the same form
724 //start:
725 //ll
726 //do stuff (maybe branch to exit)
727 //sc
728 //test sc and maybe branck to start
729 //exit:
730 const BasicBlock *LLVM_BB = BB->getBasicBlock();
731 DebugLoc dl = MI->getDebugLoc();
732 MachineFunction::iterator It = BB;
733 ++It;
734
735 MachineBasicBlock *thisMBB = BB;
736 MachineFunction *F = BB->getParent();
737 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
738 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
739
740 sinkMBB->transferSuccessors(thisMBB);
741
742 F->insert(It, llscMBB);
743 F->insert(It, sinkMBB);
744
745 BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
746
747 unsigned reg_res = MI->getOperand(0).getReg(),
748 reg_ptr = MI->getOperand(1).getReg(),
749 reg_v2 = MI->getOperand(2).getReg(),
750 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
751
752 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
753 reg_res).addImm(0).addReg(reg_ptr);
754 switch (MI->getOpcode()) {
755 case Alpha::CAS32:
756 case Alpha::CAS64: {
757 unsigned reg_cmp
758 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
759 BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
760 .addReg(reg_v2).addReg(reg_res);
761 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
762 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
763 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
764 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
765 break;
766 }
767 case Alpha::LAS32:
768 case Alpha::LAS64: {
769 BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
770 .addReg(reg_res).addReg(reg_v2);
771 break;
772 }
773 case Alpha::SWAP32:
774 case Alpha::SWAP64: {
775 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
776 .addReg(reg_v2).addReg(reg_v2);
777 break;
778 }
779 }
780 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
781 .addReg(reg_store).addImm(0).addReg(reg_ptr);
782 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
783 .addImm(0).addReg(reg_store).addMBB(llscMBB);
784 BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
785
786 thisMBB->addSuccessor(llscMBB);
787 llscMBB->addSuccessor(llscMBB);
788 llscMBB->addSuccessor(sinkMBB);
789 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
790
791 return sinkMBB;
792 }
793
794 bool
795 AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
796 // The Alpha target isn't yet aware of offsets.
797 return false;
798 }
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