lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

   1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the Emit routines for the ScheduleDAG class, which creates
  11 // MachineInstrs according to the computed schedule.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "pre-RA-sched"
  16 #include "ScheduleDAGSDNodes.h"
  17 #include "llvm/CodeGen/MachineConstantPool.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/Target/TargetData.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/Target/TargetInstrInfo.h"
  24 #include "llvm/Target/TargetLowering.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/Support/CommandLine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/MathExtras.h"
  29 using namespace llvm;
  30
  31 /// getInstrOperandRegClass - Return register class of the operand of an
  32 /// instruction of the specified TargetInstrDesc.
  33 static const TargetRegisterClass*
  34 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
  35                         const TargetInstrDesc &II, unsigned Op) {
  36   if (Op >= II.getNumOperands()) {
  37     assert(II.isVariadic() && "Invalid operand # of instruction");
  38     return NULL;
  39   }
  40   if (II.OpInfo[Op].isLookupPtrRegClass())
  41     return TRI->getPointerRegClass();
  42   return TRI->getRegClass(II.OpInfo[Op].RegClass);
  43 }
  44
  45 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
  46 /// implicit physical register output.
  47 void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
  48                                          bool IsClone, bool IsCloned,
  49                                          unsigned SrcReg,
  50                                          DenseMap<SDValue, unsigned> &VRBaseMap) {
  51   unsigned VRBase = 0;
  52   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  53     // Just use the input register directly!
  54     SDValue Op(Node, ResNo);
  55     if (IsClone)
  56       VRBaseMap.erase(Op);
  57     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
  58     isNew = isNew; // Silence compiler warning.
  59     assert(isNew && "Node emitted out of order - early");
  60     return;
  61   }
  62
  63   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
  64   // the CopyToReg'd destination register instead of creating a new vreg.
  65   bool MatchReg = true;
  66   const TargetRegisterClass *UseRC = NULL;
  67   if (!IsClone && !IsCloned)
  68     for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
  69          UI != E; ++UI) {
  70       SDNode *User = *UI;
  71       bool Match = true;
  72       if (User->getOpcode() == ISD::CopyToReg &&
  73           User->getOperand(2).getNode() == Node &&
  74           User->getOperand(2).getResNo() == ResNo) {
  75         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
  76         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
  77           VRBase = DestReg;
  78           Match = false;
  79         } else if (DestReg != SrcReg)
  80           Match = false;
  81       } else {
  82         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
  83           SDValue Op = User->getOperand(i);
  84           if (Op.getNode() != Node || Op.getResNo() != ResNo)
  85             continue;
  86           MVT VT = Node->getValueType(Op.getResNo());
  87           if (VT == MVT::Other || VT == MVT::Flag)
  88             continue;
  89           Match = false;
  90           if (User->isMachineOpcode()) {
  91             const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
  92             const TargetRegisterClass *RC =
  93               getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
  94             if (!UseRC)
  95               UseRC = RC;
  96             else if (RC)
  97               assert(UseRC == RC &&
  98                      "Multiple uses expecting different register classes!");
  99           }
 100         }
 101       }
 102       MatchReg &= Match;
 103       if (VRBase)
 104         break;
 105     }
 106
 107   MVT VT = Node->getValueType(ResNo);
 108   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
 109   SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
 110
 111   // Figure out the register class to create for the destreg.
 112   if (VRBase) {
 113     DstRC = MRI.getRegClass(VRBase);
 114   } else if (UseRC) {
 115     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
 116     DstRC = UseRC;
 117   } else {
 118     DstRC = TLI->getRegClassFor(VT);
 119   }
 120
 121   // If all uses are reading from the src physical register and copying the
 122   // register is either impossible or very expensive, then don't create a copy.
 123   if (MatchReg && SrcRC->getCopyCost() < 0) {
 124     VRBase = SrcReg;
 125   } else {
 126     // Create the reg, emit the copy.
 127     VRBase = MRI.createVirtualRegister(DstRC);
 128     bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
 129                                      DstRC, SrcRC);
 130     if (!Emitted) {
 131       cerr << "Unable to issue a copy instruction!\n";
 132       abort();
 133     }
 134   }
 135
 136   SDValue Op(Node, ResNo);
 137   if (IsClone)
 138     VRBaseMap.erase(Op);
 139   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 140   isNew = isNew; // Silence compiler warning.
 141   assert(isNew && "Node emitted out of order - early");
 142 }
 143
 144 /// getDstOfCopyToRegUse - If the only use of the specified result number of
 145 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
 146 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
 147                                                       unsigned ResNo) const {
 148   if (!Node->hasOneUse())
 149     return 0;
 150
 151   SDNode *User = *Node->use_begin();
 152   if (User->getOpcode() == ISD::CopyToReg &&
 153       User->getOperand(2).getNode() == Node &&
 154       User->getOperand(2).getResNo() == ResNo) {
 155     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 156     if (TargetRegisterInfo::isVirtualRegister(Reg))
 157       return Reg;
 158   }
 159   return 0;
 160 }
 161
 162 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
 163                                        const TargetInstrDesc &II,
 164                                        bool IsClone, bool IsCloned,
 165                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 166   assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
 167          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
 168
 169   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
 170     // If the specific node value is only used by a CopyToReg and the dest reg
 171     // is a vreg, use the CopyToReg'd destination register instead of creating
 172     // a new vreg.
 173     unsigned VRBase = 0;
 174
 175     if (!IsClone && !IsCloned)
 176       for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 177            UI != E; ++UI) {
 178         SDNode *User = *UI;
 179         if (User->getOpcode() == ISD::CopyToReg &&
 180             User->getOperand(2).getNode() == Node &&
 181             User->getOperand(2).getResNo() == i) {
 182           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 183           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
 184             VRBase = Reg;
 185             MI->addOperand(MachineOperand::CreateReg(Reg, true));
 186             break;
 187           }
 188         }
 189       }
 190
 191     // Create the result registers for this node and add the result regs to
 192     // the machine instruction.
 193     if (VRBase == 0) {
 194       const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
 195       assert(RC && "Isn't a register operand!");
 196       VRBase = MRI.createVirtualRegister(RC);
 197       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 198     }
 199
 200     SDValue Op(Node, i);
 201     if (IsClone)
 202       VRBaseMap.erase(Op);
 203     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 204     isNew = isNew; // Silence compiler warning.
 205     assert(isNew && "Node emitted out of order - early");
 206   }
 207 }
 208
 209 /// getVR - Return the virtual register corresponding to the specified result
 210 /// of the specified node.
 211 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
 212                                    DenseMap<SDValue, unsigned> &VRBaseMap) {
 213   if (Op.isMachineOpcode() &&
 214       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
 215     // Add an IMPLICIT_DEF instruction before every use.
 216     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
 217     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
 218     // does not include operand register class info.
 219     if (!VReg) {
 220       const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
 221       VReg = MRI.createVirtualRegister(RC);
 222     }
 223     BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
 224     return VReg;
 225   }
 226
 227   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 228   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
 229   return I->second;
 230 }
 231
 232
 233 /// AddOperand - Add the specified operand to the specified machine instr.  II
 234 /// specifies the instruction information for the node, and IIOpNum is the
 235 /// operand number (in the II) that we are adding. IIOpNum and II are used for
 236 /// assertions only.
 237 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
 238                                     unsigned IIOpNum,
 239                                     const TargetInstrDesc *II,
 240                                     DenseMap<SDValue, unsigned> &VRBaseMap) {
 241   if (Op.isMachineOpcode()) {
 242     // Note that this case is redundant with the final else block, but we
 243     // include it because it is the most common and it makes the logic
 244     // simpler here.
 245     assert(Op.getValueType() != MVT::Other &&
 246            Op.getValueType() != MVT::Flag &&
 247            "Chain and flag operands should occur at end of operand list!");
 248     // Get/emit the operand.
 249     unsigned VReg = getVR(Op, VRBaseMap);
 250     const TargetInstrDesc &TID = MI->getDesc();
 251     bool isOptDef = IIOpNum < TID.getNumOperands() &&
 252       TID.OpInfo[IIOpNum].isOptionalDef();
 253     MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
 254
 255     // Verify that it is right.
 256     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
 257 #ifndef NDEBUG
 258     if (II) {
 259       // There may be no register class for this operand if it is a variadic
 260       // argument (RC will be NULL in this case).  In this case, we just assume
 261       // the regclass is ok.
 262       const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
 263       assert((RC || II->isVariadic()) && "Expected reg class info!");
 264       const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
 265       if (RC && VRC != RC) {
 266         cerr << "Register class of operand and regclass of use don't agree!\n";
 267         cerr << "Operand = " << IIOpNum << "\n";
 268         cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
 269         cerr << "MI = "; MI->print(cerr);
 270         cerr << "VReg = " << VReg << "\n";
 271         cerr << "VReg RegClass     size = " << VRC->getSize()
 272              << ", align = " << VRC->getAlignment() << "\n";
 273         cerr << "Expected RegClass size = " << RC->getSize()
 274              << ", align = " << RC->getAlignment() << "\n";
 275         cerr << "Fatal error, aborting.\n";
 276         abort();
 277       }
 278     }
 279 #endif
 280   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 281     MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
 282   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
 283     const ConstantFP *CFP = F->getConstantFPValue();
 284     MI->addOperand(MachineOperand::CreateFPImm(CFP));
 285   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
 286     MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
 287   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
 288     MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
 289   } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
 290     MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
 291   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
 292     MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
 293   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
 294     MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
 295   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
 296     int Offset = CP->getOffset();
 297     unsigned Align = CP->getAlignment();
 298     const Type *Type = CP->getType();
 299     // MachineConstantPool wants an explicit alignment.
 300     if (Align == 0) {
 301       Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
 302       if (Align == 0) {
 303         // Alignment of vector types.  FIXME!
 304         Align = TM.getTargetData()->getTypePaddedSize(Type);
 305         Align = Log2_64(Align);
 306       }
 307     }
 308
 309     unsigned Idx;
 310     if (CP->isMachineConstantPoolEntry())
 311       Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
 312     else
 313       Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
 314     MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
 315   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
 316     MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
 317   } else {
 318     assert(Op.getValueType() != MVT::Other &&
 319            Op.getValueType() != MVT::Flag &&
 320            "Chain and flag operands should occur at end of operand list!");
 321     unsigned VReg = getVR(Op, VRBaseMap);
 322     MI->addOperand(MachineOperand::CreateReg(VReg, false));
 323
 324     // Verify that it is right.  Note that the reg class of the physreg and the
 325     // vreg don't necessarily need to match, but the target copy insertion has
 326     // to be able to handle it.  This handles things like copies from ST(0) to
 327     // an FP vreg on x86.
 328     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
 329     if (II && !II->isVariadic()) {
 330       assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
 331              "Don't have operand info for this instruction!");
 332     }
 333   }
 334 }
 335
 336 /// EmitSubregNode - Generate machine code for subreg nodes.
 337 ///
 338 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
 339                                         DenseMap<SDValue, unsigned> &VRBaseMap) {
 340   unsigned VRBase = 0;
 341   unsigned Opc = Node->getMachineOpcode();
 342
 343   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
 344   // the CopyToReg'd destination register instead of creating a new vreg.
 345   for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 346        UI != E; ++UI) {
 347     SDNode *User = *UI;
 348     if (User->getOpcode() == ISD::CopyToReg &&
 349         User->getOperand(2).getNode() == Node) {
 350       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 351       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
 352         VRBase = DestReg;
 353         break;
 354       }
 355     }
 356   }
 357
 358   if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
 359     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 360
 361     // Create the extract_subreg machine instruction.
 362     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
 363                                TII->get(TargetInstrInfo::EXTRACT_SUBREG));
 364
 365     // Figure out the register class to create for the destreg.
 366     const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
 367
 368     if (VRBase) {
 369       // Grab the destination register
 370 #ifndef NDEBUG
 371       const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
 372       assert(SRC && DRC && SRC == DRC &&
 373              "Source subregister and destination must have the same class");
 374 #endif
 375     } else {
 376       // Create the reg
 377       assert(SRC && "Couldn't find source register class");
 378       VRBase = MRI.createVirtualRegister(SRC);
 379     }
 380
 381     // Add def, source, and subreg index
 382     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 383     AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
 384     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 385     BB->insert(InsertPos, MI);
 386   } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
 387              Opc == TargetInstrInfo::SUBREG_TO_REG) {
 388     SDValue N0 = Node->getOperand(0);
 389     SDValue N1 = Node->getOperand(1);
 390     SDValue N2 = Node->getOperand(2);
 391     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
 392
 393
 394     // Figure out the register class to create for the destreg.
 395     const TargetRegisterClass *TRC = 0;
 396     if (VRBase) {
 397       TRC = MRI.getRegClass(VRBase);
 398     } else {
 399       TRC = TLI->getRegClassFor(Node->getValueType(0));
 400       assert(TRC && "Couldn't determine register class for insert_subreg");
 401       VRBase = MRI.createVirtualRegister(TRC); // Create the reg
 402     }
 403
 404     // Create the insert_subreg or subreg_to_reg machine instruction.
 405     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
 406     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 407
 408     // If creating a subreg_to_reg, then the first input operand
 409     // is an implicit value immediate, otherwise it's a register
 410     if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
 411       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
 412       MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
 413     } else
 414       AddOperand(MI, N0, 0, 0, VRBaseMap);
 415     // Add the subregster being inserted
 416     AddOperand(MI, N1, 0, 0, VRBaseMap);
 417     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 418     BB->insert(InsertPos, MI);
 419   } else
 420     assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
 421
 422   SDValue Op(Node, 0);
 423   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 424   isNew = isNew; // Silence compiler warning.
 425   assert(isNew && "Node emitted out of order - early");
 426 }
 427
 428 /// EmitNode - Generate machine code for an node and needed dependencies.
 429 ///
 430 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
 431                                   DenseMap<SDValue, unsigned> &VRBaseMap) {
 432   // If machine instruction
 433   if (Node->isMachineOpcode()) {
 434     unsigned Opc = Node->getMachineOpcode();
 435
 436     // Handle subreg insert/extract specially
 437     if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
 438         Opc == TargetInstrInfo::INSERT_SUBREG ||
 439         Opc == TargetInstrInfo::SUBREG_TO_REG) {
 440       EmitSubregNode(Node, VRBaseMap);
 441       return;
 442     }
 443
 444     if (Opc == TargetInstrInfo::IMPLICIT_DEF)
 445       // We want a unique VR for each IMPLICIT_DEF use.
 446       return;
 447
 448     const TargetInstrDesc &II = TII->get(Opc);
 449     unsigned NumResults = CountResults(Node);
 450     unsigned NodeOperands = CountOperands(Node);
 451     unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
 452     bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
 453                           II.getImplicitDefs() != 0;
 454 #ifndef NDEBUG
 455     unsigned NumMIOperands = NodeOperands + NumResults;
 456     assert((II.getNumOperands() == NumMIOperands ||
 457             HasPhysRegOuts || II.isVariadic()) &&
 458            "#operands for dag node doesn't match .td file!");
 459 #endif
 460
 461     // Create the new machine instruction.
 462     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
 463
 464     // Add result register values for things that are defined by this
 465     // instruction.
 466     if (NumResults)
 467       CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
 468
 469     // Emit all of the actual operands of this instruction, adding them to the
 470     // instruction as appropriate.
 471     for (unsigned i = 0; i != NodeOperands; ++i)
 472       AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
 473
 474     // Emit all of the memory operands of this instruction
 475     for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
 476       AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
 477
 478     if (II.usesCustomDAGSchedInsertionHook()) {
 479       // Insert this instruction into the basic block using a target
 480       // specific inserter which may returns a new basic block.
 481       BB = TLI->EmitInstrWithCustomInserter(MI, BB);
 482       InsertPos = BB->end();
 483     } else {
 484       BB->insert(InsertPos, MI);
 485     }
 486
 487     // Additional results must be an physical register def.
 488     if (HasPhysRegOuts) {
 489       for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
 490         unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
 491         if (Node->hasAnyUseOfValue(i))
 492           EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
 493       }
 494     }
 495     return;
 496   }
 497
 498   switch (Node->getOpcode()) {
 499   default:
 500 #ifndef NDEBUG
 501     Node->dump(DAG);
 502 #endif
 503     assert(0 && "This target-independent node should have been selected!");
 504     break;
 505   case ISD::EntryToken:
 506     assert(0 && "EntryToken should have been excluded from the schedule!");
 507     break;
 508   case ISD::TokenFactor: // fall thru
 509     break;
 510   case ISD::CopyToReg: {
 511     unsigned SrcReg;
 512     SDValue SrcVal = Node->getOperand(2);
 513     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
 514       SrcReg = R->getReg();
 515     else
 516       SrcReg = getVR(SrcVal, VRBaseMap);
 517
 518     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 519     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
 520       break;
 521
 522     const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
 523     // Get the register classes of the src/dst.
 524     if (TargetRegisterInfo::isVirtualRegister(SrcReg))
 525       SrcTRC = MRI.getRegClass(SrcReg);
 526     else
 527       SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
 528
 529     if (TargetRegisterInfo::isVirtualRegister(DestReg))
 530       DstTRC = MRI.getRegClass(DestReg);
 531     else
 532       DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
 533                                             Node->getOperand(1).getValueType());
 534     bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
 535                                      DstTRC, SrcTRC);
 536     if (!Emitted) {
 537       cerr << "Unable to issue a copy instruction!\n";
 538       abort();
 539     }
 540     break;
 541   }
 542   case ISD::CopyFromReg: {
 543     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 544     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
 545     break;
 546   }
 547   case ISD::INLINEASM: {
 548     unsigned NumOps = Node->getNumOperands();
 549     if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
 550       --NumOps;  // Ignore the flag operand.
 551
 552     // Create the inline asm machine instruction.
 553     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
 554                                TII->get(TargetInstrInfo::INLINEASM));
 555
 556     // Add the asm string as an external symbol operand.
 557     const char *AsmStr =
 558       cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
 559     MI->addOperand(MachineOperand::CreateES(AsmStr));
 560
 561     // Add all of the operand registers to the instruction.
 562     for (unsigned i = 2; i != NumOps;) {
 563       unsigned Flags =
 564         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
 565       unsigned NumVals = Flags >> 3;
 566
 567       MI->addOperand(MachineOperand::CreateImm(Flags));
 568       ++i;  // Skip the ID value.
 569
 570       switch (Flags & 7) {
 571       default: assert(0 && "Bad flags!");
 572       case 2:   // Def of register.
 573         for (; NumVals; --NumVals, ++i) {
 574           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 575           MI->addOperand(MachineOperand::CreateReg(Reg, true));
 576         }
 577         break;
 578       case 6:   // Def of earlyclobber register.
 579         for (; NumVals; --NumVals, ++i) {
 580           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 581           MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
 582                                                    false, 0, true));
 583         }
 584         break;
 585       case 1:  // Use of register.
 586       case 3:  // Immediate.
 587       case 4:  // Addressing mode.
 588         // The addressing mode has been selected, just add all of the
 589         // operands to the machine instruction.
 590         for (; NumVals; --NumVals, ++i)
 591           AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
 592         break;
 593       }
 594     }
 595     BB->insert(InsertPos, MI);
 596     break;
 597   }
 598   }
 599 }
 600
 601 /// EmitSchedule - Emit the machine code in scheduled order.
 602 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
 603   DenseMap<SDValue, unsigned> VRBaseMap;
 604   DenseMap<SUnit*, unsigned> CopyVRBaseMap;
 605   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
 606     SUnit *SU = Sequence[i];
 607     if (!SU) {
 608       // Null SUnit* is a noop.
 609       EmitNoop();
 610       continue;
 611     }
 612
 613     // For pre-regalloc scheduling, create instructions corresponding to the
 614     // SDNode and any flagged SDNodes and append them to the block.
 615     if (!SU->getNode()) {
 616       // Emit a copy.
 617       EmitPhysRegCopy(SU, CopyVRBaseMap);
 618       continue;
 619     }
 620
 621     SmallVector<SDNode *, 4> FlaggedNodes;
 622     for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
 623          N = N->getFlaggedNode())
 624       FlaggedNodes.push_back(N);
 625     while (!FlaggedNodes.empty()) {
 626       EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
 627       FlaggedNodes.pop_back();
 628     }
 629     EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
 630   }
 631
 632   return BB;
 633 }