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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
26 // Start the numbering where the builtin ops and target ops leave off.
29 /// FSEL - Traditional three-operand fsel node.
30 ///
31 FSEL,
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
36 FCFID,
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
40 /// of that FP value.
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
45 STFIWX,
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
52 ///
53 VPERM,
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
62 TOC_ENTRY,
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
70 TOC_RESTORE,
72 /// Like a regular LOAD but additionally taking/producing a flag.
73 LOAD,
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
77 LOAD_TOC,
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
82 DYNALLOC,
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
86 GlobalBaseReg,
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
90 /// code.
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
94 /// registers.
95 EXTSW_32,
97 /// CALL - A direct function call.
100 /// NOP - Special NOP which follows 64-bit SVR4 calls.
101 NOP,
103 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
104 /// MTCTR instruction.
105 MTCTR,
107 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
108 /// BCTRL instruction.
111 /// Return with a flag operand, matched by 'blr'
112 RET_FLAG,
114 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
115 /// instructions. This copies the bits corresponding to the specified
116 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
117 /// are undefined.
118 MFCR,
120 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
121 /// instructions. For lack of better number, we use the opcode number
122 /// encoding for the OPC field to identify the compare. For example, 838
123 /// is VCMPGTSH.
124 VCMP,
126 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
127 /// altivec VCMP*o instructions. For lack of better number, we use the
128 /// opcode number encoding for the OPC field to identify the compare. For
129 /// example, 838 is VCMPGTSH.
130 VCMPo,
132 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
133 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
134 /// condition register to branch on, OPC is the branch opcode to use (e.g.
135 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
136 /// an optional input flag argument.
137 COND_BRANCH,
139 // The following 5 instructions are used only as part of the
140 // long double-to-int conversion sequence.
142 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
143 /// register.
144 MFFS,
146 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
147 MTFSB0,
149 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
150 MTFSB1,
152 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
153 /// rounding towards zero. It has flags added so it won't move past the
154 /// FPSCR-setting instructions.
155 FADDRTZ,
157 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
158 MTFSF,
160 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
161 /// reserve indexed. This is used to implement atomic operations.
162 LARX,
164 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
165 /// indexed. This is used to implement atomic operations.
166 STCX,
168 /// TC_RETURN - A tail call return.
169 /// operand #0 chain
170 /// operand #1 callee (register or absolute)
171 /// operand #2 stack adjustment
172 /// operand #3 optional in flag
173 TC_RETURN,
175 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
178 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
179 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
180 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
181 /// i32.
182 STBRX,
184 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
185 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
186 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
187 /// or i32.
188 LBRX
189 };
190 }
192 /// Define some predicates that are used for node matching.
194 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
195 /// VPKUHUM instruction.
198 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
199 /// VPKUWUM instruction.
202 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
203 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
207 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
208 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
212 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
213 /// amount, otherwise return -1.
216 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
217 /// specifies a splat of a single element that is suitable for input to
218 /// VSPLTB/VSPLTH/VSPLTW.
221 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
222 /// are -0.0.
225 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
226 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
229 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
230 /// formed by using a vspltis[bhw] instruction of the specified element
231 /// size, return the constant being splatted. The ByteSize field indicates
232 /// the number of bytes of each element [124] -> [bhw].
234 }
242 /// getTargetNodeName() - This method returns the name of a target specific
243 /// DAG node.
248 /// getSetCCResultType - Return the ISD::SETCC ValueType
251 /// getPreIndexedAddressParts - returns true by value, base pointer and
252 /// offset pointer and addressing mode by reference if the node's address
253 /// can be legally represented as pre-indexed load / store address.
259 /// SelectAddressRegReg - Given the specified addressed, check to see if it
260 /// can be represented as an indexed [r+r] operation. Returns false if it
261 /// can be more efficiently represented with [r+imm].
265 /// SelectAddressRegImm - Returns true if the address N can be represented
266 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
267 /// is not better represented as reg+reg.
271 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
272 /// represented as an indexed [r+r] operation.
276 /// SelectAddressRegImmShift - Returns true if the address N can be
277 /// represented by a base register plus a signed 14-bit displacement
278 /// [r+imm*4]. Suitable for use by STD and friends.
283 /// LowerOperation - Provide custom lowering hooks for some operations.
284 ///
287 /// ReplaceNodeResults - Replace the results of node with an illegal result
288 /// type with new values built out of custom code.
289 ///
314 /// Examine constraint string and operand type and determine a weight value.
315 /// The operand object must already have been set up with the operand type.
323 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
324 /// function arguments in the caller parameter area. This is the actual
325 /// alignment, not its logarithm.
328 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
329 /// vector. If it is invalid, don't add anything to Ops.
335 /// isLegalAddressingMode - Return true if the addressing mode represented
336 /// by AM is legal for this target, for a load/store of the specified type.
339 /// isLegalAddressImmediate - Return true if the integer value can be used
340 /// as the offset of the target addressing mode for load / store of the
341 /// given type.
344 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
345 /// the offset of the target addressing mode.
350 /// getOptimalMemOpType - Returns the target specific optimal type for load
351 /// and store operations as a result of memset, memcpy, and memmove
352 /// lowering. If DstAlign is zero that means it's safe to destination
353 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
354 /// means there isn't a need to check it against alignment requirement,
355 /// probably because the source does not need to be loaded. If
356 /// 'NonScalarIntSafe' is true, that means it's safe to return a
357 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
358 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
359 /// constant so it does not need to be loaded.
360 /// It returns EVT::Other if the type should be determined using generic
361 /// target-independent logic.
362 virtual EVT
371 bool
380 SDValue Chain,
431 virtual SDValue
438 virtual SDValue
447 virtual SDValue
454 SDValue
460 SDValue
467 SDValue
475 SDValue
483 };
484 }