lib/CodeGen/LowerSubregs.cpp

   1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a MachineFunction pass which runs after register
  11 // allocation that turns subreg insert/extract instructions into register
  12 // copies, as needed. This ensures correct codegen even if the coalescer
  13 // isn't able to remove all subreg instructions.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "lowersubregs"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/raw_ostream.h"
  29 using namespace llvm;
  30
  31 namespace {
  32   struct LowerSubregsInstructionPass : public MachineFunctionPass {
  33   private:
  34     const TargetRegisterInfo *TRI;
  35     const TargetInstrInfo *TII;
  36
  37   public:
  38     static char ID; // Pass identification, replacement for typeid
  39     LowerSubregsInstructionPass() : MachineFunctionPass(ID) {}
  40
  41     const char *getPassName() const {
  42       return "Subregister lowering instruction pass";
  43     }
  44
  45     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  46       AU.setPreservesCFG();
  47       AU.addPreservedID(MachineLoopInfoID);
  48       AU.addPreservedID(MachineDominatorsID);
  49       MachineFunctionPass::getAnalysisUsage(AU);
  50     }
  51
  52     /// runOnMachineFunction - pass entry point
  53     bool runOnMachineFunction(MachineFunction&);
  54
  55   private:
  56     bool LowerSubregToReg(MachineInstr *MI);
  57     bool LowerCopy(MachineInstr *MI);
  58
  59     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
  60                           const TargetRegisterInfo *TRI);
  61     void TransferImplicitDefs(MachineInstr *MI);
  62   };
  63
  64   char LowerSubregsInstructionPass::ID = 0;
  65 }
  66
  67 FunctionPass *llvm::createLowerSubregsPass() {
  68   return new LowerSubregsInstructionPass();
  69 }
  70
  71 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
  72 /// and the lowered replacement instructions immediately precede it.
  73 /// Mark the replacement instructions with the dead flag.
  74 void
  75 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
  76                                               unsigned DstReg,
  77                                               const TargetRegisterInfo *TRI) {
  78   for (MachineBasicBlock::iterator MII =
  79         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  80     if (MII->addRegisterDead(DstReg, TRI))
  81       break;
  82     assert(MII != MI->getParent()->begin() &&
  83            "copyPhysReg output doesn't reference destination register!");
  84   }
  85 }
  86
  87 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
  88 /// replacement instructions immediately precede it.  Copy any implicit-def
  89 /// operands from MI to the replacement instruction.
  90 void
  91 LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
  92   MachineBasicBlock::iterator CopyMI = MI;
  93   --CopyMI;
  94
  95   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
  96     MachineOperand &MO = MI->getOperand(i);
  97     if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
  98       continue;
  99     CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
 100   }
 101 }
 102
 103 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
 104   MachineBasicBlock *MBB = MI->getParent();
 105   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 106          MI->getOperand(1).isImm() &&
 107          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 108           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 109
 110   unsigned DstReg  = MI->getOperand(0).getReg();
 111   unsigned InsReg  = MI->getOperand(2).getReg();
 112   assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
 113   unsigned SubIdx  = MI->getOperand(3).getImm();
 114
 115   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 116   unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
 117
 118   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 119          "Insert destination must be in a physical register");
 120   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 121          "Inserted value must be in a physical register");
 122
 123   DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
 124
 125   if (DstSubReg == InsReg) {
 126     // No need to insert an identify copy instruction.
 127     // Watch out for case like this:
 128     // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
 129     // We must leave %RAX live.
 130     if (DstReg != InsReg) {
 131       MI->setDesc(TII->get(TargetOpcode::KILL));
 132       MI->RemoveOperand(3);     // SubIdx
 133       MI->RemoveOperand(1);     // Imm
 134       DEBUG(dbgs() << "subreg: replace by: " << *MI);
 135       return true;
 136     }
 137     DEBUG(dbgs() << "subreg: eliminated!");
 138   } else {
 139     TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
 140                      MI->getOperand(2).isKill());
 141     // Transfer the kill/dead flags, if needed.
 142     if (MI->getOperand(0).isDead())
 143       TransferDeadFlag(MI, DstSubReg, TRI);
 144     DEBUG({
 145         MachineBasicBlock::iterator dMI = MI;
 146         dbgs() << "subreg: " << *(--dMI);
 147       });
 148   }
 149
 150   DEBUG(dbgs() << '\n');
 151   MBB->erase(MI);
 152   return true;
 153 }
 154
 155 bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
 156   MachineOperand &DstMO = MI->getOperand(0);
 157   MachineOperand &SrcMO = MI->getOperand(1);
 158
 159   if (SrcMO.getReg() == DstMO.getReg()) {
 160     DEBUG(dbgs() << "identity copy: " << *MI);
 161     // No need to insert an identity copy instruction, but replace with a KILL
 162     // if liveness is changed.
 163     if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
 164       // We must make sure the super-register gets killed. Replace the
 165       // instruction with KILL.
 166       MI->setDesc(TII->get(TargetOpcode::KILL));
 167       DEBUG(dbgs() << "replaced by:   " << *MI);
 168       return true;
 169     }
 170     // Vanilla identity copy.
 171     MI->eraseFromParent();
 172     return true;
 173   }
 174
 175   DEBUG(dbgs() << "real copy:   " << *MI);
 176   TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
 177                    DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
 178
 179   if (DstMO.isDead())
 180     TransferDeadFlag(MI, DstMO.getReg(), TRI);
 181   if (MI->getNumOperands() > 2)
 182     TransferImplicitDefs(MI);
 183   DEBUG({
 184     MachineBasicBlock::iterator dMI = MI;
 185     dbgs() << "replaced by: " << *(--dMI);
 186   });
 187   MI->eraseFromParent();
 188   return true;
 189 }
 190
 191 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 192 /// copies.
 193 ///
 194 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 195   DEBUG(dbgs() << "Machine Function\n"
 196                << "********** LOWERING SUBREG INSTRS **********\n"
 197                << "********** Function: "
 198                << MF.getFunction()->getName() << '\n');
 199   TRI = MF.getTarget().getRegisterInfo();
 200   TII = MF.getTarget().getInstrInfo();
 201
 202   bool MadeChange = false;
 203
 204   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
 205        mbbi != mbbe; ++mbbi) {
 206     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
 207          mi != me;) {
 208       MachineBasicBlock::iterator nmi = llvm::next(mi);
 209       MachineInstr *MI = mi;
 210       assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
 211       assert(MI->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
 212              "EXTRACT_SUBREG should no longer appear");
 213       if (MI->isSubregToReg()) {
 214         MadeChange |= LowerSubregToReg(MI);
 215       } else if (MI->isCopy()) {
 216         MadeChange |= LowerCopy(MI);
 217       }
 218       mi = nmi;
 219     }
 220   }
 221
 222   return MadeChange;
 223 }