lib/CodeGen/RegAllocBase.h

   1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RegAllocBase class, which is the skeleton of a basic
  11 // register allocation algorithm and interface for extending it. It provides the
  12 // building blocks on which to construct other experimental allocators and test
  13 // the validity of two principles:
  14 //
  15 // - If virtual and physical register liveness is modeled using intervals, then
  16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
  17 // lazily cached and reused.
  18 //
  19 // - Register allocation complexity, and generated code performance is
  20 // determined by the effectiveness of live range splitting rather than optimal
  21 // coloring.
  22 //
  23 // Following the first principle, interfering checking revolves around the
  24 // LiveIntervalUnion data structure.
  25 //
  26 // To fulfill the second principle, the basic allocator provides a driver for
  27 // incremental splitting. It essentially punts on the problem of register
  28 // coloring, instead driving the assignment of virtual to physical registers by
  29 // the cost of splitting. The basic allocator allows for heuristic reassignment
  30 // of registers, if a more sophisticated allocator chooses to do that.
  31 //
  32 // This framework provides a way to engineer the compile time vs. code
  33 // quality trade-off without relying on a particular theoretical solver.
  34 //
  35 //===----------------------------------------------------------------------===//
  36
  37 #ifndef LLVM_CODEGEN_REGALLOCBASE
  38 #define LLVM_CODEGEN_REGALLOCBASE
  39
  40 #include "llvm/ADT/OwningPtr.h"
  41 #include "LiveIntervalUnion.h"
  42
  43 namespace llvm {
  44
  45 template<typename T> class SmallVectorImpl;
  46 class TargetRegisterInfo;
  47 class VirtRegMap;
  48 class LiveIntervals;
  49 class Spiller;
  50
  51 // Forward declare a priority queue of live virtual registers. If an
  52 // implementation needs to prioritize by anything other than spill weight, then
  53 // this will become an abstract base class with virtual calls to push/get.
  54 class LiveVirtRegQueue;
  55
  56 /// RegAllocBase provides the register allocation driver and interface that can
  57 /// be extended to add interesting heuristics.
  58 ///
  59 /// Register allocators must override the selectOrSplit() method to implement
  60 /// live range splitting. They must also override enqueue/dequeue to provide an
  61 /// assignment order.
  62 class RegAllocBase {
  63   LiveIntervalUnion::Allocator UnionAllocator;
  64
  65   // Cache tag for PhysReg2LiveUnion entries. Increment whenever virtual
  66   // registers may have changed.
  67   unsigned UserTag;
  68
  69 protected:
  70   // Array of LiveIntervalUnions indexed by physical register.
  71   class LiveUnionArray {
  72     unsigned NumRegs;
  73     LiveIntervalUnion *Array;
  74   public:
  75     LiveUnionArray(): NumRegs(0), Array(0) {}
  76     ~LiveUnionArray() { clear(); }
  77
  78     unsigned numRegs() const { return NumRegs; }
  79
  80     void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
  81
  82     void clear();
  83
  84     LiveIntervalUnion& operator[](unsigned PhysReg) {
  85       assert(PhysReg <  NumRegs && "physReg out of bounds");
  86       return Array[PhysReg];
  87     }
  88   };
  89
  90   const TargetRegisterInfo *TRI;
  91   MachineRegisterInfo *MRI;
  92   VirtRegMap *VRM;
  93   LiveIntervals *LIS;
  94   LiveUnionArray PhysReg2LiveUnion;
  95
  96   // Current queries, one per physreg. They must be reinitialized each time we
  97   // query on a new live virtual register.
  98   OwningArrayPtr<LiveIntervalUnion::Query> Queries;
  99
 100   RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
 101
 102   virtual ~RegAllocBase() {}
 103
 104   // A RegAlloc pass should call this before allocatePhysRegs.
 105   void init(VirtRegMap &vrm, LiveIntervals &lis);
 106
 107   // Get an initialized query to check interferences between lvr and preg.  Note
 108   // that Query::init must be called at least once for each physical register
 109   // before querying a new live virtual register. This ties Queries and
 110   // PhysReg2LiveUnion together.
 111   LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
 112     Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
 113     return Queries[PhysReg];
 114   }
 115
 116   // The top-level driver. The output is a VirtRegMap that us updated with
 117   // physical register assignments.
 118   //
 119   // If an implementation wants to override the LiveInterval comparator, we
 120   // should modify this interface to allow passing in an instance derived from
 121   // LiveVirtRegQueue.
 122   void allocatePhysRegs();
 123
 124   // Get a temporary reference to a Spiller instance.
 125   virtual Spiller &spiller() = 0;
 126
 127   /// enqueue - Add VirtReg to the priority queue of unassigned registers.
 128   virtual void enqueue(LiveInterval *LI) = 0;
 129
 130   /// dequeue - Return the next unassigned register, or NULL.
 131   virtual LiveInterval *dequeue() = 0;
 132
 133   // A RegAlloc pass should override this to provide the allocation heuristics.
 134   // Each call must guarantee forward progess by returning an available PhysReg
 135   // or new set of split live virtual registers. It is up to the splitter to
 136   // converge quickly toward fully spilled live ranges.
 137   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
 138                                  SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
 139
 140   // A RegAlloc pass should call this when PassManager releases its memory.
 141   virtual void releaseMemory();
 142
 143   // Helper for checking interference between a live virtual register and a
 144   // physical register, including all its register aliases. If an interference
 145   // exists, return the interfering register, which may be preg or an alias.
 146   unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
 147
 148   /// assign - Assign VirtReg to PhysReg.
 149   /// This should not be called from selectOrSplit for the current register.
 150   void assign(LiveInterval &VirtReg, unsigned PhysReg);
 151
 152   /// unassign - Undo a previous assignment of VirtReg to PhysReg.
 153   /// This can be invoked from selectOrSplit, but be careful to guarantee that
 154   /// allocation is making progress.
 155   void unassign(LiveInterval &VirtReg, unsigned PhysReg);
 156
 157   // Helper for spilling all live virtual registers currently unified under preg
 158   // that interfere with the most recently queried lvr.  Return true if spilling
 159   // was successful, and append any new spilled/split intervals to splitLVRs.
 160   bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
 161                           SmallVectorImpl<LiveInterval*> &SplitVRegs);
 162
 163   /// addMBBLiveIns - Add physreg liveins to basic blocks.
 164   void addMBBLiveIns(MachineFunction *);
 165
 166 #ifndef NDEBUG
 167   // Verify each LiveIntervalUnion.
 168   void verify();
 169 #endif
 170
 171   // Use this group name for NamedRegionTimer.
 172   static const char *TimerGroupName;
 173
 174 public:
 175   /// VerifyEnabled - True when -verify-regalloc is given.
 176   static bool VerifyEnabled;
 177
 178 private:
 179   void seedLiveRegs();
 180
 181   void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
 182                 SmallVectorImpl<LiveInterval*> &SplitVRegs);
 183 };
 184
 185 } // end namespace llvm
 186
 187 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)