lib/CodeGen/RegAllocBasic.cpp

   1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RABasic function pass, which provides a minimal
  11 // implementation of the basic register allocator.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "regalloc"
  16 #include "LiveDebugVariables.h"
  17 #include "LiveIntervalUnion.h"
  18 #include "LiveRangeEdit.h"
  19 #include "RegAllocBase.h"
  20 #include "RenderMachineFunction.h"
  21 #include "Spiller.h"
  22 #include "VirtRegMap.h"
  23 #include "llvm/ADT/OwningPtr.h"
  24 #include "llvm/ADT/Statistic.h"
  25 #include "llvm/Analysis/AliasAnalysis.h"
  26 #include "llvm/Function.h"
  27 #include "llvm/PassAnalysisSupport.h"
  28 #include "llvm/CodeGen/CalcSpillWeights.h"
  29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  30 #include "llvm/CodeGen/LiveStackAnalysis.h"
  31 #include "llvm/CodeGen/MachineFunctionPass.h"
  32 #include "llvm/CodeGen/MachineInstr.h"
  33 #include "llvm/CodeGen/MachineLoopInfo.h"
  34 #include "llvm/CodeGen/MachineRegisterInfo.h"
  35 #include "llvm/CodeGen/Passes.h"
  36 #include "llvm/CodeGen/RegAllocRegistry.h"
  37 #include "llvm/CodeGen/RegisterCoalescer.h"
  38 #include "llvm/Target/TargetMachine.h"
  39 #include "llvm/Target/TargetOptions.h"
  40 #include "llvm/Target/TargetRegisterInfo.h"
  41 #ifndef NDEBUG
  42 #include "llvm/ADT/SparseBitVector.h"
  43 #endif
  44 #include "llvm/Support/Debug.h"
  45 #include "llvm/Support/ErrorHandling.h"
  46 #include "llvm/Support/raw_ostream.h"
  47 #include "llvm/Support/Timer.h"
  48
  49 #include <cstdlib>
  50 #include <queue>
  51
  52 using namespace llvm;
  53
  54 STATISTIC(NumAssigned     , "Number of registers assigned");
  55 STATISTIC(NumUnassigned   , "Number of registers unassigned");
  56 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
  57
  58 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
  59                                       createBasicRegisterAllocator);
  60
  61 // Temporary verification option until we can put verification inside
  62 // MachineVerifier.
  63 static cl::opt<bool, true>
  64 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
  65                cl::desc("Verify during register allocation"));
  66
  67 const char *RegAllocBase::TimerGroupName = "Register Allocation";
  68 bool RegAllocBase::VerifyEnabled = false;
  69
  70 namespace {
  71   struct CompSpillWeight {
  72     bool operator()(LiveInterval *A, LiveInterval *B) const {
  73       return A->weight < B->weight;
  74     }
  75   };
  76 }
  77
  78 namespace {
  79 /// RABasic provides a minimal implementation of the basic register allocation
  80 /// algorithm. It prioritizes live virtual registers by spill weight and spills
  81 /// whenever a register is unavailable. This is not practical in production but
  82 /// provides a useful baseline both for measuring other allocators and comparing
  83 /// the speed of the basic algorithm against other styles of allocators.
  84 class RABasic : public MachineFunctionPass, public RegAllocBase
  85 {
  86   // context
  87   MachineFunction *MF;
  88   BitVector ReservedRegs;
  89
  90   // analyses
  91   LiveStacks *LS;
  92   RenderMachineFunction *RMF;
  93
  94   // state
  95   std::auto_ptr<Spiller> SpillerInstance;
  96   std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
  97                       CompSpillWeight> Queue;
  98 public:
  99   RABasic();
 100
 101   /// Return the pass name.
 102   virtual const char* getPassName() const {
 103     return "Basic Register Allocator";
 104   }
 105
 106   /// RABasic analysis usage.
 107   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 108
 109   virtual void releaseMemory();
 110
 111   virtual Spiller &spiller() { return *SpillerInstance; }
 112
 113   virtual float getPriority(LiveInterval *LI) { return LI->weight; }
 114
 115   virtual void enqueue(LiveInterval *LI) {
 116     Queue.push(LI);
 117   }
 118
 119   virtual LiveInterval *dequeue() {
 120     if (Queue.empty())
 121       return 0;
 122     LiveInterval *LI = Queue.top();
 123     Queue.pop();
 124     return LI;
 125   }
 126
 127   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
 128                                  SmallVectorImpl<LiveInterval*> &SplitVRegs);
 129
 130   /// Perform register allocation.
 131   virtual bool runOnMachineFunction(MachineFunction &mf);
 132
 133   static char ID;
 134 };
 135
 136 char RABasic::ID = 0;
 137
 138 } // end anonymous namespace
 139
 140 RABasic::RABasic(): MachineFunctionPass(ID) {
 141   initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
 142   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
 143   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
 144   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
 145   initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
 146   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
 147   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
 148   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
 149   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
 150   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
 151   initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
 152 }
 153
 154 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
 155   AU.setPreservesCFG();
 156   AU.addRequired<AliasAnalysis>();
 157   AU.addPreserved<AliasAnalysis>();
 158   AU.addRequired<LiveIntervals>();
 159   AU.addPreserved<SlotIndexes>();
 160   AU.addRequired<LiveDebugVariables>();
 161   AU.addPreserved<LiveDebugVariables>();
 162   if (StrongPHIElim)
 163     AU.addRequiredID(StrongPHIEliminationID);
 164   AU.addRequiredTransitive<RegisterCoalescer>();
 165   AU.addRequired<CalculateSpillWeights>();
 166   AU.addRequired<LiveStacks>();
 167   AU.addPreserved<LiveStacks>();
 168   AU.addRequiredID(MachineDominatorsID);
 169   AU.addPreservedID(MachineDominatorsID);
 170   AU.addRequired<MachineLoopInfo>();
 171   AU.addPreserved<MachineLoopInfo>();
 172   AU.addRequired<VirtRegMap>();
 173   AU.addPreserved<VirtRegMap>();
 174   DEBUG(AU.addRequired<RenderMachineFunction>());
 175   MachineFunctionPass::getAnalysisUsage(AU);
 176 }
 177
 178 void RABasic::releaseMemory() {
 179   SpillerInstance.reset(0);
 180   RegAllocBase::releaseMemory();
 181 }
 182
 183 #ifndef NDEBUG
 184 // Verify each LiveIntervalUnion.
 185 void RegAllocBase::verify() {
 186   LiveVirtRegBitSet VisitedVRegs;
 187   OwningArrayPtr<LiveVirtRegBitSet>
 188     unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
 189
 190   // Verify disjoint unions.
 191   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
 192     DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
 193     LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
 194     PhysReg2LiveUnion[PhysReg].verify(VRegs);
 195     // Union + intersection test could be done efficiently in one pass, but
 196     // don't add a method to SparseBitVector unless we really need it.
 197     assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
 198     VisitedVRegs |= VRegs;
 199   }
 200
 201   // Verify vreg coverage.
 202   for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
 203        liItr != liEnd; ++liItr) {
 204     unsigned reg = liItr->first;
 205     if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
 206     if (!VRM->hasPhys(reg)) continue; // spilled?
 207     unsigned PhysReg = VRM->getPhys(reg);
 208     if (!unionVRegs[PhysReg].test(reg)) {
 209       dbgs() << "LiveVirtReg " << reg << " not in union " <<
 210         TRI->getName(PhysReg) << "\n";
 211       llvm_unreachable("unallocated live vreg");
 212     }
 213   }
 214   // FIXME: I'm not sure how to verify spilled intervals.
 215 }
 216 #endif //!NDEBUG
 217
 218 //===----------------------------------------------------------------------===//
 219 //                         RegAllocBase Implementation
 220 //===----------------------------------------------------------------------===//
 221
 222 // Instantiate a LiveIntervalUnion for each physical register.
 223 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
 224                                         unsigned NRegs) {
 225   NumRegs = NRegs;
 226   Array =
 227     static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
 228   for (unsigned r = 0; r != NRegs; ++r)
 229     new(Array + r) LiveIntervalUnion(r, allocator);
 230 }
 231
 232 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
 233   NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
 234   TRI = &vrm.getTargetRegInfo();
 235   MRI = &vrm.getRegInfo();
 236   VRM = &vrm;
 237   LIS = &lis;
 238   const unsigned NumRegs = TRI->getNumRegs();
 239   if (NumRegs != PhysReg2LiveUnion.numRegs()) {
 240     PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
 241     // Cache an interferece query for each physical reg
 242     Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
 243   }
 244 }
 245
 246 void RegAllocBase::LiveUnionArray::clear() {
 247   if (!Array)
 248     return;
 249   for (unsigned r = 0; r != NumRegs; ++r)
 250     Array[r].~LiveIntervalUnion();
 251   free(Array);
 252   NumRegs =  0;
 253   Array = 0;
 254 }
 255
 256 void RegAllocBase::releaseMemory() {
 257   for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
 258     PhysReg2LiveUnion[r].clear();
 259 }
 260
 261 // Visit all the live registers. If they are already assigned to a physical
 262 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
 263 // them on the priority queue for later assignment.
 264 void RegAllocBase::seedLiveRegs() {
 265   NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
 266   for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
 267     unsigned RegNum = I->first;
 268     LiveInterval &VirtReg = *I->second;
 269     if (TargetRegisterInfo::isPhysicalRegister(RegNum))
 270       PhysReg2LiveUnion[RegNum].unify(VirtReg);
 271     else
 272       enqueue(&VirtReg);
 273   }
 274 }
 275
 276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
 277   DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
 278                << " to " << PrintReg(PhysReg, TRI) << '\n');
 279   assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
 280   VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
 281   MRI->setPhysRegUsed(PhysReg);
 282   PhysReg2LiveUnion[PhysReg].unify(VirtReg);
 283   ++NumAssigned;
 284 }
 285
 286 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
 287   DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
 288                << " from " << PrintReg(PhysReg, TRI) << '\n');
 289   assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
 290   PhysReg2LiveUnion[PhysReg].extract(VirtReg);
 291   VRM->clearVirt(VirtReg.reg);
 292   ++NumUnassigned;
 293 }
 294
 295 // Top-level driver to manage the queue of unassigned VirtRegs and call the
 296 // selectOrSplit implementation.
 297 void RegAllocBase::allocatePhysRegs() {
 298   seedLiveRegs();
 299
 300   // Continue assigning vregs one at a time to available physical registers.
 301   while (LiveInterval *VirtReg = dequeue()) {
 302     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
 303
 304     // Unused registers can appear when the spiller coalesces snippets.
 305     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
 306       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
 307       LIS->removeInterval(VirtReg->reg);
 308       continue;
 309     }
 310
 311     // Invalidate all interference queries, live ranges could have changed.
 312     ++UserTag;
 313
 314     // selectOrSplit requests the allocator to return an available physical
 315     // register if possible and populate a list of new live intervals that
 316     // result from splitting.
 317     DEBUG(dbgs() << "\nselectOrSplit "
 318                  << MRI->getRegClass(VirtReg->reg)->getName()
 319                  << ':' << *VirtReg << '\n');
 320     typedef SmallVector<LiveInterval*, 4> VirtRegVec;
 321     VirtRegVec SplitVRegs;
 322     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
 323
 324     if (AvailablePhysReg)
 325       assign(*VirtReg, AvailablePhysReg);
 326
 327     for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
 328          I != E; ++I) {
 329       LiveInterval *SplitVirtReg = *I;
 330       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
 331       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
 332         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
 333         LIS->removeInterval(SplitVirtReg->reg);
 334         continue;
 335       }
 336       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
 337       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
 338              "expect split value in virtual register");
 339       enqueue(SplitVirtReg);
 340       ++NumNewQueued;
 341     }
 342   }
 343 }
 344
 345 // Check if this live virtual register interferes with a physical register. If
 346 // not, then check for interference on each register that aliases with the
 347 // physical register. Return the interfering register.
 348 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
 349                                                 unsigned PhysReg) {
 350   for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
 351     if (query(VirtReg, *AliasI).checkInterference())
 352       return *AliasI;
 353   return 0;
 354 }
 355
 356 // Helper for spillInteferences() that spills all interfering vregs currently
 357 // assigned to this physical register.
 358 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
 359                             SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 360   LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
 361   assert(Q.seenAllInterferences() && "need collectInterferences()");
 362   const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
 363
 364   for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
 365          E = PendingSpills.end(); I != E; ++I) {
 366     LiveInterval &SpilledVReg = **I;
 367     DEBUG(dbgs() << "extracting from " <<
 368           TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
 369
 370     // Deallocate the interfering vreg by removing it from the union.
 371     // A LiveInterval instance may not be in a union during modification!
 372     unassign(SpilledVReg, PhysReg);
 373
 374     // Spill the extracted interval.
 375     LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
 376     spiller().spill(LRE);
 377   }
 378   // After extracting segments, the query's results are invalid. But keep the
 379   // contents valid until we're done accessing pendingSpills.
 380   Q.clear();
 381 }
 382
 383 // Spill or split all live virtual registers currently unified under PhysReg
 384 // that interfere with VirtReg. The newly spilled or split live intervals are
 385 // returned by appending them to SplitVRegs.
 386 bool
 387 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
 388                                  SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 389   // Record each interference and determine if all are spillable before mutating
 390   // either the union or live intervals.
 391   unsigned NumInterferences = 0;
 392   // Collect interferences assigned to any alias of the physical register.
 393   for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
 394     LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
 395     NumInterferences += QAlias.collectInterferingVRegs();
 396     if (QAlias.seenUnspillableVReg()) {
 397       return false;
 398     }
 399   }
 400   DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
 401         " interferences with " << VirtReg << "\n");
 402   assert(NumInterferences > 0 && "expect interference");
 403
 404   // Spill each interfering vreg allocated to PhysReg or an alias.
 405   for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
 406     spillReg(VirtReg, *AliasI, SplitVRegs);
 407   return true;
 408 }
 409
 410 // Add newly allocated physical registers to the MBB live in sets.
 411 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
 412   NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
 413   SlotIndexes *Indexes = LIS->getSlotIndexes();
 414   if (MF->size() <= 1)
 415     return;
 416
 417   LiveIntervalUnion::SegmentIter SI;
 418   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
 419     LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
 420     if (LiveUnion.empty())
 421       continue;
 422     MachineFunction::iterator MBB = llvm::next(MF->begin());
 423     MachineFunction::iterator MFE = MF->end();
 424     SlotIndex Start, Stop;
 425     tie(Start, Stop) = Indexes->getMBBRange(MBB);
 426     SI.setMap(LiveUnion.getMap());
 427     SI.find(Start);
 428     while (SI.valid()) {
 429       if (SI.start() <= Start) {
 430         if (!MBB->isLiveIn(PhysReg))
 431           MBB->addLiveIn(PhysReg);
 432       } else if (SI.start() > Stop)
 433         MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex());
 434       if (++MBB == MFE)
 435         break;
 436       tie(Start, Stop) = Indexes->getMBBRange(MBB);
 437       SI.advanceTo(Start);
 438     }
 439   }
 440 }
 441
 442
 443 //===----------------------------------------------------------------------===//
 444 //                         RABasic Implementation
 445 //===----------------------------------------------------------------------===//
 446
 447 // Driver for the register assignment and splitting heuristics.
 448 // Manages iteration over the LiveIntervalUnions.
 449 //
 450 // This is a minimal implementation of register assignment and splitting that
 451 // spills whenever we run out of registers.
 452 //
 453 // selectOrSplit can only be called once per live virtual register. We then do a
 454 // single interference test for each register the correct class until we find an
 455 // available register. So, the number of interference tests in the worst case is
 456 // |vregs| * |machineregs|. And since the number of interference tests is
 457 // minimal, there is no value in caching them outside the scope of
 458 // selectOrSplit().
 459 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
 460                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 461   // Populate a list of physical register spill candidates.
 462   SmallVector<unsigned, 8> PhysRegSpillCands;
 463
 464   // Check for an available register in this class.
 465   const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
 466
 467   for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
 468          E = TRC->allocation_order_end(*MF);
 469        I != E; ++I) {
 470
 471     unsigned PhysReg = *I;
 472     if (ReservedRegs.test(PhysReg)) continue;
 473
 474     // Check interference and as a side effect, intialize queries for this
 475     // VirtReg and its aliases.
 476     unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
 477     if (interfReg == 0) {
 478       // Found an available register.
 479       return PhysReg;
 480     }
 481     LiveInterval *interferingVirtReg =
 482       Queries[interfReg].firstInterference().liveUnionPos().value();
 483
 484     // The current VirtReg must either be spillable, or one of its interferences
 485     // must have less spill weight.
 486     if (interferingVirtReg->weight < VirtReg.weight ) {
 487       PhysRegSpillCands.push_back(PhysReg);
 488     }
 489   }
 490   // Try to spill another interfering reg with less spill weight.
 491   for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
 492          PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
 493
 494     if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
 495
 496     assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
 497            "Interference after spill.");
 498     // Tell the caller to allocate to this newly freed physical register.
 499     return *PhysRegI;
 500   }
 501   // No other spill candidates were found, so spill the current VirtReg.
 502   DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
 503   LiveRangeEdit LRE(VirtReg, SplitVRegs);
 504   spiller().spill(LRE);
 505
 506   // The live virtual register requesting allocation was spilled, so tell
 507   // the caller not to allocate anything during this round.
 508   return 0;
 509 }
 510
 511 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
 512   DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
 513                << "********** Function: "
 514                << ((Value*)mf.getFunction())->getName() << '\n');
 515
 516   MF = &mf;
 517   DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
 518
 519   RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
 520
 521   ReservedRegs = TRI->getReservedRegs(*MF);
 522
 523   SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
 524
 525   allocatePhysRegs();
 526
 527   addMBBLiveIns(MF);
 528
 529   // Diagnostic output before rewriting
 530   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
 531
 532   // optional HTML output
 533   DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
 534
 535   // FIXME: Verification currently must run before VirtRegRewriter. We should
 536   // make the rewriter a separate pass and override verifyAnalysis instead. When
 537   // that happens, verification naturally falls under VerifyMachineCode.
 538 #ifndef NDEBUG
 539   if (VerifyEnabled) {
 540     // Verify accuracy of LiveIntervals. The standard machine code verifier
 541     // ensures that each LiveIntervals covers all uses of the virtual reg.
 542
 543     // FIXME: MachineVerifier is badly broken when using the standard
 544     // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
 545     // inline spiller, some tests fail to verify because the coalescer does not
 546     // always generate verifiable code.
 547     MF->verify(this, "In RABasic::verify");
 548
 549     // Verify that LiveIntervals are partitioned into unions and disjoint within
 550     // the unions.
 551     verify();
 552   }
 553 #endif // !NDEBUG
 554
 555   // Run rewriter
 556   VRM->rewrite(LIS->getSlotIndexes());
 557
 558   // Write out new DBG_VALUE instructions.
 559   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
 560
 561   // The pass output is in VirtRegMap. Release all the transient data.
 562   releaseMemory();
 563
 564   return true;
 565 }
 566
 567 FunctionPass* llvm::createBasicRegisterAllocator()
 568 {
 569   return new RABasic();
 570 }