lib/CodeGen/RegAllocGreedy.cpp

   1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RAGreedy function pass for register allocation in
  11 // optimized builds.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "regalloc"
  16 #include "AllocationOrder.h"
  17 #include "InterferenceCache.h"
  18 #include "LiveDebugVariables.h"
  19 #include "LiveRangeEdit.h"
  20 #include "RegAllocBase.h"
  21 #include "Spiller.h"
  22 #include "SpillPlacement.h"
  23 #include "SplitKit.h"
  24 #include "VirtRegMap.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/Analysis/AliasAnalysis.h"
  27 #include "llvm/Function.h"
  28 #include "llvm/PassAnalysisSupport.h"
  29 #include "llvm/CodeGen/CalcSpillWeights.h"
  30 #include "llvm/CodeGen/EdgeBundles.h"
  31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  32 #include "llvm/CodeGen/LiveStackAnalysis.h"
  33 #include "llvm/CodeGen/MachineDominators.h"
  34 #include "llvm/CodeGen/MachineFunctionPass.h"
  35 #include "llvm/CodeGen/MachineLoopInfo.h"
  36 #include "llvm/CodeGen/MachineLoopRanges.h"
  37 #include "llvm/CodeGen/MachineRegisterInfo.h"
  38 #include "llvm/CodeGen/Passes.h"
  39 #include "llvm/CodeGen/RegAllocRegistry.h"
  40 #include "llvm/CodeGen/RegisterCoalescer.h"
  41 #include "llvm/Target/TargetOptions.h"
  42 #include "llvm/Support/Debug.h"
  43 #include "llvm/Support/ErrorHandling.h"
  44 #include "llvm/Support/raw_ostream.h"
  45 #include "llvm/Support/Timer.h"
  46
  47 #include <queue>
  48
  49 using namespace llvm;
  50
  51 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
  52 STATISTIC(NumLocalSplits,  "Number of split local live ranges");
  53 STATISTIC(NumEvicted,      "Number of interferences evicted");
  54
  55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
  56                                        createGreedyRegisterAllocator);
  57
  58 namespace {
  59 class RAGreedy : public MachineFunctionPass,
  60                  public RegAllocBase,
  61                  private LiveRangeEdit::Delegate {
  62
  63   // context
  64   MachineFunction *MF;
  65   BitVector ReservedRegs;
  66
  67   // analyses
  68   SlotIndexes *Indexes;
  69   LiveStacks *LS;
  70   MachineDominatorTree *DomTree;
  71   MachineLoopInfo *Loops;
  72   MachineLoopRanges *LoopRanges;
  73   EdgeBundles *Bundles;
  74   SpillPlacement *SpillPlacer;
  75
  76   // state
  77   std::auto_ptr<Spiller> SpillerInstance;
  78   std::priority_queue<std::pair<unsigned, unsigned> > Queue;
  79
  80   // Live ranges pass through a number of stages as we try to allocate them.
  81   // Some of the stages may also create new live ranges:
  82   //
  83   // - Region splitting.
  84   // - Per-block splitting.
  85   // - Local splitting.
  86   // - Spilling.
  87   //
  88   // Ranges produced by one of the stages skip the previous stages when they are
  89   // dequeued. This improves performance because we can skip interference checks
  90   // that are unlikely to give any results. It also guarantees that the live
  91   // range splitting algorithm terminates, something that is otherwise hard to
  92   // ensure.
  93   enum LiveRangeStage {
  94     RS_New,      ///< Never seen before.
  95     RS_First,    ///< First time in the queue.
  96     RS_Second,   ///< Second time in the queue.
  97     RS_Global,   ///< Produced by global splitting.
  98     RS_Local,    ///< Produced by local splitting.
  99     RS_Spill     ///< Produced by spilling.
 100   };
 101
 102   IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
 103
 104   LiveRangeStage getStage(const LiveInterval &VirtReg) const {
 105     return LiveRangeStage(LRStage[VirtReg.reg]);
 106   }
 107
 108   template<typename Iterator>
 109   void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
 110     LRStage.resize(MRI->getNumVirtRegs());
 111     for (;Begin != End; ++Begin) {
 112       unsigned Reg = (*Begin)->reg;
 113       if (LRStage[Reg] == RS_New)
 114         LRStage[Reg] = NewStage;
 115     }
 116   }
 117
 118   // splitting state.
 119   std::auto_ptr<SplitAnalysis> SA;
 120   std::auto_ptr<SplitEditor> SE;
 121
 122   /// Cached per-block interference maps
 123   InterferenceCache IntfCache;
 124
 125   /// All basic blocks where the current register has uses.
 126   SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
 127
 128   /// Global live range splitting candidate info.
 129   struct GlobalSplitCandidate {
 130     unsigned PhysReg;
 131     BitVector LiveBundles;
 132     SmallVector<unsigned, 8> ActiveBlocks;
 133
 134     void reset(unsigned Reg) {
 135       PhysReg = Reg;
 136       LiveBundles.clear();
 137       ActiveBlocks.clear();
 138     }
 139   };
 140
 141   /// Candidate info for for each PhysReg in AllocationOrder.
 142   /// This vector never shrinks, but grows to the size of the largest register
 143   /// class.
 144   SmallVector<GlobalSplitCandidate, 32> GlobalCand;
 145
 146   /// For every instruction in SA->UseSlots, store the previous non-copy
 147   /// instruction.
 148   SmallVector<SlotIndex, 8> PrevSlot;
 149
 150 public:
 151   RAGreedy();
 152
 153   /// Return the pass name.
 154   virtual const char* getPassName() const {
 155     return "Greedy Register Allocator";
 156   }
 157
 158   /// RAGreedy analysis usage.
 159   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 160   virtual void releaseMemory();
 161   virtual Spiller &spiller() { return *SpillerInstance; }
 162   virtual void enqueue(LiveInterval *LI);
 163   virtual LiveInterval *dequeue();
 164   virtual unsigned selectOrSplit(LiveInterval&,
 165                                  SmallVectorImpl<LiveInterval*>&);
 166
 167   /// Perform register allocation.
 168   virtual bool runOnMachineFunction(MachineFunction &mf);
 169
 170   static char ID;
 171
 172 private:
 173   void LRE_WillEraseInstruction(MachineInstr*);
 174   bool LRE_CanEraseVirtReg(unsigned);
 175   void LRE_WillShrinkVirtReg(unsigned);
 176   void LRE_DidCloneVirtReg(unsigned, unsigned);
 177
 178   bool addSplitConstraints(InterferenceCache::Cursor, float&);
 179   void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
 180   void growRegion(GlobalSplitCandidate &Cand, InterferenceCache::Cursor);
 181   float calcGlobalSplitCost(GlobalSplitCandidate&, InterferenceCache::Cursor);
 182   void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&,
 183                          SmallVectorImpl<LiveInterval*>&);
 184   void calcGapWeights(unsigned, SmallVectorImpl<float>&);
 185   SlotIndex getPrevMappedIndex(const MachineInstr*);
 186   void calcPrevSlots();
 187   unsigned nextSplitPoint(unsigned);
 188   bool canEvictInterference(LiveInterval&, unsigned, float&);
 189
 190   unsigned tryAssign(LiveInterval&, AllocationOrder&,
 191                      SmallVectorImpl<LiveInterval*>&);
 192   unsigned tryEvict(LiveInterval&, AllocationOrder&,
 193                     SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
 194   unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
 195                           SmallVectorImpl<LiveInterval*>&);
 196   unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
 197     SmallVectorImpl<LiveInterval*>&);
 198   unsigned trySplit(LiveInterval&, AllocationOrder&,
 199                     SmallVectorImpl<LiveInterval*>&);
 200 };
 201 } // end anonymous namespace
 202
 203 char RAGreedy::ID = 0;
 204
 205 FunctionPass* llvm::createGreedyRegisterAllocator() {
 206   return new RAGreedy();
 207 }
 208
 209 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
 210   initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
 211   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
 212   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
 213   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
 214   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
 215   initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
 216   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
 217   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
 218   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
 219   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
 220   initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
 221   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
 222   initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
 223   initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
 224 }
 225
 226 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
 227   AU.setPreservesCFG();
 228   AU.addRequired<AliasAnalysis>();
 229   AU.addPreserved<AliasAnalysis>();
 230   AU.addRequired<LiveIntervals>();
 231   AU.addRequired<SlotIndexes>();
 232   AU.addPreserved<SlotIndexes>();
 233   AU.addRequired<LiveDebugVariables>();
 234   AU.addPreserved<LiveDebugVariables>();
 235   if (StrongPHIElim)
 236     AU.addRequiredID(StrongPHIEliminationID);
 237   AU.addRequiredTransitive<RegisterCoalescer>();
 238   AU.addRequired<CalculateSpillWeights>();
 239   AU.addRequired<LiveStacks>();
 240   AU.addPreserved<LiveStacks>();
 241   AU.addRequired<MachineDominatorTree>();
 242   AU.addPreserved<MachineDominatorTree>();
 243   AU.addRequired<MachineLoopInfo>();
 244   AU.addPreserved<MachineLoopInfo>();
 245   AU.addRequired<MachineLoopRanges>();
 246   AU.addPreserved<MachineLoopRanges>();
 247   AU.addRequired<VirtRegMap>();
 248   AU.addPreserved<VirtRegMap>();
 249   AU.addRequired<EdgeBundles>();
 250   AU.addRequired<SpillPlacement>();
 251   MachineFunctionPass::getAnalysisUsage(AU);
 252 }
 253
 254
 255 //===----------------------------------------------------------------------===//
 256 //                     LiveRangeEdit delegate methods
 257 //===----------------------------------------------------------------------===//
 258
 259 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
 260   // LRE itself will remove from SlotIndexes and parent basic block.
 261   VRM->RemoveMachineInstrFromMaps(MI);
 262 }
 263
 264 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
 265   if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
 266     unassign(LIS->getInterval(VirtReg), PhysReg);
 267     return true;
 268   }
 269   // Unassigned virtreg is probably in the priority queue.
 270   // RegAllocBase will erase it after dequeueing.
 271   return false;
 272 }
 273
 274 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
 275   unsigned PhysReg = VRM->getPhys(VirtReg);
 276   if (!PhysReg)
 277     return;
 278
 279   // Register is assigned, put it back on the queue for reassignment.
 280   LiveInterval &LI = LIS->getInterval(VirtReg);
 281   unassign(LI, PhysReg);
 282   enqueue(&LI);
 283 }
 284
 285 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
 286   // LRE may clone a virtual register because dead code elimination causes it to
 287   // be split into connected components. Ensure that the new register gets the
 288   // same stage as the parent.
 289   LRStage.grow(New);
 290   LRStage[New] = LRStage[Old];
 291 }
 292
 293 void RAGreedy::releaseMemory() {
 294   SpillerInstance.reset(0);
 295   LRStage.clear();
 296   GlobalCand.clear();
 297   RegAllocBase::releaseMemory();
 298 }
 299
 300 void RAGreedy::enqueue(LiveInterval *LI) {
 301   // Prioritize live ranges by size, assigning larger ranges first.
 302   // The queue holds (size, reg) pairs.
 303   const unsigned Size = LI->getSize();
 304   const unsigned Reg = LI->reg;
 305   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
 306          "Can only enqueue virtual registers");
 307   unsigned Prio;
 308
 309   LRStage.grow(Reg);
 310   if (LRStage[Reg] == RS_New)
 311     LRStage[Reg] = RS_First;
 312
 313   if (LRStage[Reg] == RS_Second)
 314     // Unsplit ranges that couldn't be allocated immediately are deferred until
 315     // everything else has been allocated. Long ranges are allocated last so
 316     // they are split against realistic interference.
 317     Prio = (1u << 31) - Size;
 318   else {
 319     // Everything else is allocated in long->short order. Long ranges that don't
 320     // fit should be spilled ASAP so they don't create interference.
 321     Prio = (1u << 31) + Size;
 322
 323     // Boost ranges that have a physical register hint.
 324     if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
 325       Prio |= (1u << 30);
 326   }
 327
 328   Queue.push(std::make_pair(Prio, Reg));
 329 }
 330
 331 LiveInterval *RAGreedy::dequeue() {
 332   if (Queue.empty())
 333     return 0;
 334   LiveInterval *LI = &LIS->getInterval(Queue.top().second);
 335   Queue.pop();
 336   return LI;
 337 }
 338
 339
 340 //===----------------------------------------------------------------------===//
 341 //                            Direct Assignment
 342 //===----------------------------------------------------------------------===//
 343
 344 /// tryAssign - Try to assign VirtReg to an available register.
 345 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
 346                              AllocationOrder &Order,
 347                              SmallVectorImpl<LiveInterval*> &NewVRegs) {
 348   Order.rewind();
 349   unsigned PhysReg;
 350   while ((PhysReg = Order.next()))
 351     if (!checkPhysRegInterference(VirtReg, PhysReg))
 352       break;
 353   if (!PhysReg || Order.isHint(PhysReg))
 354     return PhysReg;
 355
 356   // PhysReg is available. Try to evict interference from a cheaper alternative.
 357   unsigned Cost = TRI->getCostPerUse(PhysReg);
 358
 359   // Most registers have 0 additional cost.
 360   if (!Cost)
 361     return PhysReg;
 362
 363   DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
 364                << '\n');
 365   unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
 366   return CheapReg ? CheapReg : PhysReg;
 367 }
 368
 369
 370 //===----------------------------------------------------------------------===//
 371 //                         Interference eviction
 372 //===----------------------------------------------------------------------===//
 373
 374 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
 375 /// be evicted.
 376 /// Return false if any interference is heavier than MaxWeight.
 377 /// On return, set MaxWeight to the maximal spill weight of an interference.
 378 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
 379                                     float &MaxWeight) {
 380   float Weight = 0;
 381   for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
 382     LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
 383     // If there is 10 or more interferences, chances are one is heavier.
 384     if (Q.collectInterferingVRegs(10, MaxWeight) >= 10)
 385       return false;
 386
 387     // Check if any interfering live range is heavier than MaxWeight.
 388     for (unsigned i = Q.interferingVRegs().size(); i; --i) {
 389       LiveInterval *Intf = Q.interferingVRegs()[i - 1];
 390       if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
 391         return false;
 392       if (Intf->weight >= MaxWeight)
 393         return false;
 394       Weight = std::max(Weight, Intf->weight);
 395     }
 396   }
 397   MaxWeight = Weight;
 398   return true;
 399 }
 400
 401 /// tryEvict - Try to evict all interferences for a physreg.
 402 /// @param  VirtReg Currently unassigned virtual register.
 403 /// @param  Order   Physregs to try.
 404 /// @return         Physreg to assign VirtReg, or 0.
 405 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
 406                             AllocationOrder &Order,
 407                             SmallVectorImpl<LiveInterval*> &NewVRegs,
 408                             unsigned CostPerUseLimit) {
 409   NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
 410
 411   // Keep track of the lightest single interference seen so far.
 412   float BestWeight = VirtReg.weight;
 413   unsigned BestPhys = 0;
 414
 415   Order.rewind();
 416   while (unsigned PhysReg = Order.next()) {
 417     if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
 418       continue;
 419     // The first use of a register in a function has cost 1.
 420     if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg))
 421       continue;
 422
 423     float Weight = BestWeight;
 424     if (!canEvictInterference(VirtReg, PhysReg, Weight))
 425       continue;
 426
 427     // This is an eviction candidate.
 428     DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " interference = "
 429                  << Weight << '\n');
 430     if (BestPhys && Weight >= BestWeight)
 431       continue;
 432
 433     // Best so far.
 434     BestPhys = PhysReg;
 435     BestWeight = Weight;
 436     // Stop if the hint can be used.
 437     if (Order.isHint(PhysReg))
 438       break;
 439   }
 440
 441   if (!BestPhys)
 442     return 0;
 443
 444   DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
 445   for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
 446     LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
 447     assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
 448     for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
 449       LiveInterval *Intf = Q.interferingVRegs()[i];
 450       unassign(*Intf, VRM->getPhys(Intf->reg));
 451       ++NumEvicted;
 452       NewVRegs.push_back(Intf);
 453     }
 454   }
 455   return BestPhys;
 456 }
 457
 458
 459 //===----------------------------------------------------------------------===//
 460 //                              Region Splitting
 461 //===----------------------------------------------------------------------===//
 462
 463 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
 464 /// interference pattern in Physreg and its aliases. Add the constraints to
 465 /// SpillPlacement and return the static cost of this split in Cost, assuming
 466 /// that all preferences in SplitConstraints are met.
 467 /// Return false if there are no bundles with positive bias.
 468 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
 469                                    float &Cost) {
 470   ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
 471
 472   // Reset interference dependent info.
 473   SplitConstraints.resize(UseBlocks.size());
 474   float StaticCost = 0;
 475   for (unsigned i = 0; i != UseBlocks.size(); ++i) {
 476     const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
 477     SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
 478
 479     BC.Number = BI.MBB->getNumber();
 480     Intf.moveToBlock(BC.Number);
 481     BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
 482     BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
 483
 484     if (!Intf.hasInterference())
 485       continue;
 486
 487     // Number of spill code instructions to insert.
 488     unsigned Ins = 0;
 489
 490     // Interference for the live-in value.
 491     if (BI.LiveIn) {
 492       if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
 493         BC.Entry = SpillPlacement::MustSpill, ++Ins;
 494       else if (Intf.first() < BI.FirstUse)
 495         BC.Entry = SpillPlacement::PrefSpill, ++Ins;
 496       else if (Intf.first() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
 497         ++Ins;
 498     }
 499
 500     // Interference for the live-out value.
 501     if (BI.LiveOut) {
 502       if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
 503         BC.Exit = SpillPlacement::MustSpill, ++Ins;
 504       else if (Intf.last() > BI.LastUse)
 505         BC.Exit = SpillPlacement::PrefSpill, ++Ins;
 506       else if (Intf.last() > (BI.LiveThrough ? BI.FirstUse : BI.Def))
 507         ++Ins;
 508     }
 509
 510     // Accumulate the total frequency of inserted spill code.
 511     if (Ins)
 512       StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
 513   }
 514   Cost = StaticCost;
 515
 516   // Add constraints for use-blocks. Note that these are the only constraints
 517   // that may add a positive bias, it is downhill from here.
 518   SpillPlacer->addConstraints(SplitConstraints);
 519   return SpillPlacer->scanActiveBundles();
 520 }
 521
 522
 523 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
 524 /// live-through blocks in Blocks.
 525 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
 526                                      ArrayRef<unsigned> Blocks) {
 527   const unsigned GroupSize = 8;
 528   SpillPlacement::BlockConstraint BCS[GroupSize];
 529   unsigned TBS[GroupSize];
 530   unsigned B = 0, T = 0;
 531
 532   for (unsigned i = 0; i != Blocks.size(); ++i) {
 533     unsigned Number = Blocks[i];
 534     Intf.moveToBlock(Number);
 535
 536     if (!Intf.hasInterference()) {
 537       assert(T < GroupSize && "Array overflow");
 538       TBS[T] = Number;
 539       if (++T == GroupSize) {
 540         SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
 541         T = 0;
 542       }
 543       continue;
 544     }
 545
 546     assert(B < GroupSize && "Array overflow");
 547     BCS[B].Number = Number;
 548
 549     // Interference for the live-in value.
 550     if (Intf.first() <= Indexes->getMBBStartIdx(Number))
 551       BCS[B].Entry = SpillPlacement::MustSpill;
 552     else
 553       BCS[B].Entry = SpillPlacement::PrefSpill;
 554
 555     // Interference for the live-out value.
 556     if (Intf.last() >= SA->getLastSplitPoint(Number))
 557       BCS[B].Exit = SpillPlacement::MustSpill;
 558     else
 559       BCS[B].Exit = SpillPlacement::PrefSpill;
 560
 561     if (++B == GroupSize) {
 562       ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
 563       SpillPlacer->addConstraints(Array);
 564       B = 0;
 565     }
 566   }
 567
 568   ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
 569   SpillPlacer->addConstraints(Array);
 570   SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
 571 }
 572
 573 void RAGreedy::growRegion(GlobalSplitCandidate &Cand,
 574                           InterferenceCache::Cursor Intf) {
 575   // Keep track of through blocks that have not been added to SpillPlacer.
 576   BitVector Todo = SA->getThroughBlocks();
 577   SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
 578   unsigned AddedTo = 0;
 579 #ifndef NDEBUG
 580   unsigned Visited = 0;
 581 #endif
 582
 583   for (;;) {
 584     ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
 585     if (NewBundles.empty())
 586       break;
 587     // Find new through blocks in the periphery of PrefRegBundles.
 588     for (int i = 0, e = NewBundles.size(); i != e; ++i) {
 589       unsigned Bundle = NewBundles[i];
 590       // Look at all blocks connected to Bundle in the full graph.
 591       ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
 592       for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
 593            I != E; ++I) {
 594         unsigned Block = *I;
 595         if (!Todo.test(Block))
 596           continue;
 597         Todo.reset(Block);
 598         // This is a new through block. Add it to SpillPlacer later.
 599         ActiveBlocks.push_back(Block);
 600 #ifndef NDEBUG
 601         ++Visited;
 602 #endif
 603       }
 604     }
 605     // Any new blocks to add?
 606     if (ActiveBlocks.size() > AddedTo) {
 607       ArrayRef<unsigned> Add(&ActiveBlocks[AddedTo],
 608                              ActiveBlocks.size() - AddedTo);
 609       addThroughConstraints(Intf, Add);
 610       AddedTo = ActiveBlocks.size();
 611     }
 612     // Perhaps iterating can enable more bundles?
 613     SpillPlacer->iterate();
 614   }
 615   DEBUG(dbgs() << ", v=" << Visited);
 616 }
 617
 618 /// calcGlobalSplitCost - Return the global split cost of following the split
 619 /// pattern in LiveBundles. This cost should be added to the local cost of the
 620 /// interference pattern in SplitConstraints.
 621 ///
 622 float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand,
 623                                     InterferenceCache::Cursor Intf) {
 624   float GlobalCost = 0;
 625   const BitVector &LiveBundles = Cand.LiveBundles;
 626   ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
 627   for (unsigned i = 0; i != UseBlocks.size(); ++i) {
 628     const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
 629     SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
 630     bool RegIn  = LiveBundles[Bundles->getBundle(BC.Number, 0)];
 631     bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
 632     unsigned Ins = 0;
 633
 634     if (BI.LiveIn)
 635       Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
 636     if (BI.LiveOut)
 637       Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
 638     if (Ins)
 639       GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
 640   }
 641
 642   for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
 643     unsigned Number = Cand.ActiveBlocks[i];
 644     bool RegIn  = LiveBundles[Bundles->getBundle(Number, 0)];
 645     bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
 646     if (!RegIn && !RegOut)
 647       continue;
 648     if (RegIn && RegOut) {
 649       // We need double spill code if this block has interference.
 650       Intf.moveToBlock(Number);
 651       if (Intf.hasInterference())
 652         GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
 653       continue;
 654     }
 655     // live-in / stack-out or stack-in live-out.
 656     GlobalCost += SpillPlacer->getBlockFrequency(Number);
 657   }
 658   return GlobalCost;
 659 }
 660
 661 /// splitAroundRegion - Split VirtReg around the region determined by
 662 /// LiveBundles. Make an effort to avoid interference from PhysReg.
 663 ///
 664 /// The 'register' interval is going to contain as many uses as possible while
 665 /// avoiding interference. The 'stack' interval is the complement constructed by
 666 /// SplitEditor. It will contain the rest.
 667 ///
 668 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg,
 669                                  GlobalSplitCandidate &Cand,
 670                                  SmallVectorImpl<LiveInterval*> &NewVRegs) {
 671   const BitVector &LiveBundles = Cand.LiveBundles;
 672
 673   DEBUG({
 674     dbgs() << "Splitting around region for " << PrintReg(Cand.PhysReg, TRI)
 675            << " with bundles";
 676     for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
 677       dbgs() << " EB#" << i;
 678     dbgs() << ".\n";
 679   });
 680
 681   InterferenceCache::Cursor Intf(IntfCache, Cand.PhysReg);
 682   LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
 683   SE->reset(LREdit);
 684
 685   // Create the main cross-block interval.
 686   const unsigned MainIntv = SE->openIntv();
 687
 688   // First add all defs that are live out of a block.
 689   ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
 690   for (unsigned i = 0; i != UseBlocks.size(); ++i) {
 691     const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
 692     bool RegIn  = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
 693     bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
 694
 695     // Create separate intervals for isolated blocks with multiple uses.
 696     if (!RegIn && !RegOut && BI.FirstUse != BI.LastUse) {
 697       DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
 698       SE->splitSingleBlock(BI);
 699       SE->selectIntv(MainIntv);
 700       continue;
 701     }
 702
 703     // Should the register be live out?
 704     if (!BI.LiveOut || !RegOut)
 705       continue;
 706
 707     SlotIndex Start, Stop;
 708     tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
 709     Intf.moveToBlock(BI.MBB->getNumber());
 710     DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
 711                  << Bundles->getBundle(BI.MBB->getNumber(), 1)
 712                  << " [" << Start << ';'
 713                  << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
 714                  << ") intf [" << Intf.first() << ';' << Intf.last() << ')');
 715
 716     // The interference interval should either be invalid or overlap MBB.
 717     assert((!Intf.hasInterference() || Intf.first() < Stop)
 718            && "Bad interference");
 719     assert((!Intf.hasInterference() || Intf.last() > Start)
 720            && "Bad interference");
 721
 722     // Check interference leaving the block.
 723     if (!Intf.hasInterference()) {
 724       // Block is interference-free.
 725       DEBUG(dbgs() << ", no interference");
 726       if (!BI.LiveThrough) {
 727         DEBUG(dbgs() << ", not live-through.\n");
 728         SE->useIntv(SE->enterIntvBefore(BI.Def), Stop);
 729         continue;
 730       }
 731       if (!RegIn) {
 732         // Block is live-through, but entry bundle is on the stack.
 733         // Reload just before the first use.
 734         DEBUG(dbgs() << ", not live-in, enter before first use.\n");
 735         SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop);
 736         continue;
 737       }
 738       DEBUG(dbgs() << ", live-through.\n");
 739       continue;
 740     }
 741
 742     // Block has interference.
 743     DEBUG(dbgs() << ", interference to " << Intf.last());
 744
 745     if (!BI.LiveThrough && Intf.last() <= BI.Def) {
 746       // The interference doesn't reach the outgoing segment.
 747       DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
 748       SE->useIntv(BI.Def, Stop);
 749       continue;
 750     }
 751
 752     SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
 753     if (Intf.last().getBoundaryIndex() < BI.LastUse) {
 754       // There are interference-free uses at the end of the block.
 755       // Find the first use that can get the live-out register.
 756       SmallVectorImpl<SlotIndex>::const_iterator UI =
 757         std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
 758                          Intf.last().getBoundaryIndex());
 759       assert(UI != SA->UseSlots.end() && "Couldn't find last use");
 760       SlotIndex Use = *UI;
 761       assert(Use <= BI.LastUse && "Couldn't find last use");
 762       // Only attempt a split befroe the last split point.
 763       if (Use.getBaseIndex() <= LastSplitPoint) {
 764         DEBUG(dbgs() << ", free use at " << Use << ".\n");
 765         SlotIndex SegStart = SE->enterIntvBefore(Use);
 766         assert(SegStart >= Intf.last() && "Couldn't avoid interference");
 767         assert(SegStart < LastSplitPoint && "Impossible split point");
 768         SE->useIntv(SegStart, Stop);
 769         continue;
 770       }
 771     }
 772
 773     // Interference is after the last use.
 774     DEBUG(dbgs() << " after last use.\n");
 775     SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
 776     assert(SegStart >= Intf.last() && "Couldn't avoid interference");
 777   }
 778
 779   // Now all defs leading to live bundles are handled, do everything else.
 780   for (unsigned i = 0; i != UseBlocks.size(); ++i) {
 781     const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
 782     bool RegIn  = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
 783     bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
 784
 785     // Is the register live-in?
 786     if (!BI.LiveIn || !RegIn)
 787       continue;
 788
 789     // We have an incoming register. Check for interference.
 790     SlotIndex Start, Stop;
 791     tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
 792     Intf.moveToBlock(BI.MBB->getNumber());
 793     DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
 794                  << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';'
 795                  << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
 796                  << ')');
 797
 798     // Check interference entering the block.
 799     if (!Intf.hasInterference()) {
 800       // Block is interference-free.
 801       DEBUG(dbgs() << ", no interference");
 802       if (!BI.LiveThrough) {
 803         DEBUG(dbgs() << ", killed in block.\n");
 804         SE->useIntv(Start, SE->leaveIntvAfter(BI.Kill));
 805         continue;
 806       }
 807       if (!RegOut) {
 808         SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
 809         // Block is live-through, but exit bundle is on the stack.
 810         // Spill immediately after the last use.
 811         if (BI.LastUse < LastSplitPoint) {
 812           DEBUG(dbgs() << ", uses, stack-out.\n");
 813           SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse));
 814           continue;
 815         }
 816         // The last use is after the last split point, it is probably an
 817         // indirect jump.
 818         DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
 819                      << LastSplitPoint << ", stack-out.\n");
 820         SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint);
 821         SE->useIntv(Start, SegEnd);
 822         // Run a double interval from the split to the last use.
 823         // This makes it possible to spill the complement without affecting the
 824         // indirect branch.
 825         SE->overlapIntv(SegEnd, BI.LastUse);
 826         continue;
 827       }
 828       // Register is live-through.
 829       DEBUG(dbgs() << ", uses, live-through.\n");
 830       SE->useIntv(Start, Stop);
 831       continue;
 832     }
 833
 834     // Block has interference.
 835     DEBUG(dbgs() << ", interference from " << Intf.first());
 836
 837     if (!BI.LiveThrough && Intf.first() >= BI.Kill) {
 838       // The interference doesn't reach the outgoing segment.
 839       DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
 840       SE->useIntv(Start, BI.Kill);
 841       continue;
 842     }
 843
 844     if (Intf.first().getBaseIndex() > BI.FirstUse) {
 845       // There are interference-free uses at the beginning of the block.
 846       // Find the last use that can get the register.
 847       SmallVectorImpl<SlotIndex>::const_iterator UI =
 848         std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
 849                          Intf.first().getBaseIndex());
 850       assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
 851       SlotIndex Use = (--UI)->getBoundaryIndex();
 852       DEBUG(dbgs() << ", free use at " << *UI << ".\n");
 853       SlotIndex SegEnd = SE->leaveIntvAfter(Use);
 854       assert(SegEnd <= Intf.first() && "Couldn't avoid interference");
 855       SE->useIntv(Start, SegEnd);
 856       continue;
 857     }
 858
 859     // Interference is before the first use.
 860     DEBUG(dbgs() << " before first use.\n");
 861     SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
 862     assert(SegEnd <= Intf.first() && "Couldn't avoid interference");
 863   }
 864
 865   // Handle live-through blocks.
 866   for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
 867     unsigned Number = Cand.ActiveBlocks[i];
 868     bool RegIn  = LiveBundles[Bundles->getBundle(Number, 0)];
 869     bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
 870     DEBUG(dbgs() << "Live through BB#" << Number << '\n');
 871     if (RegIn && RegOut) {
 872       Intf.moveToBlock(Number);
 873       if (!Intf.hasInterference()) {
 874         SE->useIntv(Indexes->getMBBStartIdx(Number),
 875                     Indexes->getMBBEndIdx(Number));
 876         continue;
 877       }
 878     }
 879     MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
 880     if (RegIn)
 881       SE->leaveIntvAtTop(*MBB);
 882     if (RegOut)
 883       SE->enterIntvAtEnd(*MBB);
 884   }
 885
 886   // FIXME: Should we be more aggressive about splitting the stack region into
 887   // per-block segments? The current approach allows the stack region to
 888   // separate into connected components. Some components may be allocatable.
 889   SE->finish();
 890   ++NumGlobalSplits;
 891
 892   if (VerifyEnabled)
 893     MF->verify(this, "After splitting live range around region");
 894 }
 895
 896 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
 897                                   SmallVectorImpl<LiveInterval*> &NewVRegs) {
 898   float BestCost = 0;
 899   const unsigned NoCand = ~0u;
 900   unsigned BestCand = NoCand;
 901
 902   Order.rewind();
 903   for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
 904     if (GlobalCand.size() <= Cand)
 905       GlobalCand.resize(Cand+1);
 906     GlobalCand[Cand].reset(PhysReg);
 907
 908     SpillPlacer->prepare(GlobalCand[Cand].LiveBundles);
 909     float Cost;
 910     InterferenceCache::Cursor Intf(IntfCache, PhysReg);
 911     if (!addSplitConstraints(Intf, Cost)) {
 912       DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
 913       continue;
 914     }
 915     DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
 916     if (BestCand != NoCand && Cost >= BestCost) {
 917       DEBUG(dbgs() << " worse than "
 918                    << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n');
 919       continue;
 920     }
 921     growRegion(GlobalCand[Cand], Intf);
 922
 923     SpillPlacer->finish();
 924
 925     // No live bundles, defer to splitSingleBlocks().
 926     if (!GlobalCand[Cand].LiveBundles.any()) {
 927       DEBUG(dbgs() << " no bundles.\n");
 928       continue;
 929     }
 930
 931     Cost += calcGlobalSplitCost(GlobalCand[Cand], Intf);
 932     DEBUG({
 933       dbgs() << ", total = " << Cost << " with bundles";
 934       for (int i = GlobalCand[Cand].LiveBundles.find_first(); i>=0;
 935            i = GlobalCand[Cand].LiveBundles.find_next(i))
 936         dbgs() << " EB#" << i;
 937       dbgs() << ".\n";
 938     });
 939     if (BestCand == NoCand || Cost < BestCost) {
 940       BestCand = Cand;
 941       BestCost = 0.98f * Cost; // Prevent rounding effects.
 942     }
 943   }
 944
 945   if (BestCand == NoCand)
 946     return 0;
 947
 948   splitAroundRegion(VirtReg, GlobalCand[BestCand], NewVRegs);
 949   setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global);
 950   return 0;
 951 }
 952
 953
 954 //===----------------------------------------------------------------------===//
 955 //                             Local Splitting
 956 //===----------------------------------------------------------------------===//
 957
 958
 959 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
 960 /// in order to use PhysReg between two entries in SA->UseSlots.
 961 ///
 962 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
 963 ///
 964 void RAGreedy::calcGapWeights(unsigned PhysReg,
 965                               SmallVectorImpl<float> &GapWeight) {
 966   assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
 967   const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
 968   const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
 969   const unsigned NumGaps = Uses.size()-1;
 970
 971   // Start and end points for the interference check.
 972   SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
 973   SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
 974
 975   GapWeight.assign(NumGaps, 0.0f);
 976
 977   // Add interference from each overlapping register.
 978   for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
 979     if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
 980            .checkInterference())
 981       continue;
 982
 983     // We know that VirtReg is a continuous interval from FirstUse to LastUse,
 984     // so we don't need InterferenceQuery.
 985     //
 986     // Interference that overlaps an instruction is counted in both gaps
 987     // surrounding the instruction. The exception is interference before
 988     // StartIdx and after StopIdx.
 989     //
 990     LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
 991     for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
 992       // Skip the gaps before IntI.
 993       while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
 994         if (++Gap == NumGaps)
 995           break;
 996       if (Gap == NumGaps)
 997         break;
 998
 999       // Update the gaps covered by IntI.
1000       const float weight = IntI.value()->weight;
1001       for (; Gap != NumGaps; ++Gap) {
1002         GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1003         if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1004           break;
1005       }
1006       if (Gap == NumGaps)
1007         break;
1008     }
1009   }
1010 }
1011
1012 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
1013 /// before MI that has a slot index. If MI is the first mapped instruction in
1014 /// its block, return the block start index instead.
1015 ///
1016 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
1017   assert(MI && "Missing MachineInstr");
1018   const MachineBasicBlock *MBB = MI->getParent();
1019   MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
1020   while (I != B)
1021     if (!(--I)->isDebugValue() && !I->isCopy())
1022       return Indexes->getInstructionIndex(I);
1023   return Indexes->getMBBStartIdx(MBB);
1024 }
1025
1026 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
1027 /// real non-copy instruction for each instruction in SA->UseSlots.
1028 ///
1029 void RAGreedy::calcPrevSlots() {
1030   const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1031   PrevSlot.clear();
1032   PrevSlot.reserve(Uses.size());
1033   for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
1034     const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
1035     PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
1036   }
1037 }
1038
1039 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
1040 /// be beneficial to split before UseSlots[i].
1041 ///
1042 /// 0 is always a valid split point
1043 unsigned RAGreedy::nextSplitPoint(unsigned i) {
1044   const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1045   const unsigned Size = Uses.size();
1046   assert(i != Size && "No split points after the end");
1047   // Allow split before i when Uses[i] is not adjacent to the previous use.
1048   while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
1049     ;
1050   return i;
1051 }
1052
1053 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1054 /// basic block.
1055 ///
1056 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1057                                  SmallVectorImpl<LiveInterval*> &NewVRegs) {
1058   assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1059   const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1060
1061   // Note that it is possible to have an interval that is live-in or live-out
1062   // while only covering a single block - A phi-def can use undef values from
1063   // predecessors, and the block could be a single-block loop.
1064   // We don't bother doing anything clever about such a case, we simply assume
1065   // that the interval is continuous from FirstUse to LastUse. We should make
1066   // sure that we don't do anything illegal to such an interval, though.
1067
1068   const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1069   if (Uses.size() <= 2)
1070     return 0;
1071   const unsigned NumGaps = Uses.size()-1;
1072
1073   DEBUG({
1074     dbgs() << "tryLocalSplit: ";
1075     for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1076       dbgs() << ' ' << SA->UseSlots[i];
1077     dbgs() << '\n';
1078   });
1079
1080   // For every use, find the previous mapped non-copy instruction.
1081   // We use this to detect valid split points, and to estimate new interval
1082   // sizes.
1083   calcPrevSlots();
1084
1085   unsigned BestBefore = NumGaps;
1086   unsigned BestAfter = 0;
1087   float BestDiff = 0;
1088
1089   const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1090   SmallVector<float, 8> GapWeight;
1091
1092   Order.rewind();
1093   while (unsigned PhysReg = Order.next()) {
1094     // Keep track of the largest spill weight that would need to be evicted in
1095     // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1096     calcGapWeights(PhysReg, GapWeight);
1097
1098     // Try to find the best sequence of gaps to close.
1099     // The new spill weight must be larger than any gap interference.
1100
1101     // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1102     unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
1103
1104     // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1105     // It is the spill weight that needs to be evicted.
1106     float MaxGap = GapWeight[0];
1107     for (unsigned i = 1; i != SplitAfter; ++i)
1108       MaxGap = std::max(MaxGap, GapWeight[i]);
1109
1110     for (;;) {
1111       // Live before/after split?
1112       const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1113       const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1114
1115       DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1116                    << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1117                    << " i=" << MaxGap);
1118
1119       // Stop before the interval gets so big we wouldn't be making progress.
1120       if (!LiveBefore && !LiveAfter) {
1121         DEBUG(dbgs() << " all\n");
1122         break;
1123       }
1124       // Should the interval be extended or shrunk?
1125       bool Shrink = true;
1126       if (MaxGap < HUGE_VALF) {
1127         // Estimate the new spill weight.
1128         //
1129         // Each instruction reads and writes the register, except the first
1130         // instr doesn't read when !FirstLive, and the last instr doesn't write
1131         // when !LastLive.
1132         //
1133         // We will be inserting copies before and after, so the total number of
1134         // reads and writes is 2 * EstUses.
1135         //
1136         const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
1137                                  2*(LiveBefore + LiveAfter);
1138
1139         // Try to guess the size of the new interval. This should be trivial,
1140         // but the slot index of an inserted copy can be a lot smaller than the
1141         // instruction it is inserted before if there are many dead indexes
1142         // between them.
1143         //
1144         // We measure the distance from the instruction before SplitBefore to
1145         // get a conservative estimate.
1146         //
1147         // The final distance can still be different if inserting copies
1148         // triggers a slot index renumbering.
1149         //
1150         const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1151                               PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1152         // Would this split be possible to allocate?
1153         // Never allocate all gaps, we wouldn't be making progress.
1154         float Diff = EstWeight - MaxGap;
1155         DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1156         if (Diff > 0) {
1157           Shrink = false;
1158           if (Diff > BestDiff) {
1159             DEBUG(dbgs() << " (best)");
1160             BestDiff = Diff;
1161             BestBefore = SplitBefore;
1162             BestAfter = SplitAfter;
1163           }
1164         }
1165       }
1166
1167       // Try to shrink.
1168       if (Shrink) {
1169         SplitBefore = nextSplitPoint(SplitBefore);
1170         if (SplitBefore < SplitAfter) {
1171           DEBUG(dbgs() << " shrink\n");
1172           // Recompute the max when necessary.
1173           if (GapWeight[SplitBefore - 1] >= MaxGap) {
1174             MaxGap = GapWeight[SplitBefore];
1175             for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1176               MaxGap = std::max(MaxGap, GapWeight[i]);
1177           }
1178           continue;
1179         }
1180         MaxGap = 0;
1181       }
1182
1183       // Try to extend the interval.
1184       if (SplitAfter >= NumGaps) {
1185         DEBUG(dbgs() << " end\n");
1186         break;
1187       }
1188
1189       DEBUG(dbgs() << " extend\n");
1190       for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1191            SplitAfter != e; ++SplitAfter)
1192         MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1193           continue;
1194     }
1195   }
1196
1197   // Didn't find any candidates?
1198   if (BestBefore == NumGaps)
1199     return 0;
1200
1201   DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1202                << '-' << Uses[BestAfter] << ", " << BestDiff
1203                << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1204
1205   LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1206   SE->reset(LREdit);
1207
1208   SE->openIntv();
1209   SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1210   SlotIndex SegStop  = SE->leaveIntvAfter(Uses[BestAfter]);
1211   SE->useIntv(SegStart, SegStop);
1212   SE->finish();
1213   setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1214   ++NumLocalSplits;
1215
1216   return 0;
1217 }
1218
1219 //===----------------------------------------------------------------------===//
1220 //                          Live Range Splitting
1221 //===----------------------------------------------------------------------===//
1222
1223 /// trySplit - Try to split VirtReg or one of its interferences, making it
1224 /// assignable.
1225 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1226 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1227                             SmallVectorImpl<LiveInterval*>&NewVRegs) {
1228   // Local intervals are handled separately.
1229   if (LIS->intervalIsInOneMBB(VirtReg)) {
1230     NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1231     SA->analyze(&VirtReg);
1232     return tryLocalSplit(VirtReg, Order, NewVRegs);
1233   }
1234
1235   NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1236
1237   // Don't iterate global splitting.
1238   // Move straight to spilling if this range was produced by a global split.
1239   if (getStage(VirtReg) >= RS_Global)
1240     return 0;
1241
1242   SA->analyze(&VirtReg);
1243
1244   // First try to split around a region spanning multiple blocks.
1245   unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1246   if (PhysReg || !NewVRegs.empty())
1247     return PhysReg;
1248
1249   // Then isolate blocks with multiple uses.
1250   SplitAnalysis::BlockPtrSet Blocks;
1251   if (SA->getMultiUseBlocks(Blocks)) {
1252     LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1253     SE->reset(LREdit);
1254     SE->splitSingleBlocks(Blocks);
1255     setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global);
1256     if (VerifyEnabled)
1257       MF->verify(this, "After splitting live range around basic blocks");
1258   }
1259
1260   // Don't assign any physregs.
1261   return 0;
1262 }
1263
1264
1265 //===----------------------------------------------------------------------===//
1266 //                            Main Entry Point
1267 //===----------------------------------------------------------------------===//
1268
1269 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1270                                  SmallVectorImpl<LiveInterval*> &NewVRegs) {
1271   // First try assigning a free register.
1272   AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1273   if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1274     return PhysReg;
1275
1276   if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1277     return PhysReg;
1278
1279   assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1280
1281   // The first time we see a live range, don't try to split or spill.
1282   // Wait until the second time, when all smaller ranges have been allocated.
1283   // This gives a better picture of the interference to split around.
1284   LiveRangeStage Stage = getStage(VirtReg);
1285   if (Stage == RS_First) {
1286     LRStage[VirtReg.reg] = RS_Second;
1287     DEBUG(dbgs() << "wait for second round\n");
1288     NewVRegs.push_back(&VirtReg);
1289     return 0;
1290   }
1291
1292   assert(Stage < RS_Spill && "Cannot allocate after spilling");
1293
1294   // Try splitting VirtReg or interferences.
1295   unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1296   if (PhysReg || !NewVRegs.empty())
1297     return PhysReg;
1298
1299   // Finally spill VirtReg itself.
1300   NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1301   LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1302   spiller().spill(LRE);
1303   setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
1304
1305   if (VerifyEnabled)
1306     MF->verify(this, "After spilling");
1307
1308   // The live virtual register requesting allocation was spilled, so tell
1309   // the caller not to allocate anything during this round.
1310   return 0;
1311 }
1312
1313 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1314   DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1315                << "********** Function: "
1316                << ((Value*)mf.getFunction())->getName() << '\n');
1317
1318   MF = &mf;
1319   if (VerifyEnabled)
1320     MF->verify(this, "Before greedy register allocator");
1321
1322   RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1323   Indexes = &getAnalysis<SlotIndexes>();
1324   DomTree = &getAnalysis<MachineDominatorTree>();
1325   ReservedRegs = TRI->getReservedRegs(*MF);
1326   SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1327   Loops = &getAnalysis<MachineLoopInfo>();
1328   LoopRanges = &getAnalysis<MachineLoopRanges>();
1329   Bundles = &getAnalysis<EdgeBundles>();
1330   SpillPlacer = &getAnalysis<SpillPlacement>();
1331
1332   SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1333   SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1334   LRStage.clear();
1335   LRStage.resize(MRI->getNumVirtRegs());
1336   IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1337
1338   allocatePhysRegs();
1339   addMBBLiveIns(MF);
1340   LIS->addKillFlags();
1341
1342   // Run rewriter
1343   {
1344     NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1345     VRM->rewrite(Indexes);
1346   }
1347
1348   // Write out new DBG_VALUE instructions.
1349   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
1350
1351   // The pass output is in VirtRegMap. Release all the transient data.
1352   releaseMemory();
1353
1354   return true;
1355 }