lib/CodeGen/TargetInstrInfoImpl.cpp

   1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetInstrInfoImpl class, it just provides default
  11 // implementations of various methods.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "llvm/Target/TargetInstrInfo.h"
  16 #include "llvm/Target/TargetLowering.h"
  17 #include "llvm/Target/TargetMachine.h"
  18 #include "llvm/Target/TargetRegisterInfo.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineMemOperand.h"
  24 #include "llvm/CodeGen/MachineRegisterInfo.h"
  25 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
  26 #include "llvm/CodeGen/PseudoSourceValue.h"
  27 #include "llvm/Support/CommandLine.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/raw_ostream.h"
  31 using namespace llvm;
  32
  33 static cl::opt<bool> DisableHazardRecognizer(
  34   "disable-sched-hazard", cl::Hidden, cl::init(false),
  35   cl::desc("Disable hazard detection during preRA scheduling"));
  36
  37 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
  38 /// after it, replacing it with an unconditional branch to NewDest.
  39 void
  40 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  41                                              MachineBasicBlock *NewDest) const {
  42   MachineBasicBlock *MBB = Tail->getParent();
  43
  44   // Remove all the old successors of MBB from the CFG.
  45   while (!MBB->succ_empty())
  46     MBB->removeSuccessor(MBB->succ_begin());
  47
  48   // Remove all the dead instructions from the end of MBB.
  49   MBB->erase(Tail, MBB->end());
  50
  51   // If MBB isn't immediately before MBB, insert a branch to it.
  52   if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
  53     InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
  54                  Tail->getDebugLoc());
  55   MBB->addSuccessor(NewDest);
  56 }
  57
  58 // commuteInstruction - The default implementation of this method just exchanges
  59 // the two operands returned by findCommutedOpIndices.
  60 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
  61                                                       bool NewMI) const {
  62   const TargetInstrDesc &TID = MI->getDesc();
  63   bool HasDef = TID.getNumDefs();
  64   if (HasDef && !MI->getOperand(0).isReg())
  65     // No idea how to commute this instruction. Target should implement its own.
  66     return 0;
  67   unsigned Idx1, Idx2;
  68   if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
  69     std::string msg;
  70     raw_string_ostream Msg(msg);
  71     Msg << "Don't know how to commute: " << *MI;
  72     report_fatal_error(Msg.str());
  73   }
  74
  75   assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
  76          "This only knows how to commute register operands so far");
  77   unsigned Reg1 = MI->getOperand(Idx1).getReg();
  78   unsigned Reg2 = MI->getOperand(Idx2).getReg();
  79   bool Reg1IsKill = MI->getOperand(Idx1).isKill();
  80   bool Reg2IsKill = MI->getOperand(Idx2).isKill();
  81   bool ChangeReg0 = false;
  82   if (HasDef && MI->getOperand(0).getReg() == Reg1) {
  83     // Must be two address instruction!
  84     assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
  85            "Expecting a two-address instruction!");
  86     Reg2IsKill = false;
  87     ChangeReg0 = true;
  88   }
  89
  90   if (NewMI) {
  91     // Create a new instruction.
  92     unsigned Reg0 = HasDef
  93       ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
  94     bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
  95     MachineFunction &MF = *MI->getParent()->getParent();
  96     if (HasDef)
  97       return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
  98         .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
  99         .addReg(Reg2, getKillRegState(Reg2IsKill))
 100         .addReg(Reg1, getKillRegState(Reg2IsKill));
 101     else
 102       return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
 103         .addReg(Reg2, getKillRegState(Reg2IsKill))
 104         .addReg(Reg1, getKillRegState(Reg2IsKill));
 105   }
 106
 107   if (ChangeReg0)
 108     MI->getOperand(0).setReg(Reg2);
 109   MI->getOperand(Idx2).setReg(Reg1);
 110   MI->getOperand(Idx1).setReg(Reg2);
 111   MI->getOperand(Idx2).setIsKill(Reg1IsKill);
 112   MI->getOperand(Idx1).setIsKill(Reg2IsKill);
 113   return MI;
 114 }
 115
 116 /// findCommutedOpIndices - If specified MI is commutable, return the two
 117 /// operand indices that would swap value. Return true if the instruction
 118 /// is not in a form which this routine understands.
 119 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
 120                                                 unsigned &SrcOpIdx1,
 121                                                 unsigned &SrcOpIdx2) const {
 122   const TargetInstrDesc &TID = MI->getDesc();
 123   if (!TID.isCommutable())
 124     return false;
 125   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
 126   // is not true, then the target must implement this.
 127   SrcOpIdx1 = TID.getNumDefs();
 128   SrcOpIdx2 = SrcOpIdx1 + 1;
 129   if (!MI->getOperand(SrcOpIdx1).isReg() ||
 130       !MI->getOperand(SrcOpIdx2).isReg())
 131     // No idea.
 132     return false;
 133   return true;
 134 }
 135
 136
 137 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
 138                             const SmallVectorImpl<MachineOperand> &Pred) const {
 139   bool MadeChange = false;
 140   const TargetInstrDesc &TID = MI->getDesc();
 141   if (!TID.isPredicable())
 142     return false;
 143
 144   for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
 145     if (TID.OpInfo[i].isPredicate()) {
 146       MachineOperand &MO = MI->getOperand(i);
 147       if (MO.isReg()) {
 148         MO.setReg(Pred[j].getReg());
 149         MadeChange = true;
 150       } else if (MO.isImm()) {
 151         MO.setImm(Pred[j].getImm());
 152         MadeChange = true;
 153       } else if (MO.isMBB()) {
 154         MO.setMBB(Pred[j].getMBB());
 155         MadeChange = true;
 156       }
 157       ++j;
 158     }
 159   }
 160   return MadeChange;
 161 }
 162
 163 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
 164                                         MachineBasicBlock::iterator I,
 165                                         unsigned DestReg,
 166                                         unsigned SubIdx,
 167                                         const MachineInstr *Orig,
 168                                         const TargetRegisterInfo &TRI) const {
 169   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
 170   MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
 171   MBB.insert(I, MI);
 172 }
 173
 174 bool
 175 TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
 176                                       const MachineInstr *MI1,
 177                                       const MachineRegisterInfo *MRI) const {
 178   return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
 179 }
 180
 181 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
 182                                              MachineFunction &MF) const {
 183   assert(!Orig->getDesc().isNotDuplicable() &&
 184          "Instruction cannot be duplicated");
 185   return MF.CloneMachineInstr(Orig);
 186 }
 187
 188 // If the COPY instruction in MI can be folded to a stack operation, return
 189 // the register class to use.
 190 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
 191                                               unsigned FoldIdx) {
 192   assert(MI->isCopy() && "MI must be a COPY instruction");
 193   if (MI->getNumOperands() != 2)
 194     return 0;
 195   assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
 196
 197   const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
 198   const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
 199
 200   if (FoldOp.getSubReg() || LiveOp.getSubReg())
 201     return 0;
 202
 203   unsigned FoldReg = FoldOp.getReg();
 204   unsigned LiveReg = LiveOp.getReg();
 205
 206   assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
 207          "Cannot fold physregs");
 208
 209   const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
 210   const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
 211
 212   if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
 213     return RC->contains(LiveOp.getReg()) ? RC : 0;
 214
 215   const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg);
 216   if (RC == LiveRC || RC->hasSubClass(LiveRC))
 217     return RC;
 218
 219   // FIXME: Allow folding when register classes are memory compatible.
 220   return 0;
 221 }
 222
 223 bool TargetInstrInfoImpl::
 224 canFoldMemoryOperand(const MachineInstr *MI,
 225                      const SmallVectorImpl<unsigned> &Ops) const {
 226   return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
 227 }
 228
 229 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
 230 /// slot into the specified machine instruction for the specified operand(s).
 231 /// If this is possible, a new instruction is returned with the specified
 232 /// operand folded, otherwise NULL is returned. The client is responsible for
 233 /// removing the old instruction and adding the new one in the instruction
 234 /// stream.
 235 MachineInstr*
 236 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
 237                                    const SmallVectorImpl<unsigned> &Ops,
 238                                    int FI) const {
 239   unsigned Flags = 0;
 240   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 241     if (MI->getOperand(Ops[i]).isDef())
 242       Flags |= MachineMemOperand::MOStore;
 243     else
 244       Flags |= MachineMemOperand::MOLoad;
 245
 246   MachineBasicBlock *MBB = MI->getParent();
 247   assert(MBB && "foldMemoryOperand needs an inserted instruction");
 248   MachineFunction &MF = *MBB->getParent();
 249
 250   // Ask the target to do the actual folding.
 251   if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
 252     // Add a memory operand, foldMemoryOperandImpl doesn't do that.
 253     assert((!(Flags & MachineMemOperand::MOStore) ||
 254             NewMI->getDesc().mayStore()) &&
 255            "Folded a def to a non-store!");
 256     assert((!(Flags & MachineMemOperand::MOLoad) ||
 257             NewMI->getDesc().mayLoad()) &&
 258            "Folded a use to a non-load!");
 259     const MachineFrameInfo &MFI = *MF.getFrameInfo();
 260     assert(MFI.getObjectOffset(FI) != -1);
 261     MachineMemOperand *MMO =
 262       MF.getMachineMemOperand(
 263                     MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
 264                               Flags, MFI.getObjectSize(FI),
 265                               MFI.getObjectAlignment(FI));
 266     NewMI->addMemOperand(MF, MMO);
 267
 268     // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
 269     return MBB->insert(MI, NewMI);
 270   }
 271
 272   // Straight COPY may fold as load/store.
 273   if (!MI->isCopy() || Ops.size() != 1)
 274     return 0;
 275
 276   const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
 277   if (!RC)
 278     return 0;
 279
 280   const MachineOperand &MO = MI->getOperand(1-Ops[0]);
 281   MachineBasicBlock::iterator Pos = MI;
 282   const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
 283
 284   if (Flags == MachineMemOperand::MOStore)
 285     storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
 286   else
 287     loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
 288   return --Pos;
 289 }
 290
 291 /// foldMemoryOperand - Same as the previous version except it allows folding
 292 /// of any load and store from / to any address, not just from a specific
 293 /// stack slot.
 294 MachineInstr*
 295 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
 296                                    const SmallVectorImpl<unsigned> &Ops,
 297                                    MachineInstr* LoadMI) const {
 298   assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
 299 #ifndef NDEBUG
 300   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 301     assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
 302 #endif
 303   MachineBasicBlock &MBB = *MI->getParent();
 304   MachineFunction &MF = *MBB.getParent();
 305
 306   // Ask the target to do the actual folding.
 307   MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
 308   if (!NewMI) return 0;
 309
 310   NewMI = MBB.insert(MI, NewMI);
 311
 312   // Copy the memoperands from the load to the folded instruction.
 313   NewMI->setMemRefs(LoadMI->memoperands_begin(),
 314                     LoadMI->memoperands_end());
 315
 316   return NewMI;
 317 }
 318
 319 bool TargetInstrInfo::
 320 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
 321                                          AliasAnalysis *AA) const {
 322   const MachineFunction &MF = *MI->getParent()->getParent();
 323   const MachineRegisterInfo &MRI = MF.getRegInfo();
 324   const TargetMachine &TM = MF.getTarget();
 325   const TargetInstrInfo &TII = *TM.getInstrInfo();
 326   const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
 327
 328   // A load from a fixed stack slot can be rematerialized. This may be
 329   // redundant with subsequent checks, but it's target-independent,
 330   // simple, and a common case.
 331   int FrameIdx = 0;
 332   if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
 333       MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
 334     return true;
 335
 336   const TargetInstrDesc &TID = MI->getDesc();
 337
 338   // Avoid instructions obviously unsafe for remat.
 339   if (TID.isNotDuplicable() || TID.mayStore() ||
 340       MI->hasUnmodeledSideEffects())
 341     return false;
 342
 343   // Don't remat inline asm. We have no idea how expensive it is
 344   // even if it's side effect free.
 345   if (MI->isInlineAsm())
 346     return false;
 347
 348   // Avoid instructions which load from potentially varying memory.
 349   if (TID.mayLoad() && !MI->isInvariantLoad(AA))
 350     return false;
 351
 352   // If any of the registers accessed are non-constant, conservatively assume
 353   // the instruction is not rematerializable.
 354   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 355     const MachineOperand &MO = MI->getOperand(i);
 356     if (!MO.isReg()) continue;
 357     unsigned Reg = MO.getReg();
 358     if (Reg == 0)
 359       continue;
 360
 361     // Check for a well-behaved physical register.
 362     if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 363       if (MO.isUse()) {
 364         // If the physreg has no defs anywhere, it's just an ambient register
 365         // and we can freely move its uses. Alternatively, if it's allocatable,
 366         // it could get allocated to something with a def during allocation.
 367         if (!MRI.def_empty(Reg))
 368           return false;
 369         BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
 370         if (AllocatableRegs.test(Reg))
 371           return false;
 372         // Check for a def among the register's aliases too.
 373         for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
 374           unsigned AliasReg = *Alias;
 375           if (!MRI.def_empty(AliasReg))
 376             return false;
 377           if (AllocatableRegs.test(AliasReg))
 378             return false;
 379         }
 380       } else {
 381         // A physreg def. We can't remat it.
 382         return false;
 383       }
 384       continue;
 385     }
 386
 387     // Only allow one virtual-register def, and that in the first operand.
 388     if (MO.isDef() != (i == 0))
 389       return false;
 390
 391     // Don't allow any virtual-register uses. Rematting an instruction with
 392     // virtual register uses would length the live ranges of the uses, which
 393     // is not necessarily a good idea, certainly not "trivial".
 394     if (MO.isUse())
 395       return false;
 396   }
 397
 398   // Everything checked out.
 399   return true;
 400 }
 401
 402 /// isSchedulingBoundary - Test if the given instruction should be
 403 /// considered a scheduling boundary. This primarily includes labels
 404 /// and terminators.
 405 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
 406                                                const MachineBasicBlock *MBB,
 407                                                const MachineFunction &MF) const{
 408   // Terminators and labels can't be scheduled around.
 409   if (MI->getDesc().isTerminator() || MI->isLabel())
 410     return true;
 411
 412   // Don't attempt to schedule around any instruction that defines
 413   // a stack-oriented pointer, as it's unlikely to be profitable. This
 414   // saves compile time, because it doesn't require every single
 415   // stack slot reference to depend on the instruction that does the
 416   // modification.
 417   const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
 418   if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
 419     return true;
 420
 421   return false;
 422 }
 423
 424 // Provide a global flag for disabling the PreRA hazard recognizer that targets
 425 // may choose to honor.
 426 bool TargetInstrInfoImpl::usePreRAHazardRecognizer() const {
 427   return !DisableHazardRecognizer;
 428 }
 429
 430 // Default implementation of CreateTargetRAHazardRecognizer.
 431 ScheduleHazardRecognizer *TargetInstrInfoImpl::
 432 CreateTargetHazardRecognizer(const TargetMachine *TM,
 433                              const ScheduleDAG *DAG) const {
 434   // Dummy hazard recognizer allows all instructions to issue.
 435   return new ScheduleHazardRecognizer();
 436 }
 437
 438 // Default implementation of CreateTargetPostRAHazardRecognizer.
 439 ScheduleHazardRecognizer *TargetInstrInfoImpl::
 440 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 441                                    const ScheduleDAG *DAG) const {
 442   return (ScheduleHazardRecognizer *)
 443     new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
 444 }