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20 <body>
22 <h1>
23 The LLVM Target-Independent Code Generator
24 </h1>
26 <ol>
28 <ul>
31 generator</a></li>
33 </ul>
34 </li>
36 <ul>
45 </ul>
46 </li>
48 <ul>
51 class</a></li>
53 </ul>
54 </li>
56 <ul>
62 </ul>
63 </li>
65 <ul>
67 <ul>
70 Process</a></li>
72 Construction</a></li>
76 Phase: the DAG Combiner</a></li>
79 Phase</a></li>
81 SelectionDAG</a></li>
82 </ul></li>
84 <ul>
87 </ul></li>
89 <ul>
91 LLVM</a></li>
93 registers</a></li>
98 </ul></li>
100 </ul>
101 </li>
105 <ul>
111 <ul>
116 </ul></li>
117 </ul></li>
119 </ol>
123 </div>
127 </div>
129 <!-- *********************************************************************** -->
130 <h2>
132 </h2>
133 <!-- *********************************************************************** -->
135 <div>
137 <p>The LLVM target-independent code generator is a framework that provides a
138 suite of reusable components for translating the LLVM internal representation
139 to the machine code for a specified target—either in assembly form
140 (suitable for a static compiler) or in binary machine code format (usable for
141 a JIT compiler). The LLVM target-independent code generator consists of six
142 main components:</p>
144 <ol>
146 capture important properties about various aspects of the machine,
147 independently of how they will be used. These interfaces are defined in
151 generated</a> for a target. These classes are intended to be abstract
155 exposed.</li>
157 <li>Classes and algorithms used to represent code as the object file level,
159 constructs like labels, sections, and instructions. At this level,
163 various phases of native code generation (register allocation, scheduling,
164 stack frame representation, etc). This code lives
168 interfaces</a> for particular targets. These machine descriptions make
169 use of the components provided by LLVM, and can optionally provide custom
170 target-specific passes, to build complete code generators for a specific
175 structure to interface for target-specific issues. The code for the
177 </ol>
179 <p>Depending on which part of the code generator you are interested in working
180 on, different pieces of this will be useful to you. In any case, you should
183 want to add a backend for a new target, you will need
186 representation</a>. If you are interested in implementing a
188 depend on the target-description and machine code representation classes,
189 ensuring that it is portable.</p>
191 <!-- ======================================================================= -->
192 <h3>
194 </h3>
196 <div>
198 <p>The two pieces of the LLVM code generator are the high-level interface to the
199 code generator and the set of reusable components that can be used to build
200 target-specific backends. The two most important interfaces
203 required to be defined for a backend to fit into the LLVM system, but the
204 others must be defined if the reusable code generator components are going to
205 be used.</p>
207 <p>This design has two important implications. The first is that LLVM can
208 support completely non-traditional code generation targets. For example, the
209 C backend does not require register allocation, instruction selection, or any
210 of the other standard components provided by the system. As such, it only
211 implements these two interfaces, and does its own thing. Another example of
212 a code generator like this is a (purely hypothetical) backend that converts
213 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
215 <p>This design also implies that it is possible to design and implement
216 radically different code generators in the LLVM system that do not make use
217 of any of the built-in components. Doing so is not recommended at all, but
218 could be required for radically different targets that do not fit into the
219 LLVM machine description model: FPGAs for example.</p>
221 </div>
223 <!-- ======================================================================= -->
224 <h3>
226 </h3>
228 <div>
230 <p>The LLVM target-independent code generator is designed to support efficient
231 and quality code generation for standard register-based microprocessors.
232 Code generation in this model is divided into the following stages:</p>
234 <ol>
236 determines an efficient way to express the input LLVM code in the target
237 instruction set. This stage produces the initial code for the program in
238 the target instruction set, then makes use of virtual registers in SSA
239 form and physical registers that represent any required register
240 assignments due to target constraints or calling conventions. This step
241 turns the LLVM code into a DAG of target instructions.</li>
244 This phase takes the DAG of target instructions produced by the
245 instruction selection phase, determines an ordering of the instructions,
246 then emits the instructions
249 selection section</a> because it operates on
253 This optional stage consists of a series of machine-code optimizations
254 that operate on the SSA-form produced by the instruction selector.
255 Optimizations like modulo-scheduling or peephole optimization work
256 here.</li>
259 is transformed from an infinite virtual register file in SSA form to the
260 concrete register file used by the target. This phase introduces spill
261 code and eliminates all virtual register references from the program.</li>
264 the machine code has been generated for the function and the amount of
265 stack space required is known (used for LLVM alloca's and spill slots),
266 the prolog and epilog code for the function can be inserted and "abstract
267 stack location references" can be eliminated. This stage is responsible
268 for implementing optimizations like frame-pointer elimination and stack
269 packing.</li>
272 Optimizations that operate on "final" machine code can go here, such as
273 spill code scheduling and peephole optimizations.</li>
276 actually puts out the code for the current function, either in the target
277 assembler format or in machine code.</li>
278 </ol>
280 <p>The code generator is based on the assumption that the instruction selector
281 will use an optimal pattern matching selector to create high-quality
282 sequences of native instructions. Alternative code generator designs based
283 on pattern expansion and aggressive iterative peephole optimization are much
284 slower. This design permits efficient compilation (important for JIT
285 environments) and aggressive optimization (used when generating code offline)
286 by allowing components of varying levels of sophistication to be used for any
287 step of compilation.</p>
289 <p>In addition to these stages, target implementations can insert arbitrary
290 target-specific passes into the flow. For example, the X86 target uses a
291 special pass to handle the 80x87 floating point stack architecture. Other
292 targets with unusual requirements can be supported with custom passes as
293 needed.</p>
295 </div>
297 <!-- ======================================================================= -->
298 <h3>
300 </h3>
302 <div>
304 <p>The target description classes require a detailed description of the target
305 architecture. These target descriptions often have a large amount of common
308 commonality to be factored out, the LLVM code generator uses
310 chunks of the target machine, which allows the use of domain-specific and
311 target-specific abstractions to reduce the amount of repetition.</p>
313 <p>As LLVM continues to be developed and refined, we plan to move more and more
315 number of advantages. The most important is that it makes it easier to port
316 LLVM because it reduces the amount of C++ code that has to be written, and
317 the surface area of the code generator that needs to be understood before
318 someone can get something working. Second, it makes it easier to change
319 things. In particular, if tables and other things are all emitted
321 update all of the targets to a new interface.</p>
323 </div>
325 </div>
327 <!-- *********************************************************************** -->
328 <h2>
330 </h2>
331 <!-- *********************************************************************** -->
333 <div>
335 <p>The LLVM target description classes (located in the
337 the target machine independent of any particular client. These classes are
339 instructions and registers it has), and do not incorporate any particular
340 pieces of code generation algorithms.</p>
342 <p>All of the target description classes (except the
344 subclassed by the concrete target implementation, and have virtual methods
345 implemented. To get to these implementations, the
347 that should be implemented by the target.</p>
349 <!-- ======================================================================= -->
350 <h3>
352 </h3>
354 <div>
357 access the target-specific implementations of the various target description
360 designed to be specialized by a concrete target implementation
362 methods. The only required target description class is
364 generator components are to be used, the other interfaces should be
365 implemented as well.</p>
367 </div>
369 <!-- ======================================================================= -->
370 <h3>
372 </h3>
374 <div>
377 and it is the only class that is not extensible (you cannot derived a new
379 target lays out memory for structures, the alignment requirements for various
380 data types, the size of pointers in the target, and whether the target is
381 little-endian or big-endian.</p>
383 </div>
385 <!-- ======================================================================= -->
386 <h3>
388 </h3>
390 <div>
393 selectors primarily to describe how LLVM code should be lowered to
394 SelectionDAG operations. Among other things, this class indicates:</p>
396 <ul>
405 <li>various high-level characteristics, like whether it is profitable to turn
406 division by a constant into a multiplication sequence</li>
407 </ul>
409 </div>
411 <!-- ======================================================================= -->
412 <h3>
414 </h3>
416 <div>
419 of the target and any interactions between the registers.</p>
421 <p>Registers in the code generator are represented in the code generator by
422 unsigned integers. Physical registers (those that actually exist in the
423 target description) are unique small numbers, and virtual registers are
426 <p>Each register in the processor description has an associated
428 register (used for assembly output and debugging dumps) and a set of aliases
429 (used to indicate whether one register overlaps with another).</p>
432 class exposes a set of processor specific register classes (instances of the
434 registers that have the same properties (for example, they are all 32-bit
435 integer registers). Each SSA virtual register created by the instruction
436 selector has an associated register class. When the register allocator runs,
437 it replaces virtual registers with a physical register in the set.</p>
439 <p>The target-specific implementations of these classes is auto-generated from
441 register file.</p>
443 </div>
445 <!-- ======================================================================= -->
446 <h3>
448 </h3>
450 <div>
453 instructions supported by the target. It is essentially an array of
455 instruction the target supports. Descriptors define things like the mnemonic
456 for the opcode, the number of operands, the list of implicit register uses
457 and defs, whether the instruction has certain target-independent properties
458 (accesses memory, is commutable, etc), and holds any target-specific
459 flags.</p>
461 </div>
463 <!-- ======================================================================= -->
464 <h3>
466 </h3>
468 <div>
471 stack frame layout of the target. It holds the direction of stack growth, the
472 known stack alignment on entry to each function, and the offset to the local
473 area. The offset to the local area is the offset from the stack pointer on
474 function entry to the first location where function data (local variables,
475 spill locations) can be stored.</p>
477 </div>
479 <!-- ======================================================================= -->
480 <h3>
482 </h3>
484 <div>
487 specific chip set being targeted. A sub-target informs code generation of
488 which instructions are supported, instruction latencies and instruction
489 execution itinerary; i.e., which processing units are used, in what order,
490 and for how long.</p>
492 </div>
495 <!-- ======================================================================= -->
496 <h3>
498 </h3>
500 <div>
503 Just-In-Time code generator to perform target-specific activities, such as
506 method.</p>
508 </div>
510 </div>
512 <!-- *********************************************************************** -->
513 <h2>
515 </h2>
516 <!-- *********************************************************************** -->
518 <div>
520 <p>At the high-level, LLVM code is translated to a machine specific
521 representation formed out of
526 agnostic, representing instructions in their most abstract form: an opcode
527 and a series of operands. This representation is designed to support both an
528 SSA representation for machine code, as well as a register allocated, non-SSA
529 form.</p>
531 <!-- ======================================================================= -->
532 <h3>
534 </h3>
536 <div>
538 <p>Target machine instructions are represented as instances of the
540 representing machine instructions. In particular, it only keeps track of an
541 opcode number and a set of operands.</p>
543 <p>The opcode number is a simple unsigned integer that only has meaning to a
544 specific backend. All of the instructions for a target should be defined in
547 not have any information about how to interpret the instruction (i.e., what
548 the semantics of the instruction are); for that you must refer to the
551 <p>The operands of a machine instruction can be of several different types: a
552 register reference, a constant integer, a basic block reference, etc. In
553 addition, a machine operand should be marked as a def or a use of the value
554 (though only registers are allowed to be defs).</p>
556 <p>By convention, the LLVM code generator orders instruction operands so that
557 all register definitions come before the register uses, even on architectures
558 that are normally printed in other orders. For example, the SPARC add
560 and stores the result into the "%i3" register. In the LLVM code generator,
561 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
562 destination first.</p>
564 <p>Keeping destination (definition) operands at the beginning of the operand
565 list has several advantages. In particular, the debugging printer will print
566 the instruction like this:</p>
569 <pre>
570 %r3 = add %i1, %i2
571 </pre>
572 </div>
577 <!-- _______________________________________________________________________ -->
578 <h4>
580 </h4>
582 <div>
590 <pre>
592 // instruction. The '1' specifies how many operands will be added.
595 // Create the same instr, but insert it at the end of a basic block.
596 MachineBasicBlock &MBB = ...
599 // Create the same instr, but insert it before a specified iterator point.
600 MachineBasicBlock::iterator MBBI = ...
603 // Create a 'cmp Reg, 0' instruction, no destination reg.
605 // Create an 'sahf' instruction which takes no operands and stores nothing.
606 MI = BuildMI(X86::SAHF, 0);
608 // Create a self looping branch instruction.
610 </pre>
611 </div>
614 have to specify the number of operands that the machine instruction will
615 take. This allows for efficient memory allocation. You also need to specify
616 if operands default to be uses of values, not definitions. If you need to
617 add a definition operand (other than the optional destination register), you
618 must explicitly mark it as such:</p>
621 <pre>
622 MI.addReg(Reg, RegState::Define);
623 </pre>
624 </div>
626 </div>
628 <!-- _______________________________________________________________________ -->
629 <h4>
631 </h4>
633 <div>
635 <p>One important issue that the code generator needs to be aware of is the
636 presence of fixed registers. In particular, there are often places in the
638 particular value to be in a particular register. This can occur due to
639 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
641 calling conventions. In any case, the instruction selector should emit code
642 that copies a virtual register into or out of a physical register when
643 needed.</p>
648 <pre>
649 define i32 @test(i32 %X, i32 %Y) {
650 %Z = udiv i32 %X, %Y
651 ret i32 %Z
652 }
653 </pre>
654 </div>
658 get this):</p>
661 <pre>
662 ;; Start of div
663 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
664 %reg1027 = sar %reg1024, 31
665 %EDX = mov %reg1027 ;; Sign extend X into EDX
666 idiv %reg1025 ;; Divide by Y (in reg1025)
667 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
669 ;; Start of ret
670 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
671 ret
672 </pre>
673 </div>
675 <p>By the end of code generation, the register allocator has coalesced the
676 registers and deleted the resultant identity moves producing the following
677 code:</p>
680 <pre>
681 ;; X is in EAX, Y is in ECX
682 mov %EAX, %EDX
683 sar %EDX, 31
684 idiv %ECX
685 ret
686 </pre>
687 </div>
689 <p>This approach is extremely general (if it can handle the X86 architecture, it
690 can handle anything!) and allows all of the target specific knowledge about
691 the instruction stream to be isolated in the instruction selector. Note that
692 physical registers should have a short lifetime for good code generation, and
693 all physical registers are assumed dead on entry to and exit from basic
694 blocks (before register allocation). Thus, if you need a value to be live
696 register.</p>
698 </div>
700 <!-- _______________________________________________________________________ -->
701 <h4>
703 </h4>
705 <div>
708 maintained in SSA-form until register allocation happens. For the most part,
709 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
710 become machine code PHI nodes, and virtual registers are only allowed to have
711 a single definition.</p>
713 <p>After register allocation, machine code is no longer in SSA-form because
714 there are no virtual registers left in the code.</p>
716 </div>
718 </div>
720 <!-- ======================================================================= -->
721 <h3>
723 </h3>
725 <div>
729 corresponds to the LLVM code input to the instruction selector, but there can
730 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
732 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
733 comes from.</p>
735 </div>
737 <!-- ======================================================================= -->
738 <h3>
740 </h3>
742 <div>
746 corresponds one-to-one with the LLVM function input to the instruction
747 selector. In addition to a list of basic blocks,
753 </div>
755 </div>
757 <!-- *********************************************************************** -->
758 <h2>
760 </h2>
761 <!-- *********************************************************************** -->
763 <div>
765 <p>
766 The MC Layer is used to represent and process code at the raw machine code
768 "global variables" or anything like that. At this level, LLVM handles things
769 like label names, machine instructions, and sections in the object file. The
770 code in this layer is used for a number of important purposes: the tail end of
771 the code generator uses it to write a .s or .o file, and it is also used by the
772 llvm-mc tool to implement standalone machine code assemblers and disassemblers.
773 </p>
775 <p>
776 This section describes some of the important classes. There are also a number
777 of important subsystems that interact at this layer, they are described later
778 in this manual.
779 </p>
781 <!-- ======================================================================= -->
782 <h3>
784 </h3>
786 <div>
788 <p>
789 MCStreamer is best thought of as an assembler API. It is an abstract API which
791 ELF .o file, etc) but whose API correspond directly to what you see in a .s
792 file. MCStreamer has one method per directive, such as EmitLabel,
793 EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
794 directly correspond to assembly level directives. It also has an
795 EmitInstruction method, which is used to output an MCInst to the streamer.
796 </p>
798 <p>
799 This API is most important for two clients: the llvm-mc stand-alone assembler is
800 effectively a parser that parses a line, then invokes a method on MCStreamer. In
802 generator lowers higher level LLVM IR and Machine* constructs down to the MC
803 layer, emitting directives through MCStreamer.</p>
805 <p>
806 On the implementation side of MCStreamer, there are two major implementations:
807 one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
808 file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
809 that prints out a directive for each method (e.g. EmitValue -> .byte), but
810 MCObjectStreamer implements a full assembler.
811 </p>
813 </div>
815 <!-- ======================================================================= -->
816 <h3>
818 </h3>
820 <div>
822 <p>
823 The MCContext class is the owner of a variety of uniqued data structures at the
824 MC layer, including symbols, sections, etc. As such, this is the class that you
825 interact with to create symbols and sections. This class can not be subclassed.
826 </p>
828 </div>
830 <!-- ======================================================================= -->
831 <h3>
833 </h3>
835 <div>
837 <p>
838 The MCSymbol class represents a symbol (aka label) in the assembly file. There
839 are two interesting kinds of symbols: assembler temporary symbols, and normal
840 symbols. Assembler temporary symbols are used and processed by the assembler
841 but are discarded when the object file is produced. The distinction is usually
842 represented by adding a prefix to the label, for example "L" labels are
843 assembler temporary labels in MachO.
844 </p>
846 <p>MCSymbols are created by MCContext and uniqued there. This means that
847 MCSymbols can be compared for pointer equivalence to find out if they are the
848 same symbol. Note that pointer inequality does not guarantee the labels will
849 end up at different addresses though. It's perfectly legal to output something
850 like this to the .s file:<p>
852 <pre>
853 foo:
854 bar:
855 .byte 4
856 </pre>
860 </div>
862 <!-- ======================================================================= -->
863 <h3>
865 </h3>
867 <div>
869 <p>
870 The MCSection class represents an object-file specific section. It is subclassed
873 by MCContext. The MCStreamer has a notion of the current section, which can be
874 changed with the SwitchToSection method (which corresponds to a ".section"
875 directive in a .s file).
876 </p>
878 </div>
880 <!-- ======================================================================= -->
881 <h3>
883 </h3>
885 <div>
887 <p>
888 The MCInst class is a target-independent representation of an instruction. It
890 that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
891 turn, is a simple discriminated union of three cases: 1) a simple immediate,
893 MCExpr.
894 </p>
896 <p>MCInst is the common currency used to represent machine instructions at the
897 MC layer. It is the type used by the instruction encoder, the instruction
898 printer, and the type generated by the assembly parser and disassembler.
899 </p>
901 </div>
903 </div>
905 <!-- *********************************************************************** -->
906 <h2>
908 </h2>
909 <!-- *********************************************************************** -->
911 <div>
913 <p>This section documents the phases described in the
915 It explains how they work and some of the rationale behind their design.</p>
917 <!-- ======================================================================= -->
918 <h3>
920 </h3>
922 <div>
924 <p>Instruction Selection is the process of translating LLVM code presented to
925 the code generator into target-specific machine instructions. There are
926 several well-known ways to do this in the literature. LLVM uses a
927 SelectionDAG based instruction selector.</p>
929 <p>Portions of the DAG instruction selector are generated from the target
932 there are still things that require custom C++ code.</p>
934 <!-- _______________________________________________________________________ -->
935 <h4>
937 </h4>
939 <div>
941 <p>The SelectionDAG provides an abstraction for code representation in a way
942 that is amenable to instruction selection using automatic techniques
943 (e.g. dynamic-programming based optimal pattern matching selectors). It is
944 also well-suited to other phases of code generation; in particular,
945 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
946 post-selection). Additionally, the SelectionDAG provides a host
947 representation where a large variety of very-low-level (but
949 performed; ones which require extensive information about the instructions
950 efficiently supported by the target.</p>
952 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
954 operation code (Opcode) that indicates what operation the node performs and
955 the operands to the operation. The various operation node types are
957 file.</p>
959 <p>Although most operations define a single value, each node in the graph may
960 define multiple values. For example, a combined div/rem operation will
961 define both the dividend and the remainder. Many other situations require
962 multiple values as well. Each node also has some number of operands, which
963 are edges to the node defining the used value. Because nodes may define
966 and result value being used, respectively. Each value produced by
968 indicating what the type of the value is.</p>
970 <p>SelectionDAGs contain two different kinds of values: those that represent
971 data flow and those that represent control flow dependencies. Data values
972 are simple edges with an integer or floating point value type. Control edges
974 These edges provide an ordering between nodes that have side effects (such as
975 loads, stores, calls, returns, etc). All nodes that have side effects should
976 take a token chain as input and produce a new one as output. By convention,
977 token chain inputs are always operand #0, and chain results are always the
978 last value produced by an operation.</p>
982 node is the final side-effecting node in the token chain. For example, in a
983 single basic block function it would be the return node.</p>
986 "illegal" DAG. A legal DAG for a target is one that only uses supported
987 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
988 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
989 uses a SREM or UREM operation. The
992 responsible for turning an illegal DAG into a legal DAG.</p>
994 </div>
996 <!-- _______________________________________________________________________ -->
997 <h4>
999 </h4>
1001 <div>
1005 <ol>
1007 performs a simple translation from the input LLVM code to an illegal
1008 SelectionDAG.</li>
1011 stage performs simple optimizations on the SelectionDAG to simplify it,
1012 and recognize meta instructions (like rotates
1014 operations. This makes the resultant code more efficient and
1016 (below) simpler.</li>
1019 — This stage transforms SelectionDAG nodes to eliminate any types
1020 that are unsupported on the target.</li>
1023 SelectionDAG optimizer is run to clean up redundancies exposed by type
1024 legalization.</li>
1027 This stage transforms SelectionDAG nodes to eliminate any operations
1028 that are unsupported on the target.</li>
1031 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1032 operation legalization.</li>
1035 Finally, the target instruction selector matches the DAG operations to
1036 target instructions. This process translates the target-independent input
1037 DAG into another DAG of target instructions.</li>
1040 — The last phase assigns a linear order to the instructions in the
1041 target-instruction DAG and emits them into the MachineFunction being
1042 compiled. This step uses traditional prepass scheduling techniques.</li>
1043 </ol>
1045 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
1046 rest of the code generation passes are run.</p>
1048 <p>One great way to visualize what is going on here is to take advantage of a
1049 few LLC command line options. The following options pop up a window
1050 displaying the SelectionDAG at specific times (if you only get errors printed
1051 to the console while using this, you probably
1053 to add support for it).</p>
1055 <ul>
1057 before the first optimization pass.</li>
1062 optimization pass.</li>
1067 </ul>
1070 This graph is based on the final SelectionDAG, with nodes that must be
1071 scheduled together bundled into a single scheduling-unit node, and with
1072 immediate operands and other nodes that aren't relevant for scheduling
1073 omitted.</p>
1075 </div>
1077 <!-- _______________________________________________________________________ -->
1078 <h4>
1080 </h4>
1082 <div>
1087 this pass is to expose as much low-level, target-specific details to the
1088 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1091 requires target-specific hooks to lower calls, returns, varargs, etc. For
1093 interface is used.</p>
1095 </div>
1097 <!-- _______________________________________________________________________ -->
1098 <h4>
1100 </h4>
1102 <div>
1104 <p>The Legalize phase is in charge of converting a DAG to only use the types
1105 that are natively supported by the target.</p>
1107 <p>There are two main ways of converting values of unsupported scalar types to
1108 values of supported types: converting small types to larger types
1109 ("promoting"), and breaking up large integer types into smaller ones
1110 ("expanding"). For example, a target might require that all f32 values are
1111 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1112 target might require that all i64 values be expanded into pairs of i32
1113 values. These changes can insert sign and zero extensions as needed to make
1114 sure that the final code has the same behavior as the input.</p>
1116 <p>There are two main ways of converting values of unsupported vector types to
1117 value of supported types: splitting vector types, multiple times if
1118 necessary, until a legal type is found, and extending vector types by adding
1119 elements to the end to round them out to legal types ("widening"). If a
1120 vector gets split all the way down to single-element parts with no supported
1121 vector type being found, the elements are converted to scalars
1124 <p>A target implementation tells the legalizer which types are supported (and
1125 which register class to use for them) by calling the
1128 </div>
1130 <!-- _______________________________________________________________________ -->
1131 <h4>
1133 </h4>
1135 <div>
1137 <p>The Legalize phase is in charge of converting a DAG to only use the
1138 operations that are natively supported by the target.</p>
1140 <p>Targets often have weird constraints, such as not supporting every operation
1141 on every supported datatype (e.g. X86 does not support byte conditional moves
1142 and PowerPC does not support sign-extending loads from a 16-bit memory
1143 location). Legalize takes care of this by open-coding another sequence of
1144 operations to emulate the operation ("expansion"), by promoting one type to a
1145 larger type that supports the operation ("promotion"), or by using a
1148 <p>A target implementation tells the legalizer which operations are not
1149 supported (and which of the above three actions to take) by calling the
1151 constructor.</p>
1153 <p>Prior to the existence of the Legalize passes, we required that every target
1155 operator and type even if they are not natively supported. The introduction
1156 of the Legalize phases allows all of the canonicalization patterns to be
1157 shared across targets, and makes it very easy to optimize the canonicalized
1158 code because it is still in the form of a DAG.</p>
1160 </div>
1162 <!-- _______________________________________________________________________ -->
1163 <h4>
1165 SelectionDAG Optimization Phase: the DAG Combiner
1166 </a>
1167 </h4>
1169 <div>
1171 <p>The SelectionDAG optimization phase is run multiple times for code
1172 generation, immediately after the DAG is built and once after each
1173 legalization. The first run of the pass allows the initial code to be
1174 cleaned up (e.g. performing optimizations that depend on knowing that the
1175 operators have restricted type inputs). Subsequent runs of the pass clean up
1176 the messy code generated by the Legalize passes, which allows Legalize to be
1177 very simple (it can focus on making code legal instead of focusing on
1180 <p>One important class of optimizations performed is optimizing inserted sign
1181 and zero extension instructions. We currently use ad-hoc techniques, but
1182 could move to more rigorous techniques in the future. Here are some good
1183 papers on the subject:</p>
1187 Kevin Redwine and Norman Ramsey<br>
1192 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1193 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1194 and Implementation.</p>
1196 </div>
1198 <!-- _______________________________________________________________________ -->
1199 <h4>
1201 </h4>
1203 <div>
1205 <p>The Select phase is the bulk of the target-specific code for instruction
1206 selection. This phase takes a legal SelectionDAG as input, pattern matches
1207 the instructions supported by the target to this DAG, and produces a new DAG
1208 of target code. For example, consider the following LLVM fragment:</p>
1211 <pre>
1212 %t1 = fadd float %W, %X
1213 %t2 = fmul float %t1, %Y
1214 %t3 = fadd float %t2, %Z
1215 </pre>
1216 </div>
1218 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1219 this:</p>
1222 <pre>
1223 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1224 </pre>
1225 </div>
1227 <p>If a target supports floating point multiply-and-add (FMA) operations, one of
1228 the adds can be merged with the multiply. On the PowerPC, for example, the
1229 output of the instruction selector might look like this DAG:</p>
1232 <pre>
1233 (FMADDS (FADDS W, X), Y, Z)
1234 </pre>
1235 </div>
1238 first two operands and adds the third (as single-precision floating-point
1240 add instruction. To perform this pattern match, the PowerPC backend includes
1241 the following instruction definitions:</p>
1244 <pre>
1246 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1247 "fmadds $FRT, $FRA, $FRC, $FRB",
1248 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1251 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1252 "fadds $FRT, $FRA, $FRB",
1254 </pre>
1255 </div>
1257 <p>The portion of the instruction definition in bold indicates the pattern used
1258 to match the instruction. The DAG operators
1263 <p>The TableGen DAG instruction selector generator reads the instruction
1265 pattern matching code for your target. It has the following strengths:</p>
1267 <ul>
1268 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1269 you if your patterns make sense or not.</li>
1271 <li>It can handle arbitrary constraints on operands for the pattern match. In
1272 particular, it is straight-forward to say things like "match any immediate
1273 that is a 13-bit sign-extended value". For examples, see the
1275 backend.</li>
1277 <li>It knows several important identities for the patterns defined. For
1278 example, it knows that addition is commutative, so it allows the
1280 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1281 to specially handle this case.</li>
1283 <li>It has a full-featured type-inferencing system. In particular, you should
1284 rarely have to explicitly tell the system what type parts of your patterns
1287 It was able to infer and propagate this knowledge from the fact that
1291 Pattern fragments are chunks of reusable patterns that get inlined into
1292 your patterns during compiler-compiler time. For example, the integer
1293 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1294 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1296 short-hand fragments as they see fit. See the definition of
1299 <li>In addition to instructions, targets can specify arbitrary patterns that
1300 map to one or more instructions using the 'Pat' class. For example, the
1301 PowerPC has no way to load an arbitrary integer immediate into a register
1302 in one instruction. To tell tblgen how to do this, it defines:
1303 <br>
1304 <br>
1306 <pre>
1307 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1308 def : Pat<(i32 imm:$imm),
1309 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1310 </pre>
1311 </div>
1312 <br>
1313 If none of the single-instruction patterns for loading an immediate into a
1314 register match, this will be used. This rule says "match an arbitrary i32
1315 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1316 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1317 the left 16 bits') instruction". To make this work, the
1319 the input immediate (in this case, take the high or low 16-bits of the
1320 immediate).</li>
1322 <li>While the system does automate a lot, it still allows you to write custom
1323 C++ code to match special cases if there is something that is hard to
1324 express.</li>
1325 </ul>
1327 <p>While it has many strengths, the system currently has some limitations,
1328 primarily because it is a work in progress and is not yet finished:</p>
1330 <ul>
1331 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1333 etc). This is the biggest reason that you currently still <em>have
1336 <li>There is no great way to support matching complex addressing modes yet.
1337 In the future, we will extend pattern fragments to allow them to define
1339 addressing mode</a>, which are currently matched with custom C++ code).
1340 In addition, we'll extend fragments so that a fragment can match multiple
1341 different patterns.</li>
1345 <li>We don't automatically generate the set of supported registers and
1347 yet.</li>
1350 </ul>
1352 <p>Despite these limitations, the instruction selector generator is still quite
1353 useful for most of the binary and logical operations in typical instruction
1354 sets. If you run into any problems or can't figure out how to do something,
1355 please let Chris know!</p>
1357 </div>
1359 <!-- _______________________________________________________________________ -->
1360 <h4>
1362 </h4>
1364 <div>
1366 <p>The scheduling phase takes the DAG of target instructions from the selection
1367 phase and assigns an order. The scheduler can pick an order depending on
1368 various constraints of the machines (i.e. order for minimal register pressure
1369 or try to cover instruction latencies). Once an order is established, the
1370 DAG is converted to a list
1372 destroyed.</p>
1374 <p>Note that this phase is logically separate from the instruction selection
1375 phase, but is tied to it closely in the code because it operates on
1376 SelectionDAGs.</p>
1378 </div>
1380 <!-- _______________________________________________________________________ -->
1381 <h4>
1383 </h4>
1385 <div>
1387 <ol>
1391 </ol>
1393 </div>
1395 </div>
1397 <!-- ======================================================================= -->
1398 <h3>
1400 </h3>
1403 <!-- ======================================================================= -->
1404 <h3>
1406 </h3>
1408 <div>
1412 determine if two or more virtual registers which require the same physical
1413 register are live at the same point in the program (i.e., they conflict).
1416 <!-- _______________________________________________________________________ -->
1417 <h4>
1419 </h4>
1421 <div>
1423 <p>The first step in determining the live intervals of variables is to calculate
1424 the set of registers that are immediately dead after the instruction (i.e.,
1425 the instruction calculates the value, but it is never used) and the set of
1426 registers that are used by the instruction, but are never used after the
1427 instruction (i.e., they are killed). Live variable information is computed
1429 register in the function. This is done in a very efficient manner because it
1430 uses SSA to sparsely compute lifetime information for virtual registers
1431 (which are in SSA form) and only has to track physical registers within a
1432 block. Before register allocation, LLVM can assume that physical registers
1433 are only live within a single basic block. This allows it to do a single,
1434 local analysis to resolve physical register lifetimes within each basic
1435 block. If a physical register is not register allocatable (e.g., a stack
1436 pointer or condition codes), it is not tracked.</p>
1438 <p>Physical registers may be live in to or out of a function. Live in values are
1439 typically arguments in registers. Live out values are typically return values
1440 in registers. Live in values are marked as such, and are given a dummy
1441 "defining" instruction during live intervals analysis. If the last basic
1443 out values in the function.</p>
1446 the live variable information from a depth first traversal of the CFG of the
1449 only the definition is handled, because the uses will be handled in other
1450 basic blocks.</p>
1453 assignment at the end of the current basic block and traverse the successor
1457 of its predecessor basic blocks, until the basic block with the defining
1458 instruction is encountered.</p>
1460 </div>
1462 <!-- _______________________________________________________________________ -->
1463 <h4>
1465 </h4>
1467 <div>
1469 <p>We now have the information available to perform the live intervals analysis
1470 and build the live intervals themselves. We start off by numbering the basic
1471 blocks and machine instructions. We then handle the "live-in" values. These
1472 are in physical registers, so the physical register is assumed to be killed
1473 by the end of the basic block. Live intervals for virtual registers are
1480 </div>
1482 </div>
1484 <!-- ======================================================================= -->
1485 <h3>
1487 </h3>
1489 <div>
1494 number of physical registers. Each target architecture has a different number
1495 of physical registers. If the number of physical registers is not enough to
1496 accommodate all the virtual registers, some of them will have to be mapped
1499 <!-- _______________________________________________________________________ -->
1501 <h4>
1503 </h4>
1505 <div>
1507 <p>In LLVM, physical registers are denoted by integer numbers that normally
1510 architecture. For instance, by
1515 <p>Some architectures contain registers that share the same physical location. A
1516 notable example is the X86 platform. For instance, in the X86 architecture,
1519 particular architecture, you can check which registers are aliased by
1525 Elements in the same register class are functionally equivalent, and can be
1526 interchangeably used. Each virtual register can only be mapped to physical
1527 registers of a particular class. For instance, in the X86 architecture, some
1528 virtuals can only be allocated to 8 bit registers. A register class is
1530 register is compatible with a given physical, this code can be used:</p>
1533 <pre>
1534 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1535 unsigned v_reg,
1536 unsigned p_reg) {
1537 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1538 "Target register must be physical");
1539 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1540 return trc->contains(p_reg);
1541 }
1542 </pre>
1543 </div>
1545 <p>Sometimes, mostly for debugging purposes, it is useful to change the number
1546 of physical registers available in the target architecture. This must be done
1549 registers. Just commenting some out is one simple way to avoid them being
1550 used. A more polite way is to explicitly exclude some registers from
1553 </p>
1555 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
1556 registers, different virtual registers never share the same number. Whereas
1558 file and cannot be created by the application developer, that is not the case
1559 with virtual registers. In order to create new virtual registers, use the
1563 need to enumerate all virtual registers, use the function
1565 numbers:</p>
1568 <pre>
1570 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1571 stuff(VirtReg);
1572 }
1573 </pre>
1574 </div>
1576 <p>Before register allocation, the operands of an instruction are mostly virtual
1577 registers, although physical registers may also be used. In order to check if
1578 a given machine operand is a register, use the boolean
1584 register is being used by the instruction. The
1586 defined.</p>
1588 <p>We will call physical registers present in the LLVM bitcode before register
1590 many different situations, for instance, to pass parameters of functions
1591 calls, and to store results of particular instructions. There are two types
1594 operands, and can be accessed
1596 which registers are implicitly defined by an instruction, use
1599 difference between explicit and implicit physical registers is that the
1600 latter are defined statically for each instruction, whereas the former may
1601 vary depending on the program being compiled. For example, an instruction
1602 that represents a function call will always implicitly define or use the same
1603 set of physical registers. To read the registers implicitly used by an
1604 instruction,
1606 registers impose constraints on any register allocation algorithm. The
1607 register allocator must make sure that none of them are overwritten by
1608 the values of virtual registers while still alive.</p>
1610 </div>
1612 <!-- _______________________________________________________________________ -->
1614 <h4>
1616 </h4>
1618 <div>
1620 <p>There are two ways to map virtual registers to physical registers (or to
1625 and stores sending and getting values to and from memory.</p>
1627 <p>The direct mapping provides more flexibility to the developer of the register
1628 allocator; however, it is more error prone, and demands more implementation
1629 work. Basically, the programmer will have to specify where load and store
1630 instructions should be inserted in the target function being compiled in
1631 order to get and store values in memory. To assign a physical register to a
1632 virtual register present in a given operand,
1637 <p>The indirect mapping shields the application developer from the complexities
1638 of inserting load and store instructions. In order to map a virtual register
1640 order to map a certain virtual register to memory,
1643 necessary to map another virtual register to the same stack slot,
1645 important point to consider when using the indirect mapping, is that even if
1646 a virtual register is mapped to memory, it still needs to be mapped to a
1647 physical register. This physical register is the location where the virtual
1648 register is supposed to be found before being stored or after being
1649 reloaded.</p>
1651 <p>If the indirect strategy is used, after all the virtual registers have been
1652 mapped to physical registers or stack slots, it is necessary to use a spiller
1653 object to place load and store instructions in the code. Every virtual that
1654 has been mapped to a stack slot will be stored to memory after been defined
1655 and will be loaded before being used. The implementation of the spiller tries
1656 to recycle load/store instructions, avoiding unnecessary instructions. For an
1657 example of how to invoke the spiller,
1661 </div>
1663 <!-- _______________________________________________________________________ -->
1664 <h4>
1666 </h4>
1668 <div>
1670 <p>With very rare exceptions (e.g., function calls), the LLVM machine code
1671 instructions are three address instructions. That is, each instruction is
1672 expected to define at most one register, and to use at most two registers.
1673 However, some architectures use two address instructions. In this case, the
1674 defined register is also one of the used register. For instance, an
1678 <p>In order to produce correct code, LLVM must convert three address
1679 instructions that represent two address instructions into true two address
1681 this specific purpose. It must be run before register allocation takes
1682 place. After its execution, the resulting code may no longer be in SSA
1683 form. This happens, for instance, in situations where an instruction such
1687 <pre>
1688 %a = MOVE %b
1689 %a = ADD %a %c
1690 </pre>
1691 </div>
1693 <p>Notice that, internally, the second instruction is represented as
1695 used and defined by the instruction.</p>
1697 </div>
1699 <!-- _______________________________________________________________________ -->
1700 <h4>
1702 </h4>
1704 <div>
1706 <p>An important transformation that happens during register allocation is called
1708 that are performed on the control flow graph of programs. However,
1709 traditional instruction sets do not implement PHI instructions. Thus, in
1710 order to generate executable code, compilers must replace PHI instructions
1711 with other instructions that preserve their semantics.</p>
1713 <p>There are many ways in which PHI instructions can safely be removed from the
1714 target code. The most traditional PHI deconstruction algorithm replaces PHI
1715 instructions with copy instructions. That is the strategy adopted by
1716 LLVM. The SSA deconstruction algorithm is implemented
1719 of the register allocator.</p>
1721 </div>
1723 <!-- _______________________________________________________________________ -->
1724 <h4>
1726 </h4>
1728 <div>
1731 allocation that removes unnecessary copy instructions. For instance, a
1732 sequence of instructions such as:</p>
1735 <pre>
1736 %EBX = LOAD %mem_address
1737 %EAX = COPY %EBX
1738 </pre>
1739 </div>
1744 <pre>
1745 %EAX = LOAD %mem_address
1746 </pre>
1747 </div>
1749 <p>Instructions can be folded with
1751 taken when folding instructions; a folded instruction can be quite different
1752 from the original
1755 use.</p>
1757 </div>
1759 <!-- _______________________________________________________________________ -->
1761 <h4>
1763 </h4>
1765 <div>
1767 <p>The LLVM infrastructure provides the application developer with three
1768 different register allocators:</p>
1770 <ul>
1772 well-know linear scan register allocator. Whereas the
1775 uses a spiller in order to place load and stores.</li>
1778 builds. It allocates registers on a basic block level, attempting to keep
1779 values in registers and reusing registers as appropriate.</li>
1782 based register allocator. This allocator works by constructing a PBQP
1783 problem representing the register allocation problem under consideration,
1784 solving this using a PBQP solver, and mapping the solution back to a
1785 register assignment.</li>
1787 </ul>
1793 <pre>
1794 $ llc -regalloc=linearscan file.bc -o ln.s;
1795 $ llc -regalloc=fast file.bc -o fa.s;
1796 $ llc -regalloc=pbqp file.bc -o pbqp.s;
1797 </pre>
1798 </div>
1800 </div>
1802 </div>
1804 <!-- ======================================================================= -->
1805 <h3>
1807 </h3>
1809 <!-- ======================================================================= -->
1810 <h3>
1812 </h3>
1815 <!-- ======================================================================= -->
1816 <h3>
1818 </h3>
1820 <div>
1822 <p>The code emission step of code generation is responsible for lowering from
1823 the code generator abstractions (like <a
1828 done with a combination of several different classes: the (misnamed)
1829 target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1830 (such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1832 <p>Since the MC layer works at the level of abstraction of object files, it
1833 doesn't have a notion of functions, global variables etc. Instead, it thinks
1834 about labels, directives, and instructions. A key class used at this time is
1835 the MCStreamer class. This is an abstract API that is implemented in different
1836 ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1837 an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1838 EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1839 level directives.
1840 </p>
1842 <p>If you are interested in implementing a code generator for a target, there
1843 are three important things that you have to implement for your target:</p>
1845 <ol>
1846 <li>First, you need a subclass of AsmPrinter for your target. This class
1847 implements the general lowering process converting MachineFunction's into MC
1848 label constructs. The AsmPrinter base class provides a number of useful methods
1849 and routines, and also allows you to override the lowering process in some
1850 important ways. You should get much of the lowering for free if you are
1851 implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1852 class implements much of the common logic.</li>
1854 <li>Second, you need to implement an instruction printer for your target. The
1856 raw_ostream as text. Most of this is automatically generated from the .td file
1857 (when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1858 instructions), but you need to implement routines to print operands.</li>
1862 "<target>MCInstLower.cpp". This lowering process is often target
1863 specific, and is responsible for turning jump table entries, constant pool
1864 indices, global variable addresses, etc into MCLabels as appropriate. This
1865 translation layer is also responsible for expanding pseudo ops used by the code
1866 generator into the actual machine instructions they correspond to. The MCInsts
1867 that are generated by this are fed into the instruction printer or the encoder.
1868 </li>
1870 </ol>
1872 <p>Finally, at your choosing, you can also implement an subclass of
1873 MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
1874 This is important if you want to support direct .o file emission, or would like
1875 to implement an assembler for your target.</p>
1877 </div>
1879 </div>
1881 <!-- *********************************************************************** -->
1882 <h2>
1884 </h2>
1885 <!-- *********************************************************************** -->
1887 <div>
1889 <p>Though you're probably reading this because you want to write or maintain a
1890 compiler backend, LLVM also fully supports building a native assemblers too.
1891 We've tried hard to automate the generation of the assembler from the .td files
1892 (in particular the instruction syntax and encodings), which means that a large
1893 part of the manual and repetitive data entry can be factored and shared with the
1894 compiler.</p>
1896 <!-- ======================================================================= -->
1902 <!-- ======================================================================= -->
1904 Instruction Alias Processing
1905 </h3>
1907 <div>
1908 <p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
1909 The MatchInstructionImpl function performs alias processing and then does
1910 actual matching.</p>
1912 <p>Alias processing is the phase that canonicalizes different lexical forms of
1913 the same instructions down to one representation. There are several different
1914 kinds of alias that are possible to implement and they are listed below in the
1915 order that they are processed (which is in order from simplest/weakest to most
1916 complex/powerful). Generally you want to use the first alias mechanism that
1917 meets the needs of your instruction, because it will allow a more concise
1918 description.</p>
1920 <!-- _______________________________________________________________________ -->
1923 <div>
1925 <p>The first phase of alias processing is simple instruction mnemonic
1926 remapping for classes of instructions which are allowed with two different
1927 mnemonics. This phase is a simple and unconditionally remapping from one input
1928 mnemonic to one output mnemonic. It isn't possible for this form of alias to
1929 look at the operands at all, so the remapping must apply for all forms of a
1930 given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
1931 </p>
1934 <pre>
1940 </pre>
1941 </div>
1943 <p>... and many others. With a MnemonicAlias definition, the mnemonic is
1944 remapped simply and directly. Though MnemonicAlias's can't look at any aspect
1945 of the instruction (such as the operands) they can depend on global modes (the
1946 same ones supported by the matcher), through a Requires clause:</p>
1949 <pre>
1952 </pre>
1953 </div>
1955 <p>In this example, the mnemonic gets mapped into different a new one depending
1956 on the current instruction set.</p>
1958 </div>
1960 <!-- _______________________________________________________________________ -->
1963 <div>
1965 <p>The most general phase of alias processing occurs while matching is
1966 happening: it provides new forms for the matcher to match along with a specific
1967 instruction to generate. An instruction alias has two parts: the string to
1968 match and the instruction to generate. For example:
1969 </p>
1972 <pre>
1980 </pre>
1981 </div>
1983 <p>This shows a powerful example of the instruction aliases, matching the
1984 same mnemonic in multiple different ways depending on what operands are present
1985 in the assembly. The result of instruction aliases can include operands in a
1986 different order than the destination instruction, and can use an input
1987 multiple times, for example:</p>
1990 <pre>
1995 </pre>
1996 </div>
1998 <p>This example also shows that tied operands are only listed once. In the X86
1999 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2000 to the output). InstAliases take a flattened operand list without duplicates
2001 for tied operands. The result of an instruction alias can also use immediates
2002 and fixed physical registers which are added as simple immediate operands in the
2003 result, for example:</p>
2006 <pre>
2007 // Fixed Immediate operand.
2010 // Fixed register operand.
2013 // Simple alias.
2015 </pre>
2016 </div>
2019 <p>Instruction aliases can also have a Requires clause to make them
2020 subtarget specific.</p>
2022 <p>If the back-end supports it, the instruction printer can automatically emit
2023 the alias rather than what's being aliased. It typically leads to better,
2024 more readable code. If it's better to print out what's being aliased, then
2027 </div>
2029 </div>
2031 <!-- ======================================================================= -->
2036 </div>
2038 <!-- *********************************************************************** -->
2039 <h2>
2041 </h2>
2042 <!-- *********************************************************************** -->
2044 <div>
2046 <p>This section of the document explains features or design decisions that are
2047 specific to the code generator for a particular target. First we start
2048 with a table that summarizes what features are supported by each target.</p>
2050 <!-- ======================================================================= -->
2051 <h3>
2053 </h3>
2055 <div>
2057 <p>Note that this table does not include the C backend or Cpp backends, since
2058 they do not use the target independent code generator infrastructure. It also
2059 doesn't list features that are not supported fully by any target yet. It
2060 considers a feature to be supported if at least one subtarget supports it. A
2061 feature being supported means that it is useful and works for most cases, it
2062 does not indicate that there are zero known bugs in the implementation. Here
2063 is the key:</p>
2067 <tr>
2072 </tr>
2073 <tr>
2078 </tr>
2079 </table>
2084 <tr><td></td>
2086 </tr>
2087 <tr>
2102 </tr>
2104 <tr>
2119 </tr>
2121 <tr>
2136 </tr>
2138 <tr>
2153 </tr>
2155 <tr>
2170 </tr>
2172 <tr>
2187 </tr>
2189 <tr>
2204 </tr>
2206 <tr>
2221 </tr>
2224 </table>
2226 <!-- _______________________________________________________________________ -->
2229 <div>
2230 <p>This box indicates whether the target is considered to be production quality.
2231 This indicates that the target has been used as a static compiler to
2232 compile large amounts of code by a variety of different people and is in
2233 continuous use.</p>
2234 </div>
2236 <!-- _______________________________________________________________________ -->
2239 <div>
2240 <p>This box indicates whether the target supports parsing target specific .s
2241 files by implementing the MCAsmParser interface. This is required for llvm-mc
2242 to be able to act as a native assembler and is required for inline assembly
2243 support in the native .o file writer.</p>
2245 </div>
2248 <!-- _______________________________________________________________________ -->
2251 <div>
2252 <p>This box indicates whether the target supports the MCDisassembler API for
2253 disassembling machine opcode bytes into MCInst's.</p>
2255 </div>
2257 <!-- _______________________________________________________________________ -->
2260 <div>
2261 <p>This box indicates whether the target supports most popular inline assembly
2262 constraints and modifiers.</p>
2265 constraints relating to the X86 floating point stack.</p>
2267 </div>
2269 <!-- _______________________________________________________________________ -->
2272 <div>
2273 <p>This box indicates whether the target supports the JIT compiler through
2274 the ExecutionEngine interface.</p>
2277 in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2279 </div>
2281 <!-- _______________________________________________________________________ -->
2284 <div>
2286 <p>This box indicates whether the target supports writing .o files (e.g. MachO,
2287 ELF, and/or COFF) files directly from the target. Note that the target also
2288 must include an assembly parser and general inline assembly support for full
2289 inline assembly support in the .o writer.</p>
2291 <p>Targets that don't support this feature can obviously still write out .o
2292 files, they just rely on having an external assembler to translate from a .s
2293 file to a .o file (as is the case for many C compilers).</p>
2295 </div>
2297 <!-- _______________________________________________________________________ -->
2300 <div>
2302 <p>This box indicates whether the target supports guaranteed tail calls. These
2307 </div>
2309 </div>
2311 <!-- ======================================================================= -->
2312 <h3>
2314 </h3>
2316 <div>
2318 <p>Tail call optimization, callee reusing the stack of the caller, is currently
2321 <ul>
2325 <li>The call is a tail call - in tail position (ret immediately follows call
2326 and ret uses value of call or is void).</li>
2331 </ul>
2335 <ul>
2339 = hidden or protected) are supported.</li>
2340 </ul>
2344 <ul>
2349 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2350 </ul>
2357 <pre>
2358 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2360 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2361 %l1 = add i32 %in1, %in2
2362 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2363 ret i32 %tmp
2364 }
2365 </pre>
2366 </div>
2370 <p>To support tail call optimization in situations where the callee has more
2371 arguments than the caller a 'callee pops arguments' convention is used. This
2373 (because one or more of above constraints are not met) to be followed by a
2374 readjustment of the stack. So performance might be worse in such cases.</p>
2376 </div>
2377 <!-- ======================================================================= -->
2378 <h3>
2380 </h3>
2382 <div>
2384 <p>Sibling call optimization is a restricted form of tail call optimization.
2385 Unlike tail call optimization described in the previous section, it can be
2387 is not specified.</p>
2390 following constraints are met:</p>
2392 <ul>
2393 <li>Caller and callee have the same calling convention. It can be either
2396 <li>The call is a tail call - in tail position (ret immediately follows call
2397 and ret uses value of call or is void).</li>
2399 <li>Caller and callee have matching return type or the callee result is not
2400 used.
2402 <li>If any of the callee arguments are being passed in stack, they must be
2403 available in caller's own incoming argument stack and the frame offsets
2404 must be the same.
2405 </ul>
2409 <pre>
2410 declare i32 @bar(i32, i32)
2412 define i32 @foo(i32 %a, i32 %b, i32 %c) {
2413 entry:
2414 %0 = tail call i32 @bar(i32 %a, i32 %b)
2415 ret i32 %0
2416 }
2417 </pre>
2418 </div>
2420 </div>
2421 <!-- ======================================================================= -->
2422 <h3>
2424 </h3>
2426 <div>
2430 processors, and includes support for ISA extensions such as MMX and SSE.</p>
2432 <!-- _______________________________________________________________________ -->
2433 <h4>
2435 </h4>
2437 <div>
2439 <p>The following are the known target triples that are supported by the X86
2440 backend. This is not an exhaustive list, and it would be useful to add those
2441 that people test.</p>
2443 <ul>
2457 </ul>
2459 </div>
2461 <!-- _______________________________________________________________________ -->
2462 <h4>
2464 </h4>
2467 <div>
2471 <ul>
2477 in ECX, others via stack. Callee is responsible for stack cleaning. This
2478 convention is used by MSVC by default for methods in its ABI
2480 </ul>
2482 </div>
2484 <!-- _______________________________________________________________________ -->
2485 <h4>
2487 </h4>
2489 <div>
2491 <p>The x86 has a very flexible way of accessing memory. It is capable of
2492 forming memory addresses of the following expression directly in integer
2493 instructions (which use ModR/M addressing):</p>
2496 <pre>
2498 </pre>
2499 </div>
2502 memory operand of this form. This means that the "load" form of
2506 <pre>
2508 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2509 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
2510 </pre>
2511 </div>
2513 <p>Stores, and all other instructions, treat the four memory operands in the
2514 same way and in the same order. If the segment register is unspecified
2516 have a segment register specified, so they only have 4 operands for their
2517 memory reference.</p>
2519 </div>
2521 <!-- _______________________________________________________________________ -->
2522 <h4>
2524 </h4>
2526 <div>
2528 <p>x86 has a feature which provides
2529 the ability to perform loads and stores to different address spaces
2530 via the x86 segment registers. A segment override prefix byte on an
2531 instruction causes the instruction's memory access to go to the specified
2532 segment. LLVM address space 0 is the default address space, which includes
2533 the stack, and any unqualified memory accesses in a program. Address spaces
2535 represented by address space 256, while the FS-segment is represented by
2536 address space 257. Other x86 segments have yet to be allocated address space
2537 numbers.</p>
2539 <p>While these address spaces may seem similar to TLS via the
2541 there are some fundamental differences.</p>
2544 specifies that they are to be allocated in thread-local memory. There are
2545 no type qualifiers involved, and these variables can be pointed to with
2546 normal pointers and accessed with normal loads and stores.
2548 level (though LLVM doesn't yet have implementations of it for some
2549 configurations).<p>
2551 <p>Special address spaces, in contrast, apply to static types. Every
2552 load and store has a particular address space in its address operand type,
2553 and this is what determines which address space is accessed.
2554 LLVM ignores these special address space qualifiers on global variables,
2555 and does not provide a way to directly allocate storage in them.
2556 At the LLVM IR level, the behavior of these special address spaces depends
2557 in part on the underlying OS or runtime environment, and they are specific
2558 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2560 <p>Some operating systems and runtime environments use (or may in the future
2561 use) the FS/GS-segment registers for various low-level purposes, so care
2562 should be taken when considering them.</p>
2564 </div>
2566 <!-- _______________________________________________________________________ -->
2567 <h4>
2569 </h4>
2571 <div>
2573 <p>An instruction name consists of the base name, a default operand size, and a
2574 a character per operand with an optional special size. For example:</p>
2577 <pre>
2582 </pre>
2583 </div>
2585 </div>
2587 </div>
2589 <!-- ======================================================================= -->
2590 <h3>
2592 </h3>
2594 <div>
2596 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
2598 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2600 <!-- _______________________________________________________________________ -->
2601 <h4>
2603 </h4>
2605 <div>
2607 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
2608 relative (PIC) or static addressing for accessing global values, so no TOC
2609 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2610 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2611 save the frame pointer in the PowerPC linkage area of the caller frame.
2612 Other details of PowerPC ABI can be found at <a href=
2613 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2616 for system use.</p>
2618 </div>
2620 <!-- _______________________________________________________________________ -->
2621 <h4>
2623 </h4>
2625 <div>
2627 <p>The size of a PowerPC frame is usually fixed for the duration of a
2628 function's invocation. Since the frame is fixed size, all references
2629 into the frame can be accessed via fixed offsets from the stack pointer. The
2630 exception to this is when dynamic alloca or variable sized arrays are
2631 present, then a base pointer (r31) is used as a proxy for the stack pointer
2632 and stack pointer is free to grow or shrink. A base pointer is also used if
2633 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2634 always aligned to 16 bytes, so that space allocated for altivec vectors will
2635 be properly aligned.</p>
2640 <tr>
2642 </tr>
2643 <tr>
2645 </tr>
2646 <tr>
2648 </tr>
2649 <tr>
2651 </tr>
2652 <tr>
2654 </tr>
2656 <td><br></td>
2657 </tr>
2658 <tr>
2660 </tr>
2661 </table>
2664 to allocating its own frame. Only three entries are relevant to LLVM. The
2665 first entry is the previous stack pointer (sp), aka link. This allows
2666 probing tools like gdb or exception handlers to quickly scan the frames in
2667 the stack. A function epilog can also use the link to pop the frame from the
2668 stack. The third entry in the linkage area is used to save the return
2669 address from the lr register. Finally, as mentioned above, the last entry is
2670 used to save the previous frame pointer (r31.) The entries in the linkage
2677 <tr>
2680 </tr>
2681 <tr>
2684 </tr>
2685 <tr>
2688 </tr>
2689 <tr>
2692 </tr>
2693 <tr>
2696 </tr>
2697 <tr>
2700 </tr>
2701 </table>
2706 <tr>
2709 </tr>
2710 <tr>
2713 </tr>
2714 <tr>
2717 </tr>
2718 <tr>
2721 </tr>
2722 <tr>
2725 </tr>
2726 <tr>
2729 </tr>
2730 </table>
2733 function. Following the PowerPC ABI, the first few arguments are actually
2734 passed in registers, with the space in the parameter area unused. However,
2735 if there are not enough registers or the callee is a thunk or vararg
2736 function, these register arguments can be spilled into the parameter area.
2737 Thus, the parameter area must be large enough to store all the parameters for
2738 the largest call sequence made by the caller. The size must also be
2739 minimally large enough to spill registers r3-r10. This allows callees blind
2740 to the call signature, such as thunks and vararg functions, enough space to
2741 cache the argument registers. Therefore, the parameter area is minimally 32
2743 a fixed offset from the top of the frame, that a callee can access its spilt
2744 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
2746 <p>Combining the information about the linkage, parameter areas and alignment. A
2748 mode.</p>
2751 alloca then space is added to the stack, the linkage and parameter areas are
2752 shifted to top of stack, and the new space is available immediately below the
2753 linkage and parameter areas. The cost of shifting the linkage and parameter
2754 areas is minor since only the link value needs to be copied. The link value
2755 can be easily fetched by adding the original frame size to the base pointer.
2756 Note that allocations in the dynamic space need to observe 16 byte
2757 alignment.</p>
2760 variables.</p>
2763 saved registers on entry to the callee.</p>
2765 </div>
2767 <!-- _______________________________________________________________________ -->
2768 <h4>
2770 </h4>
2772 <div>
2774 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2775 the following exceptions. Callee saved registers are spilled after the frame
2776 is created. This allows the llvm epilog/prolog support to be common with
2777 other targets. The base pointer callee saved register r31 is saved in the
2778 TOC slot of linkage area. This simplifies allocation of space for the base
2779 pointer and makes it convenient to locate programatically and during
2780 debugging.</p>
2782 </div>
2784 <!-- _______________________________________________________________________ -->
2785 <h4>
2787 </h4>
2789 <div>
2793 </div>
2795 </div>
2797 </div>
2799 <!-- *********************************************************************** -->
2800 <hr>
2801 <address>
2809 Last modified: $Date$
2810 </address>
2812 </body>
2813 </html>