lib/CodeGen/RegAllocBasic.cpp

   1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RABasic function pass, which provides a minimal
  11 // implementation of the basic register allocator.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "regalloc"
  16 #include "RegAllocBase.h"
  17 #include "LiveDebugVariables.h"
  18 #include "LiveIntervalUnion.h"
  19 #include "LiveRangeEdit.h"
  20 #include "RenderMachineFunction.h"
  21 #include "Spiller.h"
  22 #include "VirtRegMap.h"
  23 #include "RegisterCoalescer.h"
  24 #include "llvm/ADT/OwningPtr.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/Analysis/AliasAnalysis.h"
  27 #include "llvm/Function.h"
  28 #include "llvm/PassAnalysisSupport.h"
  29 #include "llvm/CodeGen/CalcSpillWeights.h"
  30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  31 #include "llvm/CodeGen/LiveStackAnalysis.h"
  32 #include "llvm/CodeGen/MachineFunctionPass.h"
  33 #include "llvm/CodeGen/MachineInstr.h"
  34 #include "llvm/CodeGen/MachineLoopInfo.h"
  35 #include "llvm/CodeGen/MachineRegisterInfo.h"
  36 #include "llvm/CodeGen/Passes.h"
  37 #include "llvm/CodeGen/RegAllocRegistry.h"
  38 #include "llvm/Target/TargetMachine.h"
  39 #include "llvm/Target/TargetOptions.h"
  40 #include "llvm/Target/TargetRegisterInfo.h"
  41 #ifndef NDEBUG
  42 #include "llvm/ADT/SparseBitVector.h"
  43 #endif
  44 #include "llvm/Support/Debug.h"
  45 #include "llvm/Support/ErrorHandling.h"
  46 #include "llvm/Support/raw_ostream.h"
  47 #include "llvm/Support/Timer.h"
  48
  49 #include <cstdlib>
  50 #include <queue>
  51
  52 using namespace llvm;
  53
  54 STATISTIC(NumAssigned     , "Number of registers assigned");
  55 STATISTIC(NumUnassigned   , "Number of registers unassigned");
  56 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
  57
  58 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
  59                                       createBasicRegisterAllocator);
  60
  61 // Temporary verification option until we can put verification inside
  62 // MachineVerifier.
  63 static cl::opt<bool, true>
  64 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
  65                cl::desc("Verify during register allocation"));
  66
  67 const char *RegAllocBase::TimerGroupName = "Register Allocation";
  68 bool RegAllocBase::VerifyEnabled = false;
  69
  70 namespace {
  71   struct CompSpillWeight {
  72     bool operator()(LiveInterval *A, LiveInterval *B) const {
  73       return A->weight < B->weight;
  74     }
  75   };
  76 }
  77
  78 namespace {
  79 /// RABasic provides a minimal implementation of the basic register allocation
  80 /// algorithm. It prioritizes live virtual registers by spill weight and spills
  81 /// whenever a register is unavailable. This is not practical in production but
  82 /// provides a useful baseline both for measuring other allocators and comparing
  83 /// the speed of the basic algorithm against other styles of allocators.
  84 class RABasic : public MachineFunctionPass, public RegAllocBase
  85 {
  86   // context
  87   MachineFunction *MF;
  88
  89   // analyses
  90   LiveStacks *LS;
  91   RenderMachineFunction *RMF;
  92
  93   // state
  94   std::auto_ptr<Spiller> SpillerInstance;
  95   std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
  96                       CompSpillWeight> Queue;
  97 public:
  98   RABasic();
  99
 100   /// Return the pass name.
 101   virtual const char* getPassName() const {
 102     return "Basic Register Allocator";
 103   }
 104
 105   /// RABasic analysis usage.
 106   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 107
 108   virtual void releaseMemory();
 109
 110   virtual Spiller &spiller() { return *SpillerInstance; }
 111
 112   virtual float getPriority(LiveInterval *LI) { return LI->weight; }
 113
 114   virtual void enqueue(LiveInterval *LI) {
 115     Queue.push(LI);
 116   }
 117
 118   virtual LiveInterval *dequeue() {
 119     if (Queue.empty())
 120       return 0;
 121     LiveInterval *LI = Queue.top();
 122     Queue.pop();
 123     return LI;
 124   }
 125
 126   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
 127                                  SmallVectorImpl<LiveInterval*> &SplitVRegs);
 128
 129   /// Perform register allocation.
 130   virtual bool runOnMachineFunction(MachineFunction &mf);
 131
 132   static char ID;
 133 };
 134
 135 char RABasic::ID = 0;
 136
 137 } // end anonymous namespace
 138
 139 RABasic::RABasic(): MachineFunctionPass(ID) {
 140   initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
 141   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
 142   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
 143   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
 144   initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
 145   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
 146   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
 147   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
 148   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
 149   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
 150   initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
 151 }
 152
 153 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
 154   AU.setPreservesCFG();
 155   AU.addRequired<AliasAnalysis>();
 156   AU.addPreserved<AliasAnalysis>();
 157   AU.addRequired<LiveIntervals>();
 158   AU.addPreserved<SlotIndexes>();
 159   AU.addRequired<LiveDebugVariables>();
 160   AU.addPreserved<LiveDebugVariables>();
 161   if (StrongPHIElim)
 162     AU.addRequiredID(StrongPHIEliminationID);
 163   AU.addRequiredTransitive<RegisterCoalescer>();
 164   AU.addRequired<CalculateSpillWeights>();
 165   AU.addRequired<LiveStacks>();
 166   AU.addPreserved<LiveStacks>();
 167   AU.addRequiredID(MachineDominatorsID);
 168   AU.addPreservedID(MachineDominatorsID);
 169   AU.addRequired<MachineLoopInfo>();
 170   AU.addPreserved<MachineLoopInfo>();
 171   AU.addRequired<VirtRegMap>();
 172   AU.addPreserved<VirtRegMap>();
 173   DEBUG(AU.addRequired<RenderMachineFunction>());
 174   MachineFunctionPass::getAnalysisUsage(AU);
 175 }
 176
 177 void RABasic::releaseMemory() {
 178   SpillerInstance.reset(0);
 179   RegAllocBase::releaseMemory();
 180 }
 181
 182 #ifndef NDEBUG
 183 // Verify each LiveIntervalUnion.
 184 void RegAllocBase::verify() {
 185   LiveVirtRegBitSet VisitedVRegs;
 186   OwningArrayPtr<LiveVirtRegBitSet>
 187     unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
 188
 189   // Verify disjoint unions.
 190   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
 191     DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
 192     LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
 193     PhysReg2LiveUnion[PhysReg].verify(VRegs);
 194     // Union + intersection test could be done efficiently in one pass, but
 195     // don't add a method to SparseBitVector unless we really need it.
 196     assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
 197     VisitedVRegs |= VRegs;
 198   }
 199
 200   // Verify vreg coverage.
 201   for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
 202        liItr != liEnd; ++liItr) {
 203     unsigned reg = liItr->first;
 204     if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
 205     if (!VRM->hasPhys(reg)) continue; // spilled?
 206     unsigned PhysReg = VRM->getPhys(reg);
 207     if (!unionVRegs[PhysReg].test(reg)) {
 208       dbgs() << "LiveVirtReg " << reg << " not in union " <<
 209         TRI->getName(PhysReg) << "\n";
 210       llvm_unreachable("unallocated live vreg");
 211     }
 212   }
 213   // FIXME: I'm not sure how to verify spilled intervals.
 214 }
 215 #endif //!NDEBUG
 216
 217 //===----------------------------------------------------------------------===//
 218 //                         RegAllocBase Implementation
 219 //===----------------------------------------------------------------------===//
 220
 221 // Instantiate a LiveIntervalUnion for each physical register.
 222 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
 223                                         unsigned NRegs) {
 224   NumRegs = NRegs;
 225   Array =
 226     static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
 227   for (unsigned r = 0; r != NRegs; ++r)
 228     new(Array + r) LiveIntervalUnion(r, allocator);
 229 }
 230
 231 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
 232   NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
 233   TRI = &vrm.getTargetRegInfo();
 234   MRI = &vrm.getRegInfo();
 235   VRM = &vrm;
 236   LIS = &lis;
 237   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
 238
 239   const unsigned NumRegs = TRI->getNumRegs();
 240   if (NumRegs != PhysReg2LiveUnion.numRegs()) {
 241     PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
 242     // Cache an interferece query for each physical reg
 243     Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
 244   }
 245 }
 246
 247 void RegAllocBase::LiveUnionArray::clear() {
 248   if (!Array)
 249     return;
 250   for (unsigned r = 0; r != NumRegs; ++r)
 251     Array[r].~LiveIntervalUnion();
 252   free(Array);
 253   NumRegs =  0;
 254   Array = 0;
 255 }
 256
 257 void RegAllocBase::releaseMemory() {
 258   for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
 259     PhysReg2LiveUnion[r].clear();
 260 }
 261
 262 // Visit all the live registers. If they are already assigned to a physical
 263 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
 264 // them on the priority queue for later assignment.
 265 void RegAllocBase::seedLiveRegs() {
 266   NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
 267   for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
 268     unsigned RegNum = I->first;
 269     LiveInterval &VirtReg = *I->second;
 270     if (TargetRegisterInfo::isPhysicalRegister(RegNum))
 271       PhysReg2LiveUnion[RegNum].unify(VirtReg);
 272     else
 273       enqueue(&VirtReg);
 274   }
 275 }
 276
 277 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
 278   DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
 279                << " to " << PrintReg(PhysReg, TRI) << '\n');
 280   assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
 281   VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
 282   MRI->setPhysRegUsed(PhysReg);
 283   PhysReg2LiveUnion[PhysReg].unify(VirtReg);
 284   ++NumAssigned;
 285 }
 286
 287 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
 288   DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
 289                << " from " << PrintReg(PhysReg, TRI) << '\n');
 290   assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
 291   PhysReg2LiveUnion[PhysReg].extract(VirtReg);
 292   VRM->clearVirt(VirtReg.reg);
 293   ++NumUnassigned;
 294 }
 295
 296 // Top-level driver to manage the queue of unassigned VirtRegs and call the
 297 // selectOrSplit implementation.
 298 void RegAllocBase::allocatePhysRegs() {
 299   seedLiveRegs();
 300
 301   // Continue assigning vregs one at a time to available physical registers.
 302   while (LiveInterval *VirtReg = dequeue()) {
 303     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
 304
 305     // Unused registers can appear when the spiller coalesces snippets.
 306     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
 307       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
 308       LIS->removeInterval(VirtReg->reg);
 309       continue;
 310     }
 311
 312     // Invalidate all interference queries, live ranges could have changed.
 313     invalidateVirtRegs();
 314
 315     // selectOrSplit requests the allocator to return an available physical
 316     // register if possible and populate a list of new live intervals that
 317     // result from splitting.
 318     DEBUG(dbgs() << "\nselectOrSplit "
 319                  << MRI->getRegClass(VirtReg->reg)->getName()
 320                  << ':' << *VirtReg << '\n');
 321     typedef SmallVector<LiveInterval*, 4> VirtRegVec;
 322     VirtRegVec SplitVRegs;
 323     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
 324
 325     if (AvailablePhysReg == ~0u) {
 326       // selectOrSplit failed to find a register!
 327       const char *Msg = "ran out of registers during register allocation";
 328       // Probably caused by an inline asm.
 329       MachineInstr *MI;
 330       for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
 331            (MI = I.skipInstruction());)
 332         if (MI->isInlineAsm())
 333           break;
 334       if (MI)
 335         MI->emitError(Msg);
 336       else
 337         report_fatal_error(Msg);
 338       // Keep going after reporting the error.
 339       VRM->assignVirt2Phys(VirtReg->reg,
 340                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
 341       continue;
 342     }
 343
 344     if (AvailablePhysReg)
 345       assign(*VirtReg, AvailablePhysReg);
 346
 347     for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
 348          I != E; ++I) {
 349       LiveInterval *SplitVirtReg = *I;
 350       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
 351       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
 352         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
 353         LIS->removeInterval(SplitVirtReg->reg);
 354         continue;
 355       }
 356       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
 357       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
 358              "expect split value in virtual register");
 359       enqueue(SplitVirtReg);
 360       ++NumNewQueued;
 361     }
 362   }
 363 }
 364
 365 // Check if this live virtual register interferes with a physical register. If
 366 // not, then check for interference on each register that aliases with the
 367 // physical register. Return the interfering register.
 368 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
 369                                                 unsigned PhysReg) {
 370   for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
 371     if (query(VirtReg, *AliasI).checkInterference())
 372       return *AliasI;
 373   return 0;
 374 }
 375
 376 // Helper for spillInteferences() that spills all interfering vregs currently
 377 // assigned to this physical register.
 378 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
 379                             SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 380   LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
 381   assert(Q.seenAllInterferences() && "need collectInterferences()");
 382   const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
 383
 384   for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
 385          E = PendingSpills.end(); I != E; ++I) {
 386     LiveInterval &SpilledVReg = **I;
 387     DEBUG(dbgs() << "extracting from " <<
 388           TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
 389
 390     // Deallocate the interfering vreg by removing it from the union.
 391     // A LiveInterval instance may not be in a union during modification!
 392     unassign(SpilledVReg, PhysReg);
 393
 394     // Spill the extracted interval.
 395     LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
 396     spiller().spill(LRE);
 397   }
 398   // After extracting segments, the query's results are invalid. But keep the
 399   // contents valid until we're done accessing pendingSpills.
 400   Q.clear();
 401 }
 402
 403 // Spill or split all live virtual registers currently unified under PhysReg
 404 // that interfere with VirtReg. The newly spilled or split live intervals are
 405 // returned by appending them to SplitVRegs.
 406 bool
 407 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
 408                                  SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 409   // Record each interference and determine if all are spillable before mutating
 410   // either the union or live intervals.
 411   unsigned NumInterferences = 0;
 412   // Collect interferences assigned to any alias of the physical register.
 413   for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
 414     LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
 415     NumInterferences += QAlias.collectInterferingVRegs();
 416     if (QAlias.seenUnspillableVReg()) {
 417       return false;
 418     }
 419   }
 420   DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
 421         " interferences with " << VirtReg << "\n");
 422   assert(NumInterferences > 0 && "expect interference");
 423
 424   // Spill each interfering vreg allocated to PhysReg or an alias.
 425   for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
 426     spillReg(VirtReg, *AliasI, SplitVRegs);
 427   return true;
 428 }
 429
 430 // Add newly allocated physical registers to the MBB live in sets.
 431 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
 432   NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
 433   SlotIndexes *Indexes = LIS->getSlotIndexes();
 434   if (MF->size() <= 1)
 435     return;
 436
 437   LiveIntervalUnion::SegmentIter SI;
 438   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
 439     LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
 440     if (LiveUnion.empty())
 441       continue;
 442     MachineFunction::iterator MBB = llvm::next(MF->begin());
 443     MachineFunction::iterator MFE = MF->end();
 444     SlotIndex Start, Stop;
 445     tie(Start, Stop) = Indexes->getMBBRange(MBB);
 446     SI.setMap(LiveUnion.getMap());
 447     SI.find(Start);
 448     while (SI.valid()) {
 449       if (SI.start() <= Start) {
 450         if (!MBB->isLiveIn(PhysReg))
 451           MBB->addLiveIn(PhysReg);
 452       } else if (SI.start() > Stop)
 453         MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex());
 454       if (++MBB == MFE)
 455         break;
 456       tie(Start, Stop) = Indexes->getMBBRange(MBB);
 457       SI.advanceTo(Start);
 458     }
 459   }
 460 }
 461
 462
 463 //===----------------------------------------------------------------------===//
 464 //                         RABasic Implementation
 465 //===----------------------------------------------------------------------===//
 466
 467 // Driver for the register assignment and splitting heuristics.
 468 // Manages iteration over the LiveIntervalUnions.
 469 //
 470 // This is a minimal implementation of register assignment and splitting that
 471 // spills whenever we run out of registers.
 472 //
 473 // selectOrSplit can only be called once per live virtual register. We then do a
 474 // single interference test for each register the correct class until we find an
 475 // available register. So, the number of interference tests in the worst case is
 476 // |vregs| * |machineregs|. And since the number of interference tests is
 477 // minimal, there is no value in caching them outside the scope of
 478 // selectOrSplit().
 479 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
 480                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 481   // Populate a list of physical register spill candidates.
 482   SmallVector<unsigned, 8> PhysRegSpillCands;
 483
 484   // Check for an available register in this class.
 485   ArrayRef<unsigned> Order =
 486     RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
 487   for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
 488        ++I) {
 489     unsigned PhysReg = *I;
 490
 491     // Check interference and as a side effect, intialize queries for this
 492     // VirtReg and its aliases.
 493     unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
 494     if (interfReg == 0) {
 495       // Found an available register.
 496       return PhysReg;
 497     }
 498     LiveInterval *interferingVirtReg =
 499       Queries[interfReg].firstInterference().liveUnionPos().value();
 500
 501     // The current VirtReg must either be spillable, or one of its interferences
 502     // must have less spill weight.
 503     if (interferingVirtReg->weight < VirtReg.weight ) {
 504       PhysRegSpillCands.push_back(PhysReg);
 505     }
 506   }
 507   // Try to spill another interfering reg with less spill weight.
 508   for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
 509          PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
 510
 511     if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
 512
 513     assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
 514            "Interference after spill.");
 515     // Tell the caller to allocate to this newly freed physical register.
 516     return *PhysRegI;
 517   }
 518
 519   // No other spill candidates were found, so spill the current VirtReg.
 520   DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
 521   if (!VirtReg.isSpillable())
 522     return ~0u;
 523   LiveRangeEdit LRE(VirtReg, SplitVRegs);
 524   spiller().spill(LRE);
 525
 526   // The live virtual register requesting allocation was spilled, so tell
 527   // the caller not to allocate anything during this round.
 528   return 0;
 529 }
 530
 531 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
 532   DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
 533                << "********** Function: "
 534                << ((Value*)mf.getFunction())->getName() << '\n');
 535
 536   MF = &mf;
 537   DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
 538
 539   RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
 540   SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
 541
 542   allocatePhysRegs();
 543
 544   addMBBLiveIns(MF);
 545
 546   // Diagnostic output before rewriting
 547   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
 548
 549   // optional HTML output
 550   DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
 551
 552   // FIXME: Verification currently must run before VirtRegRewriter. We should
 553   // make the rewriter a separate pass and override verifyAnalysis instead. When
 554   // that happens, verification naturally falls under VerifyMachineCode.
 555 #ifndef NDEBUG
 556   if (VerifyEnabled) {
 557     // Verify accuracy of LiveIntervals. The standard machine code verifier
 558     // ensures that each LiveIntervals covers all uses of the virtual reg.
 559
 560     // FIXME: MachineVerifier is badly broken when using the standard
 561     // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
 562     // inline spiller, some tests fail to verify because the coalescer does not
 563     // always generate verifiable code.
 564     MF->verify(this, "In RABasic::verify");
 565
 566     // Verify that LiveIntervals are partitioned into unions and disjoint within
 567     // the unions.
 568     verify();
 569   }
 570 #endif // !NDEBUG
 571
 572   // Run rewriter
 573   VRM->rewrite(LIS->getSlotIndexes());
 574
 575   // Write out new DBG_VALUE instructions.
 576   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
 577
 578   // The pass output is in VirtRegMap. Release all the transient data.
 579   releaseMemory();
 580
 581   return true;
 582 }
 583
 584 FunctionPass* llvm::createBasicRegisterAllocator()
 585 {
 586   return new RABasic();
 587 }