lib/CodeGen/SelectionDAG/InstrEmitter.cpp

   1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the Emit routines for the SelectionDAG class, which creates
  11 // MachineInstrs based on the decisions of the SelectionDAG instruction
  12 // selection.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "instr-emitter"
  17 #include "InstrEmitter.h"
  18 #include "SDNodeDbgValue.h"
  19 #include "llvm/CodeGen/MachineConstantPool.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/Target/TargetData.h"
  24 #include "llvm/Target/TargetMachine.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetLowering.h"
  27 #include "llvm/ADT/Statistic.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/MathExtras.h"
  31 using namespace llvm;
  32
  33 /// CountResults - The results of target nodes have register or immediate
  34 /// operands first, then an optional chain, and optional glue operands (which do
  35 /// not go into the resulting MachineInstr).
  36 unsigned InstrEmitter::CountResults(SDNode *Node) {
  37   unsigned N = Node->getNumValues();
  38   while (N && Node->getValueType(N - 1) == MVT::Glue)
  39     --N;
  40   if (N && Node->getValueType(N - 1) == MVT::Other)
  41     --N;    // Skip over chain result.
  42   return N;
  43 }
  44
  45 /// CountOperands - The inputs to target nodes have any actual inputs first,
  46 /// followed by an optional chain operand, then an optional glue operand.
  47 /// Compute the number of actual operands that will go into the resulting
  48 /// MachineInstr.
  49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
  50   unsigned N = Node->getNumOperands();
  51   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
  52     --N;
  53   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
  54     --N; // Ignore chain if it exists.
  55   return N;
  56 }
  57
  58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
  59 /// implicit physical register output.
  60 void InstrEmitter::
  61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
  62                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
  63   unsigned VRBase = 0;
  64   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  65     // Just use the input register directly!
  66     SDValue Op(Node, ResNo);
  67     if (IsClone)
  68       VRBaseMap.erase(Op);
  69     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
  70     (void)isNew; // Silence compiler warning.
  71     assert(isNew && "Node emitted out of order - early");
  72     return;
  73   }
  74
  75   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
  76   // the CopyToReg'd destination register instead of creating a new vreg.
  77   bool MatchReg = true;
  78   const TargetRegisterClass *UseRC = NULL;
  79   EVT VT = Node->getValueType(ResNo);
  80
  81   // Stick to the preferred register classes for legal types.
  82   if (TLI->isTypeLegal(VT))
  83     UseRC = TLI->getRegClassFor(VT);
  84
  85   if (!IsClone && !IsCloned)
  86     for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
  87          UI != E; ++UI) {
  88       SDNode *User = *UI;
  89       bool Match = true;
  90       if (User->getOpcode() == ISD::CopyToReg &&
  91           User->getOperand(2).getNode() == Node &&
  92           User->getOperand(2).getResNo() == ResNo) {
  93         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
  94         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
  95           VRBase = DestReg;
  96           Match = false;
  97         } else if (DestReg != SrcReg)
  98           Match = false;
  99       } else {
 100         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
 101           SDValue Op = User->getOperand(i);
 102           if (Op.getNode() != Node || Op.getResNo() != ResNo)
 103             continue;
 104           EVT VT = Node->getValueType(Op.getResNo());
 105           if (VT == MVT::Other || VT == MVT::Glue)
 106             continue;
 107           Match = false;
 108           if (User->isMachineOpcode()) {
 109             const MCInstrDesc &II = TII->get(User->getMachineOpcode());
 110             const TargetRegisterClass *RC = 0;
 111             if (i+II.getNumDefs() < II.getNumOperands())
 112               RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
 113             if (!UseRC)
 114               UseRC = RC;
 115             else if (RC) {
 116               const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
 117               // If multiple uses expect disjoint register classes, we emit
 118               // copies in AddRegisterOperand.
 119               if (ComRC)
 120                 UseRC = ComRC;
 121             }
 122           }
 123         }
 124       }
 125       MatchReg &= Match;
 126       if (VRBase)
 127         break;
 128     }
 129
 130   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
 131   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
 132
 133   // Figure out the register class to create for the destreg.
 134   if (VRBase) {
 135     DstRC = MRI->getRegClass(VRBase);
 136   } else if (UseRC) {
 137     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
 138     DstRC = UseRC;
 139   } else {
 140     DstRC = TLI->getRegClassFor(VT);
 141   }
 142
 143   // If all uses are reading from the src physical register and copying the
 144   // register is either impossible or very expensive, then don't create a copy.
 145   if (MatchReg && SrcRC->getCopyCost() < 0) {
 146     VRBase = SrcReg;
 147   } else {
 148     // Create the reg, emit the copy.
 149     VRBase = MRI->createVirtualRegister(DstRC);
 150     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 151             VRBase).addReg(SrcReg);
 152   }
 153
 154   SDValue Op(Node, ResNo);
 155   if (IsClone)
 156     VRBaseMap.erase(Op);
 157   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 158   (void)isNew; // Silence compiler warning.
 159   assert(isNew && "Node emitted out of order - early");
 160 }
 161
 162 /// getDstOfCopyToRegUse - If the only use of the specified result number of
 163 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
 164 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
 165                                                 unsigned ResNo) const {
 166   if (!Node->hasOneUse())
 167     return 0;
 168
 169   SDNode *User = *Node->use_begin();
 170   if (User->getOpcode() == ISD::CopyToReg &&
 171       User->getOperand(2).getNode() == Node &&
 172       User->getOperand(2).getResNo() == ResNo) {
 173     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 174     if (TargetRegisterInfo::isVirtualRegister(Reg))
 175       return Reg;
 176   }
 177   return 0;
 178 }
 179
 180 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
 181                                        const MCInstrDesc &II,
 182                                        bool IsClone, bool IsCloned,
 183                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 184   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
 185          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
 186
 187   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
 188     // If the specific node value is only used by a CopyToReg and the dest reg
 189     // is a vreg in the same register class, use the CopyToReg'd destination
 190     // register instead of creating a new vreg.
 191     unsigned VRBase = 0;
 192     const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
 193     if (II.OpInfo[i].isOptionalDef()) {
 194       // Optional def must be a physical register.
 195       unsigned NumResults = CountResults(Node);
 196       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
 197       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
 198       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 199     }
 200
 201     if (!VRBase && !IsClone && !IsCloned)
 202       for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 203            UI != E; ++UI) {
 204         SDNode *User = *UI;
 205         if (User->getOpcode() == ISD::CopyToReg &&
 206             User->getOperand(2).getNode() == Node &&
 207             User->getOperand(2).getResNo() == i) {
 208           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 209           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
 210             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
 211             if (RegRC == RC) {
 212               VRBase = Reg;
 213               MI->addOperand(MachineOperand::CreateReg(Reg, true));
 214               break;
 215             }
 216           }
 217         }
 218       }
 219
 220     // Create the result registers for this node and add the result regs to
 221     // the machine instruction.
 222     if (VRBase == 0) {
 223       assert(RC && "Isn't a register operand!");
 224       VRBase = MRI->createVirtualRegister(RC);
 225       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 226     }
 227
 228     SDValue Op(Node, i);
 229     if (IsClone)
 230       VRBaseMap.erase(Op);
 231     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 232     (void)isNew; // Silence compiler warning.
 233     assert(isNew && "Node emitted out of order - early");
 234   }
 235 }
 236
 237 /// getVR - Return the virtual register corresponding to the specified result
 238 /// of the specified node.
 239 unsigned InstrEmitter::getVR(SDValue Op,
 240                              DenseMap<SDValue, unsigned> &VRBaseMap) {
 241   if (Op.isMachineOpcode() &&
 242       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
 243     // Add an IMPLICIT_DEF instruction before every use.
 244     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
 245     // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
 246     // does not include operand register class info.
 247     if (!VReg) {
 248       const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
 249       VReg = MRI->createVirtualRegister(RC);
 250     }
 251     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
 252             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
 253     return VReg;
 254   }
 255
 256   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 257   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
 258   return I->second;
 259 }
 260
 261
 262 /// AddRegisterOperand - Add the specified register as an operand to the
 263 /// specified machine instr. Insert register copies if the register is
 264 /// not in the required register class.
 265 void
 266 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
 267                                  unsigned IIOpNum,
 268                                  const MCInstrDesc *II,
 269                                  DenseMap<SDValue, unsigned> &VRBaseMap,
 270                                  bool IsDebug, bool IsClone, bool IsCloned) {
 271   assert(Op.getValueType() != MVT::Other &&
 272          Op.getValueType() != MVT::Glue &&
 273          "Chain and glue operands should occur at end of operand list!");
 274   // Get/emit the operand.
 275   unsigned VReg = getVR(Op, VRBaseMap);
 276   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
 277
 278   const MCInstrDesc &MCID = MI->getDesc();
 279   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
 280     MCID.OpInfo[IIOpNum].isOptionalDef();
 281
 282   // If the instruction requires a register in a different class, create
 283   // a new virtual register and copy the value into it.
 284   if (II) {
 285     const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
 286     const TargetRegisterClass *DstRC = 0;
 287     if (IIOpNum < II->getNumOperands())
 288       DstRC = TII->getRegClass(*II, IIOpNum, TRI);
 289     assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
 290            "Don't have operand info for this instruction!");
 291     if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {
 292       unsigned NewVReg = MRI->createVirtualRegister(DstRC);
 293       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
 294               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
 295       VReg = NewVReg;
 296     }
 297   }
 298
 299   // If this value has only one use, that use is a kill. This is a
 300   // conservative approximation. InstrEmitter does trivial coalescing
 301   // with CopyFromReg nodes, so don't emit kill flags for them.
 302   // Avoid kill flags on Schedule cloned nodes, since there will be
 303   // multiple uses.
 304   // Tied operands are never killed, so we need to check that. And that
 305   // means we need to determine the index of the operand.
 306   bool isKill = Op.hasOneUse() &&
 307                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
 308                 !IsDebug &&
 309                 !(IsClone || IsCloned);
 310   if (isKill) {
 311     unsigned Idx = MI->getNumOperands();
 312     while (Idx > 0 &&
 313            MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
 314       --Idx;
 315     bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
 316     if (isTied)
 317       isKill = false;
 318   }
 319
 320   MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
 321                                            false/*isImp*/, isKill,
 322                                            false/*isDead*/, false/*isUndef*/,
 323                                            false/*isEarlyClobber*/,
 324                                            0/*SubReg*/, IsDebug));
 325 }
 326
 327 /// AddOperand - Add the specified operand to the specified machine instr.  II
 328 /// specifies the instruction information for the node, and IIOpNum is the
 329 /// operand number (in the II) that we are adding. IIOpNum and II are used for
 330 /// assertions only.
 331 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
 332                               unsigned IIOpNum,
 333                               const MCInstrDesc *II,
 334                               DenseMap<SDValue, unsigned> &VRBaseMap,
 335                               bool IsDebug, bool IsClone, bool IsCloned) {
 336   if (Op.isMachineOpcode()) {
 337     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
 338                        IsDebug, IsClone, IsCloned);
 339   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 340     MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
 341   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
 342     const ConstantFP *CFP = F->getConstantFPValue();
 343     MI->addOperand(MachineOperand::CreateFPImm(CFP));
 344   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
 345     MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
 346   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
 347     MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
 348                                             TGA->getTargetFlags()));
 349   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
 350     MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
 351   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
 352     MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
 353   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
 354     MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
 355                                              JT->getTargetFlags()));
 356   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
 357     int Offset = CP->getOffset();
 358     unsigned Align = CP->getAlignment();
 359     const Type *Type = CP->getType();
 360     // MachineConstantPool wants an explicit alignment.
 361     if (Align == 0) {
 362       Align = TM->getTargetData()->getPrefTypeAlignment(Type);
 363       if (Align == 0) {
 364         // Alignment of vector types.  FIXME!
 365         Align = TM->getTargetData()->getTypeAllocSize(Type);
 366       }
 367     }
 368
 369     unsigned Idx;
 370     MachineConstantPool *MCP = MF->getConstantPool();
 371     if (CP->isMachineConstantPoolEntry())
 372       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
 373     else
 374       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
 375     MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
 376                                              CP->getTargetFlags()));
 377   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
 378     MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
 379                                             ES->getTargetFlags()));
 380   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
 381     MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
 382                                             BA->getTargetFlags()));
 383   } else {
 384     assert(Op.getValueType() != MVT::Other &&
 385            Op.getValueType() != MVT::Glue &&
 386            "Chain and glue operands should occur at end of operand list!");
 387     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
 388                        IsDebug, IsClone, IsCloned);
 389   }
 390 }
 391
 392 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
 393 /// "SubIdx"'th sub-register class is the specified register class and whose
 394 /// type matches the specified type.
 395 static const TargetRegisterClass*
 396 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
 397                          unsigned SubIdx, EVT VT) {
 398   // Pick the register class of the superegister for this type
 399   for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
 400          E = TRC->superregclasses_end(); I != E; ++I)
 401     if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
 402       return *I;
 403   assert(false && "Couldn't find the register class");
 404   return 0;
 405 }
 406
 407 /// EmitSubregNode - Generate machine code for subreg nodes.
 408 ///
 409 void InstrEmitter::EmitSubregNode(SDNode *Node,
 410                                   DenseMap<SDValue, unsigned> &VRBaseMap,
 411                                   bool IsClone, bool IsCloned) {
 412   unsigned VRBase = 0;
 413   unsigned Opc = Node->getMachineOpcode();
 414
 415   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
 416   // the CopyToReg'd destination register instead of creating a new vreg.
 417   for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 418        UI != E; ++UI) {
 419     SDNode *User = *UI;
 420     if (User->getOpcode() == ISD::CopyToReg &&
 421         User->getOperand(2).getNode() == Node) {
 422       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 423       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
 424         VRBase = DestReg;
 425         break;
 426       }
 427     }
 428   }
 429
 430   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
 431     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
 432     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 433
 434     // Figure out the register class to create for the destreg.
 435     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 436     MachineInstr *DefMI = MRI->getVRegDef(VReg);
 437     unsigned SrcReg, DstReg, DefSubIdx;
 438     if (DefMI &&
 439         TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
 440         SubIdx == DefSubIdx) {
 441       // Optimize these:
 442       // r1025 = s/zext r1024, 4
 443       // r1026 = extract_subreg r1025, 4
 444       // to a copy
 445       // r1026 = copy r1024
 446       const TargetRegisterClass *TRC = MRI->getRegClass(SrcReg);
 447       VRBase = MRI->createVirtualRegister(TRC);
 448       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
 449               TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
 450     } else {
 451       const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
 452       const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
 453       assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
 454
 455       // Figure out the register class to create for the destreg.
 456       // Note that if we're going to directly use an existing register,
 457       // it must be precisely the required class, and not a subclass
 458       // thereof.
 459       if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
 460         // Create the reg
 461         assert(SRC && "Couldn't find source register class");
 462         VRBase = MRI->createVirtualRegister(SRC);
 463       }
 464
 465       // Create the extract_subreg machine instruction.
 466       MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 467                                  TII->get(TargetOpcode::COPY), VRBase);
 468
 469       // Add source, and subreg index
 470       AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
 471                  IsClone, IsCloned);
 472       assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg())&&
 473              "Cannot yet extract from physregs");
 474       MI->getOperand(1).setSubReg(SubIdx);
 475       MBB->insert(InsertPos, MI);
 476     }
 477   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
 478              Opc == TargetOpcode::SUBREG_TO_REG) {
 479     SDValue N0 = Node->getOperand(0);
 480     SDValue N1 = Node->getOperand(1);
 481     SDValue N2 = Node->getOperand(2);
 482     unsigned SubReg = getVR(N1, VRBaseMap);
 483     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
 484     const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
 485     const TargetRegisterClass *SRC =
 486       getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
 487
 488     // Figure out the register class to create for the destreg.
 489     // Note that if we're going to directly use an existing register,
 490     // it must be precisely the required class, and not a subclass
 491     // thereof.
 492     if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
 493       // Create the reg
 494       assert(SRC && "Couldn't find source register class");
 495       VRBase = MRI->createVirtualRegister(SRC);
 496     }
 497
 498     // Create the insert_subreg or subreg_to_reg machine instruction.
 499     MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
 500     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 501
 502     // If creating a subreg_to_reg, then the first input operand
 503     // is an implicit value immediate, otherwise it's a register
 504     if (Opc == TargetOpcode::SUBREG_TO_REG) {
 505       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
 506       MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
 507     } else
 508       AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
 509                  IsClone, IsCloned);
 510     // Add the subregster being inserted
 511     AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
 512                IsClone, IsCloned);
 513     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 514     MBB->insert(InsertPos, MI);
 515   } else
 516     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
 517
 518   SDValue Op(Node, 0);
 519   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 520   (void)isNew; // Silence compiler warning.
 521   assert(isNew && "Node emitted out of order - early");
 522 }
 523
 524 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
 525 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
 526 /// register is constrained to be in a particular register class.
 527 ///
 528 void
 529 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
 530                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
 531   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 532
 533   // Create the new VReg in the destination class and emit a copy.
 534   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 535   const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
 536   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
 537   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 538     NewVReg).addReg(VReg);
 539
 540   SDValue Op(Node, 0);
 541   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
 542   (void)isNew; // Silence compiler warning.
 543   assert(isNew && "Node emitted out of order - early");
 544 }
 545
 546 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
 547 ///
 548 void InstrEmitter::EmitRegSequence(SDNode *Node,
 549                                   DenseMap<SDValue, unsigned> &VRBaseMap,
 550                                   bool IsClone, bool IsCloned) {
 551   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
 552   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
 553   unsigned NewVReg = MRI->createVirtualRegister(RC);
 554   MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 555                              TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
 556   unsigned NumOps = Node->getNumOperands();
 557   assert((NumOps & 1) == 1 &&
 558          "REG_SEQUENCE must have an odd number of operands!");
 559   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
 560   for (unsigned i = 1; i != NumOps; ++i) {
 561     SDValue Op = Node->getOperand(i);
 562     if ((i & 1) == 0) {
 563       unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
 564       unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
 565       const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
 566       const TargetRegisterClass *SRC =
 567         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
 568       if (SRC && SRC != RC) {
 569         MRI->setRegClass(NewVReg, SRC);
 570         RC = SRC;
 571       }
 572     }
 573     AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
 574                IsClone, IsCloned);
 575   }
 576
 577   MBB->insert(InsertPos, MI);
 578   SDValue Op(Node, 0);
 579   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
 580   (void)isNew; // Silence compiler warning.
 581   assert(isNew && "Node emitted out of order - early");
 582 }
 583
 584 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
 585 ///
 586 MachineInstr *
 587 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
 588                            DenseMap<SDValue, unsigned> &VRBaseMap) {
 589   uint64_t Offset = SD->getOffset();
 590   MDNode* MDPtr = SD->getMDPtr();
 591   DebugLoc DL = SD->getDebugLoc();
 592
 593   if (SD->getKind() == SDDbgValue::FRAMEIX) {
 594     // Stack address; this needs to be lowered in target-dependent fashion.
 595     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
 596     unsigned FrameIx = SD->getFrameIx();
 597     return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
 598   }
 599   // Otherwise, we're going to create an instruction here.
 600   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
 601   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
 602   if (SD->getKind() == SDDbgValue::SDNODE) {
 603     SDNode *Node = SD->getSDNode();
 604     SDValue Op = SDValue(Node, SD->getResNo());
 605     // It's possible we replaced this SDNode with other(s) and therefore
 606     // didn't generate code for it.  It's better to catch these cases where
 607     // they happen and transfer the debug info, but trying to guarantee that
 608     // in all cases would be very fragile; this is a safeguard for any
 609     // that were missed.
 610     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 611     if (I==VRBaseMap.end())
 612       MIB.addReg(0U);       // undef
 613     else
 614       AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
 615                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
 616   } else if (SD->getKind() == SDDbgValue::CONST) {
 617     const Value *V = SD->getConst();
 618     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
 619       if (CI->getBitWidth() > 64)
 620         MIB.addCImm(CI);
 621       else
 622         MIB.addImm(CI->getSExtValue());
 623     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
 624       MIB.addFPImm(CF);
 625     } else {
 626       // Could be an Undef.  In any case insert an Undef so we can see what we
 627       // dropped.
 628       MIB.addReg(0U);
 629     }
 630   } else {
 631     // Insert an Undef so we can see what we dropped.
 632     MIB.addReg(0U);
 633   }
 634
 635   MIB.addImm(Offset).addMetadata(MDPtr);
 636   return &*MIB;
 637 }
 638
 639 /// EmitMachineNode - Generate machine code for a target-specific node and
 640 /// needed dependencies.
 641 ///
 642 void InstrEmitter::
 643 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
 644                 DenseMap<SDValue, unsigned> &VRBaseMap) {
 645   unsigned Opc = Node->getMachineOpcode();
 646
 647   // Handle subreg insert/extract specially
 648   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
 649       Opc == TargetOpcode::INSERT_SUBREG ||
 650       Opc == TargetOpcode::SUBREG_TO_REG) {
 651     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
 652     return;
 653   }
 654
 655   // Handle COPY_TO_REGCLASS specially.
 656   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
 657     EmitCopyToRegClassNode(Node, VRBaseMap);
 658     return;
 659   }
 660
 661   // Handle REG_SEQUENCE specially.
 662   if (Opc == TargetOpcode::REG_SEQUENCE) {
 663     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
 664     return;
 665   }
 666
 667   if (Opc == TargetOpcode::IMPLICIT_DEF)
 668     // We want a unique VR for each IMPLICIT_DEF use.
 669     return;
 670
 671   const MCInstrDesc &II = TII->get(Opc);
 672   unsigned NumResults = CountResults(Node);
 673   unsigned NodeOperands = CountOperands(Node);
 674   bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
 675 #ifndef NDEBUG
 676   unsigned NumMIOperands = NodeOperands + NumResults;
 677   if (II.isVariadic())
 678     assert(NumMIOperands >= II.getNumOperands() &&
 679            "Too few operands for a variadic node!");
 680   else
 681     assert(NumMIOperands >= II.getNumOperands() &&
 682            NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
 683            "#operands for dag node doesn't match .td file!");
 684 #endif
 685
 686   // Create the new machine instruction.
 687   MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
 688
 689   // The MachineInstr constructor adds implicit-def operands. Scan through
 690   // these to determine which are dead.
 691   if (MI->getNumOperands() != 0 &&
 692       Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
 693     // First, collect all used registers.
 694     SmallVector<unsigned, 8> UsedRegs;
 695     for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser())
 696       if (F->getOpcode() == ISD::CopyFromReg)
 697         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
 698       else {
 699         // Collect declared implicit uses.
 700         const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
 701         UsedRegs.append(MCID.getImplicitUses(),
 702                         MCID.getImplicitUses() + MCID.getNumImplicitUses());
 703         // In addition to declared implicit uses, we must also check for
 704         // direct RegisterSDNode operands.
 705         for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
 706           if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
 707             unsigned Reg = R->getReg();
 708             if (TargetRegisterInfo::isPhysicalRegister(Reg))
 709               UsedRegs.push_back(Reg);
 710           }
 711       }
 712     // Then mark unused registers as dead.
 713     MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
 714   }
 715
 716   // Add result register values for things that are defined by this
 717   // instruction.
 718   if (NumResults)
 719     CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
 720
 721   // Emit all of the actual operands of this instruction, adding them to the
 722   // instruction as appropriate.
 723   bool HasOptPRefs = II.getNumDefs() > NumResults;
 724   assert((!HasOptPRefs || !HasPhysRegOuts) &&
 725          "Unable to cope with optional defs and phys regs defs!");
 726   unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
 727   for (unsigned i = NumSkip; i != NodeOperands; ++i)
 728     AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
 729                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
 730
 731   // Transfer all of the memory reference descriptions of this instruction.
 732   MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
 733                  cast<MachineSDNode>(Node)->memoperands_end());
 734
 735   // Insert the instruction into position in the block. This needs to
 736   // happen before any custom inserter hook is called so that the
 737   // hook knows where in the block to insert the replacement code.
 738   MBB->insert(InsertPos, MI);
 739
 740   // Additional results must be physical register defs.
 741   if (HasPhysRegOuts) {
 742     for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
 743       unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
 744       if (Node->hasAnyUseOfValue(i))
 745         EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
 746       // If there are no uses, mark the register as dead now, so that
 747       // MachineLICM/Sink can see that it's dead. Don't do this if the
 748       // node has a Glue value, for the benefit of targets still using
 749       // Glue for values in physregs.
 750       else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
 751         MI->addRegisterDead(Reg, TRI);
 752     }
 753   }
 754
 755   // If the instruction has implicit defs and the node doesn't, mark the
 756   // implicit def as dead.  If the node has any glue outputs, we don't do this
 757   // because we don't know what implicit defs are being used by glued nodes.
 758   if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
 759     if (const unsigned *IDList = II.getImplicitDefs()) {
 760       for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
 761            i != e; ++i)
 762         MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
 763     }
 764 }
 765
 766 /// EmitSpecialNode - Generate machine code for a target-independent node and
 767 /// needed dependencies.
 768 void InstrEmitter::
 769 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
 770                 DenseMap<SDValue, unsigned> &VRBaseMap) {
 771   switch (Node->getOpcode()) {
 772   default:
 773 #ifndef NDEBUG
 774     Node->dump();
 775 #endif
 776     llvm_unreachable("This target-independent node should have been selected!");
 777     break;
 778   case ISD::EntryToken:
 779     llvm_unreachable("EntryToken should have been excluded from the schedule!");
 780     break;
 781   case ISD::MERGE_VALUES:
 782   case ISD::TokenFactor: // fall thru
 783     break;
 784   case ISD::CopyToReg: {
 785     unsigned SrcReg;
 786     SDValue SrcVal = Node->getOperand(2);
 787     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
 788       SrcReg = R->getReg();
 789     else
 790       SrcReg = getVR(SrcVal, VRBaseMap);
 791
 792     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 793     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
 794       break;
 795
 796     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
 797             DestReg).addReg(SrcReg);
 798     break;
 799   }
 800   case ISD::CopyFromReg: {
 801     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 802     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
 803     break;
 804   }
 805   case ISD::EH_LABEL: {
 806     MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
 807     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
 808             TII->get(TargetOpcode::EH_LABEL)).addSym(S);
 809     break;
 810   }
 811
 812   case ISD::INLINEASM: {
 813     unsigned NumOps = Node->getNumOperands();
 814     if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
 815       --NumOps;  // Ignore the glue operand.
 816
 817     // Create the inline asm machine instruction.
 818     MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
 819                                TII->get(TargetOpcode::INLINEASM));
 820
 821     // Add the asm string as an external symbol operand.
 822     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
 823     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
 824     MI->addOperand(MachineOperand::CreateES(AsmStr));
 825
 826     // Add the HasSideEffect and isAlignStack bits.
 827     int64_t ExtraInfo =
 828       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
 829                           getZExtValue();
 830     MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
 831
 832     // Add all of the operand registers to the instruction.
 833     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
 834       unsigned Flags =
 835         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
 836       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 837
 838       MI->addOperand(MachineOperand::CreateImm(Flags));
 839       ++i;  // Skip the ID value.
 840
 841       switch (InlineAsm::getKind(Flags)) {
 842       default: llvm_unreachable("Bad flags!");
 843         case InlineAsm::Kind_RegDef:
 844         for (; NumVals; --NumVals, ++i) {
 845           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 846           // FIXME: Add dead flags for physical and virtual registers defined.
 847           // For now, mark physical register defs as implicit to help fast
 848           // regalloc. This makes inline asm look a lot like calls.
 849           MI->addOperand(MachineOperand::CreateReg(Reg, true,
 850                        /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
 851         }
 852         break;
 853       case InlineAsm::Kind_RegDefEarlyClobber:
 854       case InlineAsm::Kind_Clobber:
 855         for (; NumVals; --NumVals, ++i) {
 856           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 857           MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
 858                          /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
 859                                                    /*isKill=*/ false,
 860                                                    /*isDead=*/ false,
 861                                                    /*isUndef=*/false,
 862                                                    /*isEarlyClobber=*/ true));
 863         }
 864         break;
 865       case InlineAsm::Kind_RegUse:  // Use of register.
 866       case InlineAsm::Kind_Imm:  // Immediate.
 867       case InlineAsm::Kind_Mem:  // Addressing mode.
 868         // The addressing mode has been selected, just add all of the
 869         // operands to the machine instruction.
 870         for (; NumVals; --NumVals, ++i)
 871           AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
 872                      /*IsDebug=*/false, IsClone, IsCloned);
 873         break;
 874       }
 875     }
 876
 877     // Get the mdnode from the asm if it exists and add it to the instruction.
 878     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
 879     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
 880     if (MD)
 881       MI->addOperand(MachineOperand::CreateMetadata(MD));
 882
 883     MBB->insert(InsertPos, MI);
 884     break;
 885   }
 886   }
 887 }
 888
 889 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
 890 /// at the given position in the given block.
 891 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
 892                            MachineBasicBlock::iterator insertpos)
 893   : MF(mbb->getParent()),
 894     MRI(&MF->getRegInfo()),
 895     TM(&MF->getTarget()),
 896     TII(TM->getInstrInfo()),
 897     TRI(TM->getRegisterInfo()),
 898     TLI(TM->getTargetLowering()),
 899     MBB(mbb), InsertPos(insertpos) {
 900 }