Don't analyze block if it's not considered for ifcvt anymore.
[llvm/stm8.git] / utils / TableGen / RegisterInfoEmitter.h
blob2c01b5c3bd0665a06745d8208d448a9bb94fdf1f
1 //===- RegisterInfoEmitter.h - Generate a Register File Desc. ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #ifndef REGISTER_INFO_EMITTER_H
17 #define REGISTER_INFO_EMITTER_H
19 #include "TableGenBackend.h"
21 namespace llvm {
23 class CodeGenRegBank;
24 class CodeGenTarget;
26 class RegisterInfoEmitter : public TableGenBackend {
27 RecordKeeper &Records;
28 public:
29 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
31 // runEnums - Print out enum values for all of the registers.
32 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
34 // runMCDesc - Print out MC register descriptions.
35 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
37 // runTargetHeader - Emit a header fragment for the register info emitter.
38 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
39 CodeGenRegBank &Bank);
41 // runTargetDesc - Output the target register and register file descriptions.
42 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
43 CodeGenRegBank &Bank);
45 // run - Output the register file description.
46 void run(raw_ostream &o);
49 } // End llvm namespace
51 #endif