lib/Target/PowerPC/PPCMCCodeEmitter.cpp

   1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the PPCMCCodeEmitter class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "mccodeemitter"
  15 #include "PPC.h"
  16 #include "PPCRegisterInfo.h"
  17 #include "PPCFixupKinds.h"
  18 #include "llvm/MC/MCCodeEmitter.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/ADT/Statistic.h"
  21 #include "llvm/Support/raw_ostream.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 using namespace llvm;
  24
  25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
  26
  27 namespace {
  28 class PPCMCCodeEmitter : public MCCodeEmitter {
  29   PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
  30   void operator=(const PPCMCCodeEmitter &);   // DO NOT IMPLEMENT
  31   const TargetMachine &TM;
  32   MCContext &Ctx;
  33
  34 public:
  35   PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
  36     : TM(tm), Ctx(ctx) {
  37   }
  38
  39   ~PPCMCCodeEmitter() {}
  40
  41   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
  42                                SmallVectorImpl<MCFixup> &Fixups) const;
  43   unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
  44                              SmallVectorImpl<MCFixup> &Fixups) const;
  45   unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
  46                            SmallVectorImpl<MCFixup> &Fixups) const;
  47   unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
  48                            SmallVectorImpl<MCFixup> &Fixups) const;
  49   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
  50                             SmallVectorImpl<MCFixup> &Fixups) const;
  51   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
  52                              SmallVectorImpl<MCFixup> &Fixups) const;
  53   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
  54                                SmallVectorImpl<MCFixup> &Fixups) const;
  55
  56   /// getMachineOpValue - Return binary encoding of operand. If the machine
  57   /// operand requires relocation, record the relocation and return zero.
  58   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
  59                              SmallVectorImpl<MCFixup> &Fixups) const;
  60
  61   // getBinaryCodeForInstr - TableGen'erated function for getting the
  62   // binary encoding for an instruction.
  63   unsigned getBinaryCodeForInstr(const MCInst &MI,
  64                                  SmallVectorImpl<MCFixup> &Fixups) const;
  65   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
  66                          SmallVectorImpl<MCFixup> &Fixups) const {
  67     unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
  68
  69     // Output the constant in big endian byte order.
  70     for (unsigned i = 0; i != 4; ++i) {
  71       OS << (char)(Bits >> 24);
  72       Bits <<= 8;
  73     }
  74
  75     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
  76   }
  77
  78 };
  79
  80 } // end anonymous namespace
  81
  82 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
  83                                             MCContext &Ctx) {
  84   return new PPCMCCodeEmitter(TM, Ctx);
  85 }
  86
  87 unsigned PPCMCCodeEmitter::
  88 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
  89                     SmallVectorImpl<MCFixup> &Fixups) const {
  90   const MCOperand &MO = MI.getOperand(OpNo);
  91   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
  92
  93   // Add a fixup for the branch target.
  94   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
  95                                    (MCFixupKind)PPC::fixup_ppc_br24));
  96   return 0;
  97 }
  98
  99 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
 100                                      SmallVectorImpl<MCFixup> &Fixups) const {
 101   const MCOperand &MO = MI.getOperand(OpNo);
 102   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
 103
 104   // Add a fixup for the branch target.
 105   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
 106                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
 107   return 0;
 108 }
 109
 110 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
 111                                        SmallVectorImpl<MCFixup> &Fixups) const {
 112   const MCOperand &MO = MI.getOperand(OpNo);
 113   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
 114
 115   // Add a fixup for the branch target.
 116   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
 117                                    (MCFixupKind)PPC::fixup_ppc_ha16));
 118   return 0;
 119 }
 120
 121 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
 122                                        SmallVectorImpl<MCFixup> &Fixups) const {
 123   const MCOperand &MO = MI.getOperand(OpNo);
 124   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
 125
 126   // Add a fixup for the branch target.
 127   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
 128                                    (MCFixupKind)PPC::fixup_ppc_lo16));
 129   return 0;
 130 }
 131
 132 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
 133                                             SmallVectorImpl<MCFixup> &Fixups) const {
 134   // Encode (imm, reg) as a memri, which has the low 16-bits as the
 135   // displacement and the next 5 bits as the register #.
 136   assert(MI.getOperand(OpNo+1).isReg());
 137   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
 138
 139   const MCOperand &MO = MI.getOperand(OpNo);
 140   if (MO.isImm())
 141     return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
 142
 143   // Add a fixup for the displacement field.
 144   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
 145                                    (MCFixupKind)PPC::fixup_ppc_lo16));
 146   return RegBits;
 147 }
 148
 149
 150 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
 151                                        SmallVectorImpl<MCFixup> &Fixups) const {
 152   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
 153   // displacement and the next 5 bits as the register #.
 154   assert(MI.getOperand(OpNo+1).isReg());
 155   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
 156
 157   const MCOperand &MO = MI.getOperand(OpNo);
 158   if (MO.isImm())
 159     return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
 160
 161   // Add a fixup for the branch target.
 162   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
 163                                    (MCFixupKind)PPC::fixup_ppc_lo14));
 164   return RegBits;
 165 }
 166
 167
 168 unsigned PPCMCCodeEmitter::
 169 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
 170                     SmallVectorImpl<MCFixup> &Fixups) const {
 171   const MCOperand &MO = MI.getOperand(OpNo);
 172   assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
 173          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
 174   return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
 175 }
 176
 177
 178 unsigned PPCMCCodeEmitter::
 179 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
 180                   SmallVectorImpl<MCFixup> &Fixups) const {
 181   if (MO.isReg()) {
 182     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
 183     // The GPR operand should come through here though.
 184     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
 185            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
 186     return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
 187   }
 188
 189   assert(MO.isImm() &&
 190          "Relocation required in an instruction that we cannot encode!");
 191   return MO.getImm();
 192 }
 193
 194
 195 #include "PPCGenMCCodeEmitter.inc"