lib/Target/CellSPU/SPUInstrInfo.cpp

   1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SPURegisterNames.h"
  15 #include "SPUInstrInfo.h"
  16 #include "SPUInstrBuilder.h"
  17 #include "SPUTargetMachine.h"
  18 #include "SPUGenInstrInfo.inc"
  19 #include "SPUHazardRecognizers.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/Support/Debug.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 #include "llvm/Support/raw_ostream.h"
  24 #include "llvm/MC/MCContext.h"
  25
  26 using namespace llvm;
  27
  28 namespace {
  29   //! Predicate for an unconditional branch instruction
  30   inline bool isUncondBranch(const MachineInstr *I) {
  31     unsigned opc = I->getOpcode();
  32
  33     return (opc == SPU::BR
  34             || opc == SPU::BRA
  35             || opc == SPU::BI);
  36   }
  37
  38   //! Predicate for a conditional branch instruction
  39   inline bool isCondBranch(const MachineInstr *I) {
  40     unsigned opc = I->getOpcode();
  41
  42     return (opc == SPU::BRNZr32
  43             || opc == SPU::BRNZv4i32
  44             || opc == SPU::BRZr32
  45             || opc == SPU::BRZv4i32
  46             || opc == SPU::BRHNZr16
  47             || opc == SPU::BRHNZv8i16
  48             || opc == SPU::BRHZr16
  49             || opc == SPU::BRHZv8i16);
  50   }
  51 }
  52
  53 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
  54   : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
  55     TM(tm),
  56     RI(*TM.getSubtargetImpl(), *this)
  57 { /* NOP */ }
  58
  59 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
  60 /// this target when scheduling the DAG.
  61 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
  62   const TargetMachine *TM,
  63   const ScheduleDAG *DAG) const {
  64   const TargetInstrInfo *TII = TM->getInstrInfo();
  65   assert(TII && "No InstrInfo?");
  66   return new SPUHazardRecognizer(*TII);
  67 }
  68
  69 unsigned
  70 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  71                                   int &FrameIndex) const {
  72   switch (MI->getOpcode()) {
  73   default: break;
  74   case SPU::LQDv16i8:
  75   case SPU::LQDv8i16:
  76   case SPU::LQDv4i32:
  77   case SPU::LQDv4f32:
  78   case SPU::LQDv2f64:
  79   case SPU::LQDr128:
  80   case SPU::LQDr64:
  81   case SPU::LQDr32:
  82   case SPU::LQDr16: {
  83     const MachineOperand MOp1 = MI->getOperand(1);
  84     const MachineOperand MOp2 = MI->getOperand(2);
  85     if (MOp1.isImm() && MOp2.isFI()) {
  86       FrameIndex = MOp2.getIndex();
  87       return MI->getOperand(0).getReg();
  88     }
  89     break;
  90   }
  91   }
  92   return 0;
  93 }
  94
  95 unsigned
  96 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  97                                  int &FrameIndex) const {
  98   switch (MI->getOpcode()) {
  99   default: break;
 100   case SPU::STQDv16i8:
 101   case SPU::STQDv8i16:
 102   case SPU::STQDv4i32:
 103   case SPU::STQDv4f32:
 104   case SPU::STQDv2f64:
 105   case SPU::STQDr128:
 106   case SPU::STQDr64:
 107   case SPU::STQDr32:
 108   case SPU::STQDr16:
 109   case SPU::STQDr8: {
 110     const MachineOperand MOp1 = MI->getOperand(1);
 111     const MachineOperand MOp2 = MI->getOperand(2);
 112     if (MOp1.isImm() && MOp2.isFI()) {
 113       FrameIndex = MOp2.getIndex();
 114       return MI->getOperand(0).getReg();
 115     }
 116     break;
 117   }
 118   }
 119   return 0;
 120 }
 121
 122 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 123                                MachineBasicBlock::iterator I, DebugLoc DL,
 124                                unsigned DestReg, unsigned SrcReg,
 125                                bool KillSrc) const
 126 {
 127   // We support cross register class moves for our aliases, such as R3 in any
 128   // reg class to any other reg class containing R3.  This is required because
 129   // we instruction select bitconvert i64 -> f64 as a noop for example, so our
 130   // types have no specific meaning.
 131
 132   BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
 133     .addReg(SrcReg, getKillRegState(KillSrc));
 134 }
 135
 136 void
 137 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 138                                   MachineBasicBlock::iterator MI,
 139                                   unsigned SrcReg, bool isKill, int FrameIdx,
 140                                   const TargetRegisterClass *RC,
 141                                   const TargetRegisterInfo *TRI) const
 142 {
 143   unsigned opc;
 144   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
 145   if (RC == SPU::GPRCRegisterClass) {
 146     opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
 147   } else if (RC == SPU::R64CRegisterClass) {
 148     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 149   } else if (RC == SPU::R64FPRegisterClass) {
 150     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 151   } else if (RC == SPU::R32CRegisterClass) {
 152     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 153   } else if (RC == SPU::R32FPRegisterClass) {
 154     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 155   } else if (RC == SPU::R16CRegisterClass) {
 156     opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
 157   } else if (RC == SPU::R8CRegisterClass) {
 158     opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
 159   } else if (RC == SPU::VECREGRegisterClass) {
 160     opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
 161   } else {
 162     llvm_unreachable("Unknown regclass!");
 163   }
 164
 165   DebugLoc DL;
 166   if (MI != MBB.end()) DL = MI->getDebugLoc();
 167   addFrameReference(BuildMI(MBB, MI, DL, get(opc))
 168                     .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
 169 }
 170
 171 void
 172 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 173                                    MachineBasicBlock::iterator MI,
 174                                    unsigned DestReg, int FrameIdx,
 175                                    const TargetRegisterClass *RC,
 176                                    const TargetRegisterInfo *TRI) const
 177 {
 178   unsigned opc;
 179   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
 180   if (RC == SPU::GPRCRegisterClass) {
 181     opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
 182   } else if (RC == SPU::R64CRegisterClass) {
 183     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 184   } else if (RC == SPU::R64FPRegisterClass) {
 185     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 186   } else if (RC == SPU::R32CRegisterClass) {
 187     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 188   } else if (RC == SPU::R32FPRegisterClass) {
 189     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 190   } else if (RC == SPU::R16CRegisterClass) {
 191     opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
 192   } else if (RC == SPU::R8CRegisterClass) {
 193     opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
 194   } else if (RC == SPU::VECREGRegisterClass) {
 195     opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
 196   } else {
 197     llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
 198   }
 199
 200   DebugLoc DL;
 201   if (MI != MBB.end()) DL = MI->getDebugLoc();
 202   addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
 203 }
 204
 205 //! Branch analysis
 206 /*!
 207   \note This code was kiped from PPC. There may be more branch analysis for
 208   CellSPU than what's currently done here.
 209  */
 210 bool
 211 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 212                             MachineBasicBlock *&FBB,
 213                             SmallVectorImpl<MachineOperand> &Cond,
 214                             bool AllowModify) const {
 215   // If the block has no terminators, it just falls into the block after it.
 216   MachineBasicBlock::iterator I = MBB.end();
 217   if (I == MBB.begin())
 218     return false;
 219   --I;
 220   while (I->isDebugValue()) {
 221     if (I == MBB.begin())
 222       return false;
 223     --I;
 224   }
 225   if (!isUnpredicatedTerminator(I))
 226     return false;
 227
 228   // Get the last instruction in the block.
 229   MachineInstr *LastInst = I;
 230
 231   // If there is only one terminator instruction, process it.
 232   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 233     if (isUncondBranch(LastInst)) {
 234       // Check for jump tables
 235       if (!LastInst->getOperand(0).isMBB())
 236         return true;
 237       TBB = LastInst->getOperand(0).getMBB();
 238       return false;
 239     } else if (isCondBranch(LastInst)) {
 240       // Block ends with fall-through condbranch.
 241       TBB = LastInst->getOperand(1).getMBB();
 242       DEBUG(errs() << "Pushing LastInst:               ");
 243       DEBUG(LastInst->dump());
 244       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
 245       Cond.push_back(LastInst->getOperand(0));
 246       return false;
 247     }
 248     // Otherwise, don't know what this is.
 249     return true;
 250   }
 251
 252   // Get the instruction before it if it's a terminator.
 253   MachineInstr *SecondLastInst = I;
 254
 255   // If there are three terminators, we don't know what sort of block this is.
 256   if (SecondLastInst && I != MBB.begin() &&
 257       isUnpredicatedTerminator(--I))
 258     return true;
 259
 260   // If the block ends with a conditional and unconditional branch, handle it.
 261   if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 262     TBB =  SecondLastInst->getOperand(1).getMBB();
 263     DEBUG(errs() << "Pushing SecondLastInst:         ");
 264     DEBUG(SecondLastInst->dump());
 265     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
 266     Cond.push_back(SecondLastInst->getOperand(0));
 267     FBB = LastInst->getOperand(0).getMBB();
 268     return false;
 269   }
 270
 271   // If the block ends with two unconditional branches, handle it.  The second
 272   // one is not executed, so remove it.
 273   if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 274     TBB = SecondLastInst->getOperand(0).getMBB();
 275     I = LastInst;
 276     if (AllowModify)
 277       I->eraseFromParent();
 278     return false;
 279   }
 280
 281   // Otherwise, can't handle this.
 282   return true;
 283 }
 284
 285 // search MBB for branch hint labels and branch hit ops
 286 static void removeHBR( MachineBasicBlock &MBB) {
 287   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
 288     if (I->getOpcode() == SPU::HBRA ||
 289         I->getOpcode() == SPU::HBR_LABEL){
 290       I=MBB.erase(I);
 291     }
 292   }
 293 }
 294
 295 unsigned
 296 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 297   MachineBasicBlock::iterator I = MBB.end();
 298   removeHBR(MBB);
 299   if (I == MBB.begin())
 300     return 0;
 301   --I;
 302   while (I->isDebugValue()) {
 303     if (I == MBB.begin())
 304       return 0;
 305     --I;
 306   }
 307   if (!isCondBranch(I) && !isUncondBranch(I))
 308     return 0;
 309
 310   // Remove the first branch.
 311   DEBUG(errs() << "Removing branch:                ");
 312   DEBUG(I->dump());
 313   I->eraseFromParent();
 314   I = MBB.end();
 315   if (I == MBB.begin())
 316     return 1;
 317
 318   --I;
 319   if (!(isCondBranch(I) || isUncondBranch(I)))
 320     return 1;
 321
 322   // Remove the second branch.
 323   DEBUG(errs() << "Removing second branch:         ");
 324   DEBUG(I->dump());
 325   I->eraseFromParent();
 326   return 2;
 327 }
 328
 329 /** Find the optimal position for a hint branch instruction in a basic block.
 330  * This should take into account:
 331  *   -the branch hint delays
 332  *   -congestion of the memory bus
 333  *   -dual-issue scheduling (i.e. avoid insertion of nops)
 334  * Current implementation is rather simplistic.
 335  */
 336 static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
 337 {
 338    MachineBasicBlock::iterator J = MBB.end();
 339         for( int i=0; i<8; i++) {
 340                 if( J == MBB.begin() ) return J;
 341                 J--;
 342         }
 343         return J;
 344 }
 345
 346 unsigned
 347 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 348                            MachineBasicBlock *FBB,
 349                            const SmallVectorImpl<MachineOperand> &Cond,
 350                            DebugLoc DL) const {
 351   // Shouldn't be a fall through.
 352   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 353   assert((Cond.size() == 2 || Cond.size() == 0) &&
 354          "SPU branch conditions have two components!");
 355
 356   MachineInstrBuilder MIB;
 357   //TODO: make a more accurate algorithm.
 358   bool haveHBR = MBB.size()>8;
 359
 360   removeHBR(MBB);
 361   MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
 362   // Add a label just before the branch
 363   if (haveHBR)
 364     MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
 365
 366   // One-way branch.
 367   if (FBB == 0) {
 368     if (Cond.empty()) {
 369       // Unconditional branch
 370       MIB = BuildMI(&MBB, DL, get(SPU::BR));
 371       MIB.addMBB(TBB);
 372
 373       DEBUG(errs() << "Inserted one-way uncond branch: ");
 374       DEBUG((*MIB).dump());
 375
 376       // basic blocks have just one branch so it is safe to add the hint a its
 377       if (haveHBR) {
 378         MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
 379         MIB.addSym(branchLabel);
 380         MIB.addMBB(TBB);
 381       }
 382     } else {
 383       // Conditional branch
 384       MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
 385       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 386
 387       if (haveHBR) {
 388         MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
 389         MIB.addSym(branchLabel);
 390         MIB.addMBB(TBB);
 391       }
 392
 393       DEBUG(errs() << "Inserted one-way cond branch:   ");
 394       DEBUG((*MIB).dump());
 395     }
 396     return 1;
 397   } else {
 398     MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
 399     MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
 400
 401     // Two-way Conditional Branch.
 402     MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 403     MIB2.addMBB(FBB);
 404
 405     if (haveHBR) {
 406       MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
 407       MIB.addSym(branchLabel);
 408       MIB.addMBB(FBB);
 409     }
 410
 411     DEBUG(errs() << "Inserted conditional branch:    ");
 412     DEBUG((*MIB).dump());
 413     DEBUG(errs() << "part 2: ");
 414     DEBUG((*MIB2).dump());
 415    return 2;
 416   }
 417 }
 418
 419 //! Reverses a branch's condition, returning false on success.
 420 bool
 421 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
 422   const {
 423   // Pretty brainless way of inverting the condition, but it works, considering
 424   // there are only two conditions...
 425   static struct {
 426     unsigned Opc;               //! The incoming opcode
 427     unsigned RevCondOpc;        //! The reversed condition opcode
 428   } revconds[] = {
 429     { SPU::BRNZr32, SPU::BRZr32 },
 430     { SPU::BRNZv4i32, SPU::BRZv4i32 },
 431     { SPU::BRZr32, SPU::BRNZr32 },
 432     { SPU::BRZv4i32, SPU::BRNZv4i32 },
 433     { SPU::BRHNZr16, SPU::BRHZr16 },
 434     { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
 435     { SPU::BRHZr16, SPU::BRHNZr16 },
 436     { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
 437   };
 438
 439   unsigned Opc = unsigned(Cond[0].getImm());
 440   // Pretty dull mapping between the two conditions that SPU can generate:
 441   for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
 442     if (revconds[i].Opc == Opc) {
 443       Cond[0].setImm(revconds[i].RevCondOpc);
 444       return false;
 445     }
 446   }
 447
 448   return true;
 449 }