lib/Target/Sparc/SparcInstrInfo.cpp

   1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Sparc implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SparcInstrInfo.h"
  15 #include "SparcSubtarget.h"
  16 #include "Sparc.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "SparcGenInstrInfo.inc"
  23 #include "SparcMachineFunctionInfo.h"
  24 using namespace llvm;
  25
  26 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
  27   : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
  28     RI(ST, *this), Subtarget(ST) {
  29 }
  30
  31 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  32 /// load from a stack slot, return the virtual or physical register number of
  33 /// the destination along with the FrameIndex of the loaded stack slot.  If
  34 /// not, return 0.  This predicate must return 0 if the instruction has
  35 /// any side effects other than loading from the stack slot.
  36 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  37                                              int &FrameIndex) const {
  38   if (MI->getOpcode() == SP::LDri ||
  39       MI->getOpcode() == SP::LDFri ||
  40       MI->getOpcode() == SP::LDDFri) {
  41     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
  42         MI->getOperand(2).getImm() == 0) {
  43       FrameIndex = MI->getOperand(1).getIndex();
  44       return MI->getOperand(0).getReg();
  45     }
  46   }
  47   return 0;
  48 }
  49
  50 /// isStoreToStackSlot - If the specified machine instruction is a direct
  51 /// store to a stack slot, return the virtual or physical register number of
  52 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  53 /// not, return 0.  This predicate must return 0 if the instruction has
  54 /// any side effects other than storing to the stack slot.
  55 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  56                                             int &FrameIndex) const {
  57   if (MI->getOpcode() == SP::STri ||
  58       MI->getOpcode() == SP::STFri ||
  59       MI->getOpcode() == SP::STDFri) {
  60     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
  61         MI->getOperand(1).getImm() == 0) {
  62       FrameIndex = MI->getOperand(0).getIndex();
  63       return MI->getOperand(2).getReg();
  64     }
  65   }
  66   return 0;
  67 }
  68
  69 static bool IsIntegerCC(unsigned CC)
  70 {
  71   return  (CC <= SPCC::ICC_VC);
  72 }
  73
  74
  75 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
  76 {
  77   switch(CC) {
  78   default: llvm_unreachable("Unknown condition code");
  79   case SPCC::ICC_NE:   return SPCC::ICC_E;
  80   case SPCC::ICC_E:    return SPCC::ICC_NE;
  81   case SPCC::ICC_G:    return SPCC::ICC_LE;
  82   case SPCC::ICC_LE:   return SPCC::ICC_G;
  83   case SPCC::ICC_GE:   return SPCC::ICC_L;
  84   case SPCC::ICC_L:    return SPCC::ICC_GE;
  85   case SPCC::ICC_GU:   return SPCC::ICC_LEU;
  86   case SPCC::ICC_LEU:  return SPCC::ICC_GU;
  87   case SPCC::ICC_CC:   return SPCC::ICC_CS;
  88   case SPCC::ICC_CS:   return SPCC::ICC_CC;
  89   case SPCC::ICC_POS:  return SPCC::ICC_NEG;
  90   case SPCC::ICC_NEG:  return SPCC::ICC_POS;
  91   case SPCC::ICC_VC:   return SPCC::ICC_VS;
  92   case SPCC::ICC_VS:   return SPCC::ICC_VC;
  93
  94   case SPCC::FCC_U:    return SPCC::FCC_O;
  95   case SPCC::FCC_O:    return SPCC::FCC_U;
  96   case SPCC::FCC_G:    return SPCC::FCC_LE;
  97   case SPCC::FCC_LE:   return SPCC::FCC_G;
  98   case SPCC::FCC_UG:   return SPCC::FCC_ULE;
  99   case SPCC::FCC_ULE:  return SPCC::FCC_UG;
 100   case SPCC::FCC_L:    return SPCC::FCC_GE;
 101   case SPCC::FCC_GE:   return SPCC::FCC_L;
 102   case SPCC::FCC_UL:   return SPCC::FCC_UGE;
 103   case SPCC::FCC_UGE:  return SPCC::FCC_UL;
 104   case SPCC::FCC_LG:   return SPCC::FCC_UE;
 105   case SPCC::FCC_UE:   return SPCC::FCC_LG;
 106   case SPCC::FCC_NE:   return SPCC::FCC_E;
 107   case SPCC::FCC_E:    return SPCC::FCC_NE;
 108   }
 109 }
 110
 111
 112 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
 113                                    MachineBasicBlock *&TBB,
 114                                    MachineBasicBlock *&FBB,
 115                                    SmallVectorImpl<MachineOperand> &Cond,
 116                                    bool AllowModify) const
 117 {
 118
 119   MachineBasicBlock::iterator I = MBB.end();
 120   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
 121   while (I != MBB.begin()) {
 122     --I;
 123
 124     if (I->isDebugValue())
 125       continue;
 126
 127     //When we see a non-terminator, we are done
 128     if (!isUnpredicatedTerminator(I))
 129       break;
 130
 131     //Terminator is not a branch
 132     if (!I->getDesc().isBranch())
 133       return true;
 134
 135     //Handle Unconditional branches
 136     if (I->getOpcode() == SP::BA) {
 137       UnCondBrIter = I;
 138
 139       if (!AllowModify) {
 140         TBB = I->getOperand(0).getMBB();
 141         continue;
 142       }
 143
 144       while (llvm::next(I) != MBB.end())
 145         llvm::next(I)->eraseFromParent();
 146
 147       Cond.clear();
 148       FBB = 0;
 149
 150       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
 151         TBB = 0;
 152         I->eraseFromParent();
 153         I = MBB.end();
 154         UnCondBrIter = MBB.end();
 155         continue;
 156       }
 157
 158       TBB = I->getOperand(0).getMBB();
 159       continue;
 160     }
 161
 162     unsigned Opcode = I->getOpcode();
 163     if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
 164       return true; //Unknown Opcode
 165
 166     SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
 167
 168     if (Cond.empty()) {
 169       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
 170       if (AllowModify && UnCondBrIter != MBB.end() &&
 171           MBB.isLayoutSuccessor(TargetBB)) {
 172
 173         //Transform the code
 174         //
 175         //    brCC L1
 176         //    ba L2
 177         // L1:
 178         //    ..
 179         // L2:
 180         //
 181         // into
 182         //
 183         //   brnCC L2
 184         // L1:
 185         //   ...
 186         // L2:
 187         //
 188         BranchCode = GetOppositeBranchCondition(BranchCode);
 189         MachineBasicBlock::iterator OldInst = I;
 190         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
 191           .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
 192         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
 193           .addMBB(TargetBB);
 194         MBB.addSuccessor(TargetBB);
 195         OldInst->eraseFromParent();
 196         UnCondBrIter->eraseFromParent();
 197
 198         UnCondBrIter = MBB.end();
 199         I = MBB.end();
 200         continue;
 201       }
 202       FBB = TBB;
 203       TBB = I->getOperand(0).getMBB();
 204       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 205       continue;
 206     }
 207     //FIXME: Handle subsequent conditional branches
 208     //For now, we can't handle multiple conditional branches
 209     return true;
 210   }
 211   return false;
 212 }
 213
 214 unsigned
 215 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
 216                              MachineBasicBlock *FBB,
 217                              const SmallVectorImpl<MachineOperand> &Cond,
 218                              DebugLoc DL) const {
 219   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 220   assert((Cond.size() == 1 || Cond.size() == 0) &&
 221          "Sparc branch conditions should have one component!");
 222
 223   if (Cond.empty()) {
 224     assert(!FBB && "Unconditional branch with multiple successors!");
 225     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
 226     return 1;
 227   }
 228
 229   //Conditional branch
 230   unsigned CC = Cond[0].getImm();
 231
 232   if (IsIntegerCC(CC))
 233     BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
 234   else
 235     BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
 236   if (!FBB)
 237     return 1;
 238
 239   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
 240   return 2;
 241 }
 242
 243 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
 244 {
 245   MachineBasicBlock::iterator I = MBB.end();
 246   unsigned Count = 0;
 247   while (I != MBB.begin()) {
 248     --I;
 249
 250     if (I->isDebugValue())
 251       continue;
 252
 253     if (I->getOpcode() != SP::BA
 254         && I->getOpcode() != SP::BCOND
 255         && I->getOpcode() != SP::FBCOND)
 256       break; // Not a branch
 257
 258     I->eraseFromParent();
 259     I = MBB.end();
 260     ++Count;
 261   }
 262   return Count;
 263 }
 264
 265 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 266                                  MachineBasicBlock::iterator I, DebugLoc DL,
 267                                  unsigned DestReg, unsigned SrcReg,
 268                                  bool KillSrc) const {
 269   if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
 270     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
 271       .addReg(SrcReg, getKillRegState(KillSrc));
 272   else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
 273     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
 274       .addReg(SrcReg, getKillRegState(KillSrc));
 275   else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
 276     BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
 277       .addReg(SrcReg, getKillRegState(KillSrc));
 278   else
 279     llvm_unreachable("Impossible reg-to-reg copy");
 280 }
 281
 282 void SparcInstrInfo::
 283 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 284                     unsigned SrcReg, bool isKill, int FI,
 285                     const TargetRegisterClass *RC,
 286                     const TargetRegisterInfo *TRI) const {
 287   DebugLoc DL;
 288   if (I != MBB.end()) DL = I->getDebugLoc();
 289
 290   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
 291   if (RC == SP::IntRegsRegisterClass)
 292     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
 293       .addReg(SrcReg, getKillRegState(isKill));
 294   else if (RC == SP::FPRegsRegisterClass)
 295     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
 296       .addReg(SrcReg,  getKillRegState(isKill));
 297   else if (RC == SP::DFPRegsRegisterClass)
 298     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
 299       .addReg(SrcReg,  getKillRegState(isKill));
 300   else
 301     llvm_unreachable("Can't store this register to stack slot");
 302 }
 303
 304 void SparcInstrInfo::
 305 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 306                      unsigned DestReg, int FI,
 307                      const TargetRegisterClass *RC,
 308                      const TargetRegisterInfo *TRI) const {
 309   DebugLoc DL;
 310   if (I != MBB.end()) DL = I->getDebugLoc();
 311
 312   if (RC == SP::IntRegsRegisterClass)
 313     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
 314   else if (RC == SP::FPRegsRegisterClass)
 315     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
 316   else if (RC == SP::DFPRegsRegisterClass)
 317     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
 318   else
 319     llvm_unreachable("Can't load this register from stack slot");
 320 }
 321
 322 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
 323 {
 324   SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
 325   unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
 326   if (GlobalBaseReg != 0)
 327     return GlobalBaseReg;
 328
 329   // Insert the set of GlobalBaseReg into the first MBB of the function
 330   MachineBasicBlock &FirstMBB = MF->front();
 331   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
 332   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 333
 334   GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
 335
 336
 337   DebugLoc dl;
 338
 339   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
 340   SparcFI->setGlobalBaseReg(GlobalBaseReg);
 341   return GlobalBaseReg;
 342 }