lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp

   1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file includes code for rendering MCInst instances as AT&T-style
  11 // assembly.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "asm-printer"
  16 #include "X86ATTInstPrinter.h"
  17 #include "X86InstComments.h"
  18 #include "X86Subtarget.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCAsmInfo.h"
  21 #include "llvm/MC/MCExpr.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 #include "llvm/Support/Format.h"
  24 #include "llvm/Support/FormattedStream.h"
  25 #include "X86GenInstrNames.inc"
  26 #include <map>
  27 using namespace llvm;
  28
  29 // Include the auto-generated portion of the assembly writer.
  30 #define GET_INSTRUCTION_NAME
  31 #define PRINT_ALIAS_INSTR
  32 #include "X86GenRegisterNames.inc"
  33 #include "X86GenAsmWriter.inc"
  34 #undef PRINT_ALIAS_INSTR
  35 #undef GET_INSTRUCTION_NAME
  36
  37 X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
  38   : MCInstPrinter(MAI) {
  39   // Initialize the set of available features.
  40   setAvailableFeatures(ComputeAvailableFeatures(
  41             &TM.getSubtarget<X86Subtarget>()));
  42 }
  43
  44 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
  45   printInstruction(MI, OS);
  46
  47   // If verbose assembly is enabled, we can print some informative comments.
  48   if (CommentStream)
  49     EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
  50 }
  51
  52 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
  53   return getInstructionName(Opcode);
  54 }
  55
  56 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
  57                                    raw_ostream &O) {
  58   switch (MI->getOperand(Op).getImm()) {
  59   default: assert(0 && "Invalid ssecc argument!");
  60   case 0: O << "eq"; break;
  61   case 1: O << "lt"; break;
  62   case 2: O << "le"; break;
  63   case 3: O << "unord"; break;
  64   case 4: O << "neq"; break;
  65   case 5: O << "nlt"; break;
  66   case 6: O << "nle"; break;
  67   case 7: O << "ord"; break;
  68   }
  69 }
  70
  71 /// print_pcrel_imm - This is used to print an immediate value that ends up
  72 /// being encoded as a pc-relative value (e.g. for jumps and calls).  These
  73 /// print slightly differently than normal immediates.  For example, a $ is not
  74 /// emitted.
  75 void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
  76                                         raw_ostream &O) {
  77   const MCOperand &Op = MI->getOperand(OpNo);
  78   if (Op.isImm())
  79     // Print this as a signed 32-bit value.
  80     O << (int)Op.getImm();
  81   else {
  82     assert(Op.isExpr() && "unknown pcrel immediate operand");
  83     O << *Op.getExpr();
  84   }
  85 }
  86
  87 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
  88                                      raw_ostream &O) {
  89   const MCOperand &Op = MI->getOperand(OpNo);
  90   if (Op.isReg()) {
  91     O << '%' << getRegisterName(Op.getReg());
  92   } else if (Op.isImm()) {
  93     O << '$' << Op.getImm();
  94
  95     if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
  96       *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm());
  97
  98   } else {
  99     assert(Op.isExpr() && "unknown operand kind in printOperand");
 100     O << '$' << *Op.getExpr();
 101   }
 102 }
 103
 104 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
 105                                           raw_ostream &O) {
 106   const MCOperand &BaseReg  = MI->getOperand(Op);
 107   const MCOperand &IndexReg = MI->getOperand(Op+2);
 108   const MCOperand &DispSpec = MI->getOperand(Op+3);
 109   const MCOperand &SegReg = MI->getOperand(Op+4);
 110
 111   // If this has a segment register, print it.
 112   if (SegReg.getReg()) {
 113     printOperand(MI, Op+4, O);
 114     O << ':';
 115   }
 116
 117   if (DispSpec.isImm()) {
 118     int64_t DispVal = DispSpec.getImm();
 119     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
 120       O << DispVal;
 121   } else {
 122     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
 123     O << *DispSpec.getExpr();
 124   }
 125
 126   if (IndexReg.getReg() || BaseReg.getReg()) {
 127     O << '(';
 128     if (BaseReg.getReg())
 129       printOperand(MI, Op, O);
 130
 131     if (IndexReg.getReg()) {
 132       O << ',';
 133       printOperand(MI, Op+2, O);
 134       unsigned ScaleVal = MI->getOperand(Op+1).getImm();
 135       if (ScaleVal != 1)
 136         O << ',' << ScaleVal;
 137     }
 138     O << ')';
 139   }
 140 }