lib/Target/X86/X86AsmBackend.cpp

   1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/Target/TargetAsmBackend.h"
  11 #include "X86.h"
  12 #include "X86FixupKinds.h"
  13 #include "llvm/ADT/Twine.h"
  14 #include "llvm/MC/MCAssembler.h"
  15 #include "llvm/MC/MCELFObjectWriter.h"
  16 #include "llvm/MC/MCExpr.h"
  17 #include "llvm/MC/MCFixupKindInfo.h"
  18 #include "llvm/MC/MCMachObjectWriter.h"
  19 #include "llvm/MC/MCObjectWriter.h"
  20 #include "llvm/MC/MCSectionCOFF.h"
  21 #include "llvm/MC/MCSectionELF.h"
  22 #include "llvm/MC/MCSectionMachO.h"
  23 #include "llvm/Object/MachOFormat.h"
  24 #include "llvm/Support/ELF.h"
  25 #include "llvm/Support/ErrorHandling.h"
  26 #include "llvm/Support/raw_ostream.h"
  27 #include "llvm/Target/TargetRegistry.h"
  28 #include "llvm/Target/TargetAsmBackend.h"
  29 using namespace llvm;
  30
  31 static unsigned getFixupKindLog2Size(unsigned Kind) {
  32   switch (Kind) {
  33   default: assert(0 && "invalid fixup kind!");
  34   case FK_PCRel_1:
  35   case FK_Data_1: return 0;
  36   case FK_PCRel_2:
  37   case FK_Data_2: return 1;
  38   case FK_PCRel_4:
  39   case X86::reloc_riprel_4byte:
  40   case X86::reloc_riprel_4byte_movq_load:
  41   case X86::reloc_signed_4byte:
  42   case X86::reloc_global_offset_table:
  43   case FK_Data_4: return 2;
  44   case FK_PCRel_8:
  45   case FK_Data_8: return 3;
  46   }
  47 }
  48
  49 namespace {
  50
  51 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
  52 public:
  53   X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
  54                      bool HasRelocationAddend)
  55     : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
  56 };
  57
  58 class X86AsmBackend : public TargetAsmBackend {
  59 public:
  60   X86AsmBackend(const Target &T)
  61     : TargetAsmBackend() {}
  62
  63   unsigned getNumFixupKinds() const {
  64     return X86::NumTargetFixupKinds;
  65   }
  66
  67   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
  68     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
  69       { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
  70       { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
  71       { "reloc_signed_4byte", 0, 4 * 8, 0},
  72       { "reloc_global_offset_table", 0, 4 * 8, 0}
  73     };
  74
  75     if (Kind < FirstTargetFixupKind)
  76       return TargetAsmBackend::getFixupKindInfo(Kind);
  77
  78     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
  79            "Invalid kind!");
  80     return Infos[Kind - FirstTargetFixupKind];
  81   }
  82
  83   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
  84                   uint64_t Value) const {
  85     unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
  86
  87     assert(Fixup.getOffset() + Size <= DataSize &&
  88            "Invalid fixup offset!");
  89     for (unsigned i = 0; i != Size; ++i)
  90       Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
  91   }
  92
  93   bool MayNeedRelaxation(const MCInst &Inst) const;
  94
  95   void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
  96
  97   bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
  98 };
  99 } // end anonymous namespace
 100
 101 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
 102   switch (Op) {
 103   default:
 104     return Op;
 105
 106   case X86::JAE_1: return X86::JAE_4;
 107   case X86::JA_1:  return X86::JA_4;
 108   case X86::JBE_1: return X86::JBE_4;
 109   case X86::JB_1:  return X86::JB_4;
 110   case X86::JE_1:  return X86::JE_4;
 111   case X86::JGE_1: return X86::JGE_4;
 112   case X86::JG_1:  return X86::JG_4;
 113   case X86::JLE_1: return X86::JLE_4;
 114   case X86::JL_1:  return X86::JL_4;
 115   case X86::JMP_1: return X86::JMP_4;
 116   case X86::JNE_1: return X86::JNE_4;
 117   case X86::JNO_1: return X86::JNO_4;
 118   case X86::JNP_1: return X86::JNP_4;
 119   case X86::JNS_1: return X86::JNS_4;
 120   case X86::JO_1:  return X86::JO_4;
 121   case X86::JP_1:  return X86::JP_4;
 122   case X86::JS_1:  return X86::JS_4;
 123   }
 124 }
 125
 126 static unsigned getRelaxedOpcodeArith(unsigned Op) {
 127   switch (Op) {
 128   default:
 129     return Op;
 130
 131     // IMUL
 132   case X86::IMUL16rri8: return X86::IMUL16rri;
 133   case X86::IMUL16rmi8: return X86::IMUL16rmi;
 134   case X86::IMUL32rri8: return X86::IMUL32rri;
 135   case X86::IMUL32rmi8: return X86::IMUL32rmi;
 136   case X86::IMUL64rri8: return X86::IMUL64rri32;
 137   case X86::IMUL64rmi8: return X86::IMUL64rmi32;
 138
 139     // AND
 140   case X86::AND16ri8: return X86::AND16ri;
 141   case X86::AND16mi8: return X86::AND16mi;
 142   case X86::AND32ri8: return X86::AND32ri;
 143   case X86::AND32mi8: return X86::AND32mi;
 144   case X86::AND64ri8: return X86::AND64ri32;
 145   case X86::AND64mi8: return X86::AND64mi32;
 146
 147     // OR
 148   case X86::OR16ri8: return X86::OR16ri;
 149   case X86::OR16mi8: return X86::OR16mi;
 150   case X86::OR32ri8: return X86::OR32ri;
 151   case X86::OR32mi8: return X86::OR32mi;
 152   case X86::OR64ri8: return X86::OR64ri32;
 153   case X86::OR64mi8: return X86::OR64mi32;
 154
 155     // XOR
 156   case X86::XOR16ri8: return X86::XOR16ri;
 157   case X86::XOR16mi8: return X86::XOR16mi;
 158   case X86::XOR32ri8: return X86::XOR32ri;
 159   case X86::XOR32mi8: return X86::XOR32mi;
 160   case X86::XOR64ri8: return X86::XOR64ri32;
 161   case X86::XOR64mi8: return X86::XOR64mi32;
 162
 163     // ADD
 164   case X86::ADD16ri8: return X86::ADD16ri;
 165   case X86::ADD16mi8: return X86::ADD16mi;
 166   case X86::ADD32ri8: return X86::ADD32ri;
 167   case X86::ADD32mi8: return X86::ADD32mi;
 168   case X86::ADD64ri8: return X86::ADD64ri32;
 169   case X86::ADD64mi8: return X86::ADD64mi32;
 170
 171     // SUB
 172   case X86::SUB16ri8: return X86::SUB16ri;
 173   case X86::SUB16mi8: return X86::SUB16mi;
 174   case X86::SUB32ri8: return X86::SUB32ri;
 175   case X86::SUB32mi8: return X86::SUB32mi;
 176   case X86::SUB64ri8: return X86::SUB64ri32;
 177   case X86::SUB64mi8: return X86::SUB64mi32;
 178
 179     // CMP
 180   case X86::CMP16ri8: return X86::CMP16ri;
 181   case X86::CMP16mi8: return X86::CMP16mi;
 182   case X86::CMP32ri8: return X86::CMP32ri;
 183   case X86::CMP32mi8: return X86::CMP32mi;
 184   case X86::CMP64ri8: return X86::CMP64ri32;
 185   case X86::CMP64mi8: return X86::CMP64mi32;
 186
 187     // PUSH
 188   case X86::PUSHi8: return X86::PUSHi32;
 189   }
 190 }
 191
 192 static unsigned getRelaxedOpcode(unsigned Op) {
 193   unsigned R = getRelaxedOpcodeArith(Op);
 194   if (R != Op)
 195     return R;
 196   return getRelaxedOpcodeBranch(Op);
 197 }
 198
 199 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
 200   // Branches can always be relaxed.
 201   if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
 202     return true;
 203
 204   // Check if this instruction is ever relaxable.
 205   if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
 206     return false;
 207
 208
 209   // Check if it has an expression and is not RIP relative.
 210   bool hasExp = false;
 211   bool hasRIP = false;
 212   for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
 213     const MCOperand &Op = Inst.getOperand(i);
 214     if (Op.isExpr())
 215       hasExp = true;
 216
 217     if (Op.isReg() && Op.getReg() == X86::RIP)
 218       hasRIP = true;
 219   }
 220
 221   // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
 222   // how we do relaxations?
 223   return hasExp && !hasRIP;
 224 }
 225
 226 // FIXME: Can tblgen help at all here to verify there aren't other instructions
 227 // we can relax?
 228 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
 229   // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
 230   unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
 231
 232   if (RelaxedOp == Inst.getOpcode()) {
 233     SmallString<256> Tmp;
 234     raw_svector_ostream OS(Tmp);
 235     Inst.dump_pretty(OS);
 236     OS << "\n";
 237     report_fatal_error("unexpected instruction to relax: " + OS.str());
 238   }
 239
 240   Res = Inst;
 241   Res.setOpcode(RelaxedOp);
 242 }
 243
 244 /// WriteNopData - Write optimal nops to the output file for the \arg Count
 245 /// bytes.  This returns the number of bytes written.  It may return 0 if
 246 /// the \arg Count is more than the maximum optimal nops.
 247 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
 248   static const uint8_t Nops[10][10] = {
 249     // nop
 250     {0x90},
 251     // xchg %ax,%ax
 252     {0x66, 0x90},
 253     // nopl (%[re]ax)
 254     {0x0f, 0x1f, 0x00},
 255     // nopl 0(%[re]ax)
 256     {0x0f, 0x1f, 0x40, 0x00},
 257     // nopl 0(%[re]ax,%[re]ax,1)
 258     {0x0f, 0x1f, 0x44, 0x00, 0x00},
 259     // nopw 0(%[re]ax,%[re]ax,1)
 260     {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
 261     // nopl 0L(%[re]ax)
 262     {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
 263     // nopl 0L(%[re]ax,%[re]ax,1)
 264     {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 265     // nopw 0L(%[re]ax,%[re]ax,1)
 266     {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 267     // nopw %cs:0L(%[re]ax,%[re]ax,1)
 268     {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 269   };
 270
 271   // Write an optimal sequence for the first 15 bytes.
 272   const uint64_t OptimalCount = (Count < 16) ? Count : 15;
 273   const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
 274   for (uint64_t i = 0, e = Prefixes; i != e; i++)
 275     OW->Write8(0x66);
 276   const uint64_t Rest = OptimalCount - Prefixes;
 277   for (uint64_t i = 0, e = Rest; i != e; i++)
 278     OW->Write8(Nops[Rest - 1][i]);
 279
 280   // Finish with single byte nops.
 281   for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
 282    OW->Write8(0x90);
 283
 284   return true;
 285 }
 286
 287 /* *** */
 288
 289 namespace {
 290 class ELFX86AsmBackend : public X86AsmBackend {
 291 public:
 292   Triple::OSType OSType;
 293   ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
 294     : X86AsmBackend(T), OSType(_OSType) {
 295     HasReliableSymbolDifference = true;
 296   }
 297
 298   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
 299     const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
 300     return ES.getFlags() & ELF::SHF_MERGE;
 301   }
 302 };
 303
 304 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
 305 public:
 306   ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
 307     : ELFX86AsmBackend(T, OSType) {}
 308
 309   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 310     return createELFObjectWriter(createELFObjectTargetWriter(),
 311                                  OS, /*IsLittleEndian*/ true);
 312   }
 313
 314   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
 315     return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
 316   }
 317 };
 318
 319 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 320 public:
 321   ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
 322     : ELFX86AsmBackend(T, OSType) {}
 323
 324   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 325     return createELFObjectWriter(createELFObjectTargetWriter(),
 326                                  OS, /*IsLittleEndian*/ true);
 327   }
 328
 329   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
 330     return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
 331   }
 332 };
 333
 334 class WindowsX86AsmBackend : public X86AsmBackend {
 335   bool Is64Bit;
 336
 337 public:
 338   WindowsX86AsmBackend(const Target &T, bool is64Bit)
 339     : X86AsmBackend(T)
 340     , Is64Bit(is64Bit) {
 341   }
 342
 343   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 344     return createWinCOFFObjectWriter(OS, Is64Bit);
 345   }
 346 };
 347
 348 class DarwinX86AsmBackend : public X86AsmBackend {
 349 public:
 350   DarwinX86AsmBackend(const Target &T)
 351     : X86AsmBackend(T) { }
 352 };
 353
 354 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
 355 public:
 356   DarwinX86_32AsmBackend(const Target &T)
 357     : DarwinX86AsmBackend(T) {}
 358
 359   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 360     return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
 361                                      object::mach::CTM_i386,
 362                                      object::mach::CSX86_ALL);
 363   }
 364 };
 365
 366 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
 367 public:
 368   DarwinX86_64AsmBackend(const Target &T)
 369     : DarwinX86AsmBackend(T) {
 370     HasReliableSymbolDifference = true;
 371   }
 372
 373   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 374     return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
 375                                      object::mach::CTM_x86_64,
 376                                      object::mach::CSX86_ALL);
 377   }
 378
 379   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
 380     // Temporary labels in the string literals sections require symbols. The
 381     // issue is that the x86_64 relocation format does not allow symbol +
 382     // offset, and so the linker does not have enough information to resolve the
 383     // access to the appropriate atom unless an external relocation is used. For
 384     // non-cstring sections, we expect the compiler to use a non-temporary label
 385     // for anything that could have an addend pointing outside the symbol.
 386     //
 387     // See <rdar://problem/4765733>.
 388     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
 389     return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
 390   }
 391
 392   virtual bool isSectionAtomizable(const MCSection &Section) const {
 393     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
 394     // Fixed sized data sections are uniqued, they cannot be diced into atoms.
 395     switch (SMO.getType()) {
 396     default:
 397       return true;
 398
 399     case MCSectionMachO::S_4BYTE_LITERALS:
 400     case MCSectionMachO::S_8BYTE_LITERALS:
 401     case MCSectionMachO::S_16BYTE_LITERALS:
 402     case MCSectionMachO::S_LITERAL_POINTERS:
 403     case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
 404     case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
 405     case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
 406     case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
 407     case MCSectionMachO::S_INTERPOSING:
 408       return false;
 409     }
 410   }
 411 };
 412
 413 } // end anonymous namespace
 414
 415 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
 416                                                const std::string &TT) {
 417   switch (Triple(TT).getOS()) {
 418   case Triple::Darwin:
 419     return new DarwinX86_32AsmBackend(T);
 420   case Triple::MinGW32:
 421   case Triple::Cygwin:
 422   case Triple::Win32:
 423     if (Triple(TT).getEnvironment() == Triple::MachO)
 424       return new DarwinX86_32AsmBackend(T);
 425     else
 426       return new WindowsX86AsmBackend(T, false);
 427   default:
 428     return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
 429   }
 430 }
 431
 432 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
 433                                                const std::string &TT) {
 434   switch (Triple(TT).getOS()) {
 435   case Triple::Darwin:
 436     return new DarwinX86_64AsmBackend(T);
 437   case Triple::MinGW32:
 438   case Triple::Cygwin:
 439   case Triple::Win32:
 440     if (Triple(TT).getEnvironment() == Triple::MachO)
 441       return new DarwinX86_64AsmBackend(T);
 442     else
 443       return new WindowsX86AsmBackend(T, true);
 444   default:
 445     return new ELFX86_64AsmBackend(T, Triple(TT).getOS());
 446   }
 447 }