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[llvm/stm8.git] / lib / Target / X86 / X86CodeEmitter.cpp
blob421e221d205cb7d26f0458cf803d935701811e72
1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
21 #include "X86.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
38 using namespace llvm;
39
40 STATISTIC(NumEmitted, "Number of machine instructions emitted");
41
42 namespace {
43 template<class CodeEmitter>
44 class Emitter : public MachineFunctionPass {
45 const X86InstrInfo *II;
46 const TargetData *TD;
47 X86TargetMachine &TM;
48 CodeEmitter &MCE;
49 MachineModuleInfo *MMI;
50 intptr_t PICBaseOffset;
51 bool Is64BitMode;
52 bool IsPIC;
53 public:
54 static char ID;
55 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
56 : MachineFunctionPass(ID), II(0), TD(0), TM(tm),
57 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
59 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
60 const X86InstrInfo &ii, const TargetData &td, bool is64)
61 : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm),
62 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
63 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
64
65 bool runOnMachineFunction(MachineFunction &MF);
66
67 virtual const char *getPassName() const {
68 return "X86 Machine Code Emitter";
69 }
70
71 void emitInstruction(MachineInstr &MI, const TargetInstrDesc *Desc);
72
73 void getAnalysisUsage(AnalysisUsage &AU) const {
74 AU.setPreservesAll();
75 AU.addRequired<MachineModuleInfo>();
76 MachineFunctionPass::getAnalysisUsage(AU);
77 }
78
79 private:
80 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
81 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
82 intptr_t Disp = 0, intptr_t PCAdj = 0,
83 bool Indirect = false);
84 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
85 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
86 intptr_t PCAdj = 0);
87 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
88 intptr_t PCAdj = 0);
89
90 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
91 intptr_t Adj = 0, bool IsPCRel = true);
92
93 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
94 void emitRegModRMByte(unsigned RegOpcodeField);
95 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
96 void emitConstant(uint64_t Val, unsigned Size);
97
98 void emitMemModRMByte(const MachineInstr &MI,
99 unsigned Op, unsigned RegOpcodeField,
100 intptr_t PCAdj = 0);
101
102 unsigned getX86RegNum(unsigned RegNo) const;
103 };
104
105 template<class CodeEmitter>
106 char Emitter<CodeEmitter>::ID = 0;
107 } // end anonymous namespace.
108
109 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
110 /// to the specified templated MachineCodeEmitter object.
111 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
112 JITCodeEmitter &JCE) {
113 return new Emitter<JITCodeEmitter>(TM, JCE);
114 }
115
116 template<class CodeEmitter>
117 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
118 MMI = &getAnalysis<MachineModuleInfo>();
119 MCE.setModuleInfo(MMI);
120
121 II = TM.getInstrInfo();
122 TD = TM.getTargetData();
123 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
124 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
125
126 do {
127 DEBUG(dbgs() << "JITTing function '"
128 << MF.getFunction()->getName() << "'\n");
129 MCE.startFunction(MF);
130 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
131 MBB != E; ++MBB) {
132 MCE.StartMachineBasicBlock(MBB);
133 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
134 I != E; ++I) {
135 const TargetInstrDesc &Desc = I->getDesc();
136 emitInstruction(*I, &Desc);
137 // MOVPC32r is basically a call plus a pop instruction.
138 if (Desc.getOpcode() == X86::MOVPC32r)
139 emitInstruction(*I, &II->get(X86::POP32r));
140 ++NumEmitted; // Keep track of the # of mi's emitted
141 }
142 }
143 } while (MCE.finishFunction(MF));
144
145 return false;
146 }
147
148 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
149 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
150 /// size, and 3) use of X86-64 extended registers.
151 static unsigned determineREX(const MachineInstr &MI) {
152 unsigned REX = 0;
153 const TargetInstrDesc &Desc = MI.getDesc();
154
155 // Pseudo instructions do not need REX prefix byte.
156 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
157 return 0;
158 if (Desc.TSFlags & X86II::REX_W)
159 REX |= 1 << 3;
160
161 unsigned NumOps = Desc.getNumOperands();
162 if (NumOps) {
163 bool isTwoAddr = NumOps > 1 &&
164 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
165
166 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
167 unsigned i = isTwoAddr ? 1 : 0;
168 for (unsigned e = NumOps; i != e; ++i) {
169 const MachineOperand& MO = MI.getOperand(i);
170 if (MO.isReg()) {
171 unsigned Reg = MO.getReg();
172 if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
173 REX |= 0x40;
174 }
175 }
176
177 switch (Desc.TSFlags & X86II::FormMask) {
178 case X86II::MRMInitReg:
179 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
180 REX |= (1 << 0) | (1 << 2);
181 break;
182 case X86II::MRMSrcReg: {
183 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
184 REX |= 1 << 2;
185 i = isTwoAddr ? 2 : 1;
186 for (unsigned e = NumOps; i != e; ++i) {
187 const MachineOperand& MO = MI.getOperand(i);
188 if (X86InstrInfo::isX86_64ExtendedReg(MO))
189 REX |= 1 << 0;
190 }
191 break;
192 }
193 case X86II::MRMSrcMem: {
194 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
195 REX |= 1 << 2;
196 unsigned Bit = 0;
197 i = isTwoAddr ? 2 : 1;
198 for (; i != NumOps; ++i) {
199 const MachineOperand& MO = MI.getOperand(i);
200 if (MO.isReg()) {
201 if (X86InstrInfo::isX86_64ExtendedReg(MO))
202 REX |= 1 << Bit;
203 Bit++;
204 }
205 }
206 break;
207 }
208 case X86II::MRM0m: case X86II::MRM1m:
209 case X86II::MRM2m: case X86II::MRM3m:
210 case X86II::MRM4m: case X86II::MRM5m:
211 case X86II::MRM6m: case X86II::MRM7m:
212 case X86II::MRMDestMem: {
213 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
214 i = isTwoAddr ? 1 : 0;
215 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
216 REX |= 1 << 2;
217 unsigned Bit = 0;
218 for (; i != e; ++i) {
219 const MachineOperand& MO = MI.getOperand(i);
220 if (MO.isReg()) {
221 if (X86InstrInfo::isX86_64ExtendedReg(MO))
222 REX |= 1 << Bit;
223 Bit++;
224 }
225 }
226 break;
227 }
228 default: {
229 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
230 REX |= 1 << 0;
231 i = isTwoAddr ? 2 : 1;
232 for (unsigned e = NumOps; i != e; ++i) {
233 const MachineOperand& MO = MI.getOperand(i);
234 if (X86InstrInfo::isX86_64ExtendedReg(MO))
235 REX |= 1 << 2;
236 }
237 break;
238 }
239 }
240 }
241 return REX;
242 }
243
244
245 /// emitPCRelativeBlockAddress - This method keeps track of the information
246 /// necessary to resolve the address of this block later and emits a dummy
247 /// value.
248 ///
249 template<class CodeEmitter>
250 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
251 // Remember where this reference was and where it is to so we can
252 // deal with it later.
253 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
254 X86::reloc_pcrel_word, MBB));
255 MCE.emitWordLE(0);
256 }
257
258 /// emitGlobalAddress - Emit the specified address to the code stream assuming
259 /// this is part of a "take the address of a global" instruction.
260 ///
261 template<class CodeEmitter>
262 void Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV,
263 unsigned Reloc,
264 intptr_t Disp /* = 0 */,
265 intptr_t PCAdj /* = 0 */,
266 bool Indirect /* = false */) {
267 intptr_t RelocCST = Disp;
268 if (Reloc == X86::reloc_picrel_word)
269 RelocCST = PICBaseOffset;
270 else if (Reloc == X86::reloc_pcrel_word)
271 RelocCST = PCAdj;
272 MachineRelocation MR = Indirect
273 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
274 const_cast<GlobalValue *>(GV),
275 RelocCST, false)
276 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
277 const_cast<GlobalValue *>(GV), RelocCST, false);
278 MCE.addRelocation(MR);
279 // The relocated value will be added to the displacement
280 if (Reloc == X86::reloc_absolute_dword)
281 MCE.emitDWordLE(Disp);
282 else
283 MCE.emitWordLE((int32_t)Disp);
284 }
285
286 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
287 /// be emitted to the current location in the function, and allow it to be PC
288 /// relative.
289 template<class CodeEmitter>
290 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
291 unsigned Reloc) {
292 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
293
294 // X86 never needs stubs because instruction selection will always pick
295 // an instruction sequence that is large enough to hold any address
296 // to a symbol.
297 // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
298 bool NeedStub = false;
299 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
300 Reloc, ES, RelocCST,
301 0, NeedStub));
302 if (Reloc == X86::reloc_absolute_dword)
303 MCE.emitDWordLE(0);
304 else
305 MCE.emitWordLE(0);
306 }
307
308 /// emitConstPoolAddress - Arrange for the address of an constant pool
309 /// to be emitted to the current location in the function, and allow it to be PC
310 /// relative.
311 template<class CodeEmitter>
312 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
313 intptr_t Disp /* = 0 */,
314 intptr_t PCAdj /* = 0 */) {
315 intptr_t RelocCST = 0;
316 if (Reloc == X86::reloc_picrel_word)
317 RelocCST = PICBaseOffset;
318 else if (Reloc == X86::reloc_pcrel_word)
319 RelocCST = PCAdj;
320 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
321 Reloc, CPI, RelocCST));
322 // The relocated value will be added to the displacement
323 if (Reloc == X86::reloc_absolute_dword)
324 MCE.emitDWordLE(Disp);
325 else
326 MCE.emitWordLE((int32_t)Disp);
327 }
328
329 /// emitJumpTableAddress - Arrange for the address of a jump table to
330 /// be emitted to the current location in the function, and allow it to be PC
331 /// relative.
332 template<class CodeEmitter>
333 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
334 intptr_t PCAdj /* = 0 */) {
335 intptr_t RelocCST = 0;
336 if (Reloc == X86::reloc_picrel_word)
337 RelocCST = PICBaseOffset;
338 else if (Reloc == X86::reloc_pcrel_word)
339 RelocCST = PCAdj;
340 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
341 Reloc, JTI, RelocCST));
342 // The relocated value will be added to the displacement
343 if (Reloc == X86::reloc_absolute_dword)
344 MCE.emitDWordLE(0);
345 else
346 MCE.emitWordLE(0);
347 }
348
349 template<class CodeEmitter>
350 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
351 return X86RegisterInfo::getX86RegNum(RegNo);
352 }
353
354 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
355 unsigned RM) {
356 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
357 return RM | (RegOpcode << 3) | (Mod << 6);
358 }
359
360 template<class CodeEmitter>
361 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
362 unsigned RegOpcodeFld){
363 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
364 }
365
366 template<class CodeEmitter>
367 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
368 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
369 }
370
371 template<class CodeEmitter>
372 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
373 unsigned Index,
374 unsigned Base) {
375 // SIB byte is in the same format as the ModRMByte...
376 MCE.emitByte(ModRMByte(SS, Index, Base));
377 }
378
379 template<class CodeEmitter>
380 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
381 // Output the constant in little endian byte order...
382 for (unsigned i = 0; i != Size; ++i) {
383 MCE.emitByte(Val & 255);
384 Val >>= 8;
385 }
386 }
387
388 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
389 /// sign-extended field.
390 static bool isDisp8(int Value) {
391 return Value == (signed char)Value;
392 }
393
394 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
395 const TargetMachine &TM) {
396 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
397 // mechanism as 32-bit mode.
398 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
399 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
400 return false;
401
402 // Return true if this is a reference to a stub containing the address of the
403 // global, not the global itself.
404 return isGlobalStubReference(GVOp.getTargetFlags());
405 }
406
407 template<class CodeEmitter>
408 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
409 int DispVal,
410 intptr_t Adj /* = 0 */,
411 bool IsPCRel /* = true */) {
412 // If this is a simple integer displacement that doesn't require a relocation,
413 // emit it now.
414 if (!RelocOp) {
415 emitConstant(DispVal, 4);
416 return;
417 }
418
419 // Otherwise, this is something that requires a relocation. Emit it as such
420 // now.
421 unsigned RelocType = Is64BitMode ?
422 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
423 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
424 if (RelocOp->isGlobal()) {
425 // In 64-bit static small code model, we could potentially emit absolute.
426 // But it's probably not beneficial. If the MCE supports using RIP directly
427 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
428 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
429 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
430 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
431 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
432 Adj, Indirect);
433 } else if (RelocOp->isSymbol()) {
434 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
435 } else if (RelocOp->isCPI()) {
436 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
437 RelocOp->getOffset(), Adj);
438 } else {
439 assert(RelocOp->isJTI() && "Unexpected machine operand!");
440 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
441 }
442 }
443
444 template<class CodeEmitter>
445 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
446 unsigned Op,unsigned RegOpcodeField,
447 intptr_t PCAdj) {
448 const MachineOperand &Op3 = MI.getOperand(Op+3);
449 int DispVal = 0;
450 const MachineOperand *DispForReloc = 0;
451
452 // Figure out what sort of displacement we have to handle here.
453 if (Op3.isGlobal()) {
454 DispForReloc = &Op3;
455 } else if (Op3.isSymbol()) {
456 DispForReloc = &Op3;
457 } else if (Op3.isCPI()) {
458 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
459 DispForReloc = &Op3;
460 } else {
461 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
462 DispVal += Op3.getOffset();
463 }
464 } else if (Op3.isJTI()) {
465 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
466 DispForReloc = &Op3;
467 } else {
468 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
469 }
470 } else {
471 DispVal = Op3.getImm();
472 }
473
474 const MachineOperand &Base = MI.getOperand(Op);
475 const MachineOperand &Scale = MI.getOperand(Op+1);
476 const MachineOperand &IndexReg = MI.getOperand(Op+2);
477
478 unsigned BaseReg = Base.getReg();
479
480 // Handle %rip relative addressing.
481 if (BaseReg == X86::RIP ||
482 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
483 assert(IndexReg.getReg() == 0 && Is64BitMode &&
484 "Invalid rip-relative address");
485 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
486 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
487 return;
488 }
489
490 // Indicate that the displacement will use an pcrel or absolute reference
491 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
492 // while others, unless explicit asked to use RIP, use absolute references.
493 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
494
495 // Is a SIB byte needed?
496 // If no BaseReg, issue a RIP relative instruction only if the MCE can
497 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
498 // 2-7) and absolute references.
499 unsigned BaseRegNo = -1U;
500 if (BaseReg != 0 && BaseReg != X86::RIP)
501 BaseRegNo = getX86RegNum(BaseReg);
502
503 if (// The SIB byte must be used if there is an index register.
504 IndexReg.getReg() == 0 &&
505 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
506 // encode to an R/M value of 4, which indicates that a SIB byte is
507 // present.
508 BaseRegNo != N86::ESP &&
509 // If there is no base register and we're in 64-bit mode, we need a SIB
510 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
511 (!Is64BitMode || BaseReg != 0)) {
512 if (BaseReg == 0 || // [disp32] in X86-32 mode
513 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
514 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
515 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
516 return;
517 }
518
519 // If the base is not EBP/ESP and there is no displacement, use simple
520 // indirect register encoding, this handles addresses like [EAX]. The
521 // encoding for [EBP] with no displacement means [disp32] so we handle it
522 // by emitting a displacement of 0 below.
523 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
524 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
525 return;
526 }
527
528 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
529 if (!DispForReloc && isDisp8(DispVal)) {
530 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
531 emitConstant(DispVal, 1);
532 return;
533 }
534
535 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
536 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
537 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
538 return;
539 }
540
541 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first.
542 assert(IndexReg.getReg() != X86::ESP &&
543 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
544
545 bool ForceDisp32 = false;
546 bool ForceDisp8 = false;
547 if (BaseReg == 0) {
548 // If there is no base register, we emit the special case SIB byte with
549 // MOD=0, BASE=4, to JUST get the index, scale, and displacement.
550 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
551 ForceDisp32 = true;
552 } else if (DispForReloc) {
553 // Emit the normal disp32 encoding.
554 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
555 ForceDisp32 = true;
556 } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
557 // Emit no displacement ModR/M byte
558 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
559 } else if (isDisp8(DispVal)) {
560 // Emit the disp8 encoding...
561 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
562 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
563 } else {
564 // Emit the normal disp32 encoding...
565 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
566 }
567
568 // Calculate what the SS field value should be...
569 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
570 unsigned SS = SSTable[Scale.getImm()];
571
572 if (BaseReg == 0) {
573 // Handle the SIB byte for the case where there is no base, see Intel
574 // Manual 2A, table 2-7. The displacement has already been output.
575 unsigned IndexRegNo;
576 if (IndexReg.getReg())
577 IndexRegNo = getX86RegNum(IndexReg.getReg());
578 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
579 IndexRegNo = 4;
580 emitSIBByte(SS, IndexRegNo, 5);
581 } else {
582 unsigned BaseRegNo = getX86RegNum(BaseReg);
583 unsigned IndexRegNo;
584 if (IndexReg.getReg())
585 IndexRegNo = getX86RegNum(IndexReg.getReg());
586 else
587 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
588 emitSIBByte(SS, IndexRegNo, BaseRegNo);
589 }
590
591 // Do we need to output a displacement?
592 if (ForceDisp8) {
593 emitConstant(DispVal, 1);
594 } else if (DispVal != 0 || ForceDisp32) {
595 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
596 }
597 }
598
599 template<class CodeEmitter>
600 void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
601 const TargetInstrDesc *Desc) {
602 DEBUG(dbgs() << MI);
603
604 // If this is a pseudo instruction, lower it.
605 switch (Desc->getOpcode()) {
606 case X86::ADD16rr_DB: Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break;
607 case X86::ADD32rr_DB: Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break;
608 case X86::ADD64rr_DB: Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break;
609 case X86::ADD16ri_DB: Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break;
610 case X86::ADD32ri_DB: Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break;
611 case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break;
612 case X86::ADD16ri8_DB: Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break;
613 case X86::ADD32ri8_DB: Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break;
614 case X86::ADD64ri8_DB: Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break;
615 }
616
617
618 MCE.processDebugLoc(MI.getDebugLoc(), true);
619
620 unsigned Opcode = Desc->Opcode;
621
622 // Emit the lock opcode prefix as needed.
623 if (Desc->TSFlags & X86II::LOCK)
624 MCE.emitByte(0xF0);
625
626 // Emit segment override opcode prefix as needed.
627 switch (Desc->TSFlags & X86II::SegOvrMask) {
628 case X86II::FS:
629 MCE.emitByte(0x64);
630 break;
631 case X86II::GS:
632 MCE.emitByte(0x65);
633 break;
634 default: llvm_unreachable("Invalid segment!");
635 case 0: break; // No segment override!
636 }
637
638 // Emit the repeat opcode prefix as needed.
639 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
640 MCE.emitByte(0xF3);
641
642 // Emit the operand size opcode prefix as needed.
643 if (Desc->TSFlags & X86II::OpSize)
644 MCE.emitByte(0x66);
645
646 // Emit the address size opcode prefix as needed.
647 if (Desc->TSFlags & X86II::AdSize)
648 MCE.emitByte(0x67);
649
650 bool Need0FPrefix = false;
651 switch (Desc->TSFlags & X86II::Op0Mask) {
652 case X86II::TB: // Two-byte opcode prefix
653 case X86II::T8: // 0F 38
654 case X86II::TA: // 0F 3A
655 case X86II::A6: // 0F A6
656 case X86II::A7: // 0F A7
657 Need0FPrefix = true;
658 break;
659 case X86II::TF: // F2 0F 38
660 MCE.emitByte(0xF2);
661 Need0FPrefix = true;
662 break;
663 case X86II::REP: break; // already handled.
664 case X86II::XS: // F3 0F
665 MCE.emitByte(0xF3);
666 Need0FPrefix = true;
667 break;
668 case X86II::XD: // F2 0F
669 MCE.emitByte(0xF2);
670 Need0FPrefix = true;
671 break;
672 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
673 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
674 MCE.emitByte(0xD8+
675 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
676 >> X86II::Op0Shift));
677 break; // Two-byte opcode prefix
678 default: llvm_unreachable("Invalid prefix!");
679 case 0: break; // No prefix!
680 }
681
682 // Handle REX prefix.
683 if (Is64BitMode) {
684 if (unsigned REX = determineREX(MI))
685 MCE.emitByte(0x40 | REX);
686 }
687
688 // 0x0F escape code must be emitted just before the opcode.
689 if (Need0FPrefix)
690 MCE.emitByte(0x0F);
691
692 switch (Desc->TSFlags & X86II::Op0Mask) {
693 case X86II::TF: // F2 0F 38
694 case X86II::T8: // 0F 38
695 MCE.emitByte(0x38);
696 break;
697 case X86II::TA: // 0F 3A
698 MCE.emitByte(0x3A);
699 break;
700 case X86II::A6: // 0F A6
701 MCE.emitByte(0xA6);
702 break;
703 case X86II::A7: // 0F A7
704 MCE.emitByte(0xA7);
705 break;
706 }
707
708 // If this is a two-address instruction, skip one of the register operands.
709 unsigned NumOps = Desc->getNumOperands();
710 unsigned CurOp = 0;
711 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
712 ++CurOp;
713 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
714 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
715 --NumOps;
716
717 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
718 switch (Desc->TSFlags & X86II::FormMask) {
719 default:
720 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
721 case X86II::Pseudo:
722 // Remember the current PC offset, this is the PIC relocation
723 // base address.
724 switch (Opcode) {
725 default:
726 llvm_unreachable("pseudo instructions should be removed before code"
727 " emission");
728 break;
729 // Do nothing for Int_MemBarrier - it's just a comment. Add a debug
730 // to make it slightly easier to see.
731 case X86::Int_MemBarrier:
732 DEBUG(dbgs() << "#MEMBARRIER\n");
733 break;
734
735 case TargetOpcode::INLINEASM:
736 // We allow inline assembler nodes with empty bodies - they can
737 // implicitly define registers, which is ok for JIT.
738 if (MI.getOperand(0).getSymbolName()[0])
739 report_fatal_error("JIT does not support inline asm!");
740 break;
741 case TargetOpcode::PROLOG_LABEL:
742 case TargetOpcode::GC_LABEL:
743 case TargetOpcode::EH_LABEL:
744 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
745 break;
746
747 case TargetOpcode::IMPLICIT_DEF:
748 case TargetOpcode::KILL:
749 break;
750 case X86::MOVPC32r: {
751 // This emits the "call" portion of this pseudo instruction.
752 MCE.emitByte(BaseOpcode);
753 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
754 // Remember PIC base.
755 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
756 X86JITInfo *JTI = TM.getJITInfo();
757 JTI->setPICBase(MCE.getCurrentPCValue());
758 break;
759 }
760 }
761 CurOp = NumOps;
762 break;
763 case X86II::RawFrm: {
764 MCE.emitByte(BaseOpcode);
765
766 if (CurOp == NumOps)
767 break;
768
769 const MachineOperand &MO = MI.getOperand(CurOp++);
770
771 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
772 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
773 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
774 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
775 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
776
777 if (MO.isMBB()) {
778 emitPCRelativeBlockAddress(MO.getMBB());
779 break;
780 }
781
782 if (MO.isGlobal()) {
783 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
784 MO.getOffset(), 0);
785 break;
786 }
787
788 if (MO.isSymbol()) {
789 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
790 break;
791 }
792
793 // FIXME: Only used by hackish MCCodeEmitter, remove when dead.
794 if (MO.isJTI()) {
795 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word);
796 break;
797 }
798
799 assert(MO.isImm() && "Unknown RawFrm operand!");
800 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32 ||
801 Opcode == X86::WINCALL64pcrel32) {
802 // Fix up immediate operand for pc relative calls.
803 intptr_t Imm = (intptr_t)MO.getImm();
804 Imm = Imm - MCE.getCurrentPCValue() - 4;
805 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
806 } else
807 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
808 break;
809 }
810
811 case X86II::AddRegFrm: {
812 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
813
814 if (CurOp == NumOps)
815 break;
816
817 const MachineOperand &MO1 = MI.getOperand(CurOp++);
818 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
819 if (MO1.isImm()) {
820 emitConstant(MO1.getImm(), Size);
821 break;
822 }
823
824 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
825 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
826 if (Opcode == X86::MOV64ri64i32)
827 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
828 // This should not occur on Darwin for relocatable objects.
829 if (Opcode == X86::MOV64ri)
830 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
831 if (MO1.isGlobal()) {
832 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
833 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
834 Indirect);
835 } else if (MO1.isSymbol())
836 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
837 else if (MO1.isCPI())
838 emitConstPoolAddress(MO1.getIndex(), rt);
839 else if (MO1.isJTI())
840 emitJumpTableAddress(MO1.getIndex(), rt);
841 break;
842 }
843
844 case X86II::MRMDestReg: {
845 MCE.emitByte(BaseOpcode);
846 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
847 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
848 CurOp += 2;
849 if (CurOp != NumOps)
850 emitConstant(MI.getOperand(CurOp++).getImm(),
851 X86II::getSizeOfImm(Desc->TSFlags));
852 break;
853 }
854 case X86II::MRMDestMem: {
855 MCE.emitByte(BaseOpcode);
856 emitMemModRMByte(MI, CurOp,
857 getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
858 .getReg()));
859 CurOp += X86::AddrNumOperands + 1;
860 if (CurOp != NumOps)
861 emitConstant(MI.getOperand(CurOp++).getImm(),
862 X86II::getSizeOfImm(Desc->TSFlags));
863 break;
864 }
865
866 case X86II::MRMSrcReg:
867 MCE.emitByte(BaseOpcode);
868 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
869 getX86RegNum(MI.getOperand(CurOp).getReg()));
870 CurOp += 2;
871 if (CurOp != NumOps)
872 emitConstant(MI.getOperand(CurOp++).getImm(),
873 X86II::getSizeOfImm(Desc->TSFlags));
874 break;
875
876 case X86II::MRMSrcMem: {
877 int AddrOperands = X86::AddrNumOperands;
878
879 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
880 X86II::getSizeOfImm(Desc->TSFlags) : 0;
881
882 MCE.emitByte(BaseOpcode);
883 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
884 PCAdj);
885 CurOp += AddrOperands + 1;
886 if (CurOp != NumOps)
887 emitConstant(MI.getOperand(CurOp++).getImm(),
888 X86II::getSizeOfImm(Desc->TSFlags));
889 break;
890 }
891
892 case X86II::MRM0r: case X86II::MRM1r:
893 case X86II::MRM2r: case X86II::MRM3r:
894 case X86II::MRM4r: case X86II::MRM5r:
895 case X86II::MRM6r: case X86II::MRM7r: {
896 MCE.emitByte(BaseOpcode);
897 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
898 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
899
900 if (CurOp == NumOps)
901 break;
902
903 const MachineOperand &MO1 = MI.getOperand(CurOp++);
904 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
905 if (MO1.isImm()) {
906 emitConstant(MO1.getImm(), Size);
907 break;
908 }
909
910 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
911 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
912 if (Opcode == X86::MOV64ri32)
913 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
914 if (MO1.isGlobal()) {
915 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
916 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
917 Indirect);
918 } else if (MO1.isSymbol())
919 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
920 else if (MO1.isCPI())
921 emitConstPoolAddress(MO1.getIndex(), rt);
922 else if (MO1.isJTI())
923 emitJumpTableAddress(MO1.getIndex(), rt);
924 break;
925 }
926
927 case X86II::MRM0m: case X86II::MRM1m:
928 case X86II::MRM2m: case X86II::MRM3m:
929 case X86II::MRM4m: case X86II::MRM5m:
930 case X86II::MRM6m: case X86II::MRM7m: {
931 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
932 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
933 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
934
935 MCE.emitByte(BaseOpcode);
936 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
937 PCAdj);
938 CurOp += X86::AddrNumOperands;
939
940 if (CurOp == NumOps)
941 break;
942
943 const MachineOperand &MO = MI.getOperand(CurOp++);
944 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
945 if (MO.isImm()) {
946 emitConstant(MO.getImm(), Size);
947 break;
948 }
949
950 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
951 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
952 if (Opcode == X86::MOV64mi32)
953 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
954 if (MO.isGlobal()) {
955 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
956 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
957 Indirect);
958 } else if (MO.isSymbol())
959 emitExternalSymbolAddress(MO.getSymbolName(), rt);
960 else if (MO.isCPI())
961 emitConstPoolAddress(MO.getIndex(), rt);
962 else if (MO.isJTI())
963 emitJumpTableAddress(MO.getIndex(), rt);
964 break;
965 }
966
967 case X86II::MRMInitReg:
968 MCE.emitByte(BaseOpcode);
969 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
970 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
971 getX86RegNum(MI.getOperand(CurOp).getReg()));
972 ++CurOp;
973 break;
974
975 case X86II::MRM_C1:
976 MCE.emitByte(BaseOpcode);
977 MCE.emitByte(0xC1);
978 break;
979 case X86II::MRM_C8:
980 MCE.emitByte(BaseOpcode);
981 MCE.emitByte(0xC8);
982 break;
983 case X86II::MRM_C9:
984 MCE.emitByte(BaseOpcode);
985 MCE.emitByte(0xC9);
986 break;
987 case X86II::MRM_E8:
988 MCE.emitByte(BaseOpcode);
989 MCE.emitByte(0xE8);
990 break;
991 case X86II::MRM_F0:
992 MCE.emitByte(BaseOpcode);
993 MCE.emitByte(0xF0);
994 break;
995 }
996
997 if (!Desc->isVariadic() && CurOp != NumOps) {
998 #ifndef NDEBUG
999 dbgs() << "Cannot encode all operands of: " << MI << "\n";
1000 #endif
1001 llvm_unreachable(0);
1002 }
1003
1004 MCE.processDebugLoc(MI.getDebugLoc(), false);
1005 }
STM8 backend for LLVM