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1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
12 // registers.
13 //
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
18 //
19 let Namespace = "X86" in {
21 // Subregister indices.
22 def sub_8bit : SubRegIndex;
23 def sub_8bit_hi : SubRegIndex;
24 def sub_16bit : SubRegIndex;
25 def sub_32bit : SubRegIndex;
27 def sub_ss : SubRegIndex;
28 def sub_sd : SubRegIndex;
29 def sub_xmm : SubRegIndex;
32 // In the register alias definitions below, we define which registers alias
33 // which others. We only specify which registers the small registers alias,
34 // because the register file generator is smart enough to figure out that
35 // AL aliases AX if we tell it that AX aliased AL (for example).
37 // Dwarf numbering is different for 32-bit and 64-bit, and there are
38 // variations by target as well. Currently the first entry is for X86-64,
39 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
40 // and debug information on X86-32/Darwin)
42 // 8-bit registers
43 // Low registers
44 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
45 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
46 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
47 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
49 // X86-64 only
50 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
51 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
52 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
53 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
54 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
55 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
56 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
57 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
58 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
59 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
60 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
61 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
63 // High registers. On x86-64, these cannot be used in any instruction
64 // with a REX prefix.
65 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
66 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
67 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
68 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
70 // 16-bit registers
71 let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
72 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
73 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
74 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
75 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
76 }
77 let SubRegIndices = [sub_8bit] in {
78 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
79 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
80 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
81 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
82 }
83 def IP : Register<"ip">, DwarfRegNum<[16]>;
85 // X86-64 only
86 let SubRegIndices = [sub_8bit] in {
87 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
88 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
89 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
90 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
91 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
92 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
93 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
94 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
95 }
96 // 32-bit registers
97 let SubRegIndices = [sub_16bit] in {
98 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
99 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
100 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
101 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
102 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
103 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
104 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
105 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
106 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
108 // X86-64 only
109 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
110 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
111 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
112 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
113 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
114 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
115 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
116 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
117 }
119 // 64-bit registers, X86-64 only
120 let SubRegIndices = [sub_32bit] in {
121 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
122 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
123 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
124 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
125 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
126 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
127 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
128 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
130 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
131 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
132 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
133 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
134 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
135 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
136 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
137 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
138 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
139 }
141 // MMX Registers. These are actually aliased to ST0 .. ST7
142 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
143 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
144 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
145 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
146 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
147 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
148 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
149 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
151 // Pseudo Floating Point registers
152 def FP0 : Register<"fp0">;
153 def FP1 : Register<"fp1">;
154 def FP2 : Register<"fp2">;
155 def FP3 : Register<"fp3">;
156 def FP4 : Register<"fp4">;
157 def FP5 : Register<"fp5">;
158 def FP6 : Register<"fp6">;
160 // XMM Registers, used by the various SSE instruction set extensions.
161 // The sub_ss and sub_sd subregs are the same registers with another regclass.
162 let CompositeIndices = [(sub_ss), (sub_sd)] in {
163 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
164 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
165 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
166 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
167 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
168 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
169 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
170 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
172 // X86-64 only
173 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
174 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
175 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
176 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
177 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
178 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
179 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
180 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
181 }
183 // YMM Registers, used by AVX instructions
184 let SubRegIndices = [sub_xmm] in {
185 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
186 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
187 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
188 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
189 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
190 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
191 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
192 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
193 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
194 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
195 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
196 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
197 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
198 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
199 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
200 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
201 }
203 // Floating point stack registers
204 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
205 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
206 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
207 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
208 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
209 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
210 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
211 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
213 // Status flags register
214 def EFLAGS : Register<"flags">;
216 // Segment registers
217 def CS : Register<"cs">;
218 def DS : Register<"ds">;
219 def SS : Register<"ss">;
220 def ES : Register<"es">;
221 def FS : Register<"fs">;
222 def GS : Register<"gs">;
224 // Debug registers
225 def DR0 : Register<"dr0">;
226 def DR1 : Register<"dr1">;
227 def DR2 : Register<"dr2">;
228 def DR3 : Register<"dr3">;
229 def DR4 : Register<"dr4">;
230 def DR5 : Register<"dr5">;
231 def DR6 : Register<"dr6">;
232 def DR7 : Register<"dr7">;
234 // Control registers
235 def CR0 : Register<"cr0">;
236 def CR1 : Register<"cr1">;
237 def CR2 : Register<"cr2">;
238 def CR3 : Register<"cr3">;
239 def CR4 : Register<"cr4">;
240 def CR5 : Register<"cr5">;
241 def CR6 : Register<"cr6">;
242 def CR7 : Register<"cr7">;
243 def CR8 : Register<"cr8">;
244 def CR9 : Register<"cr9">;
245 def CR10 : Register<"cr10">;
246 def CR11 : Register<"cr11">;
247 def CR12 : Register<"cr12">;
248 def CR13 : Register<"cr13">;
249 def CR14 : Register<"cr14">;
250 def CR15 : Register<"cr15">;
252 // Pseudo index registers
253 def EIZ : Register<"eiz">;
254 def RIZ : Register<"riz">;
255 }
258 //===----------------------------------------------------------------------===//
259 // Register Class Definitions... now that we have all of the pieces, define the
260 // top-level register classes. The order specified in the register list is
261 // implicitly defined to be the register allocation order.
262 //
264 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
265 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
266 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
267 // R8B, ... R15B.
268 // Allocate R12 and R13 last, as these require an extra byte when
269 // encoded in x86_64 instructions.
270 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
271 // 64-bit mode. The main complication is that they cannot be encoded in an
272 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
273 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
274 // cannot be encoded.
275 def GR8 : RegisterClass<"X86", [i8], 8,
276 [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
277 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
278 let MethodProtos = [{
279 iterator allocation_order_begin(const MachineFunction &MF) const;
280 iterator allocation_order_end(const MachineFunction &MF) const;
281 }];
282 let MethodBodies = [{
283 static const unsigned X86_GR8_AO_64[] = {
284 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
285 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
286 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
287 };
289 GR8Class::iterator
290 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
291 const TargetMachine &TM = MF.getTarget();
292 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
293 if (Subtarget.is64Bit())
294 return X86_GR8_AO_64;
295 else
296 return begin();
297 }
299 GR8Class::iterator
300 GR8Class::allocation_order_end(const MachineFunction &MF) const {
301 const TargetMachine &TM = MF.getTarget();
302 const TargetFrameLowering *TFI = TM.getFrameLowering();
303 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
304 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
305 // Does the function dedicate RBP / EBP to being a frame ptr?
306 if (!Subtarget.is64Bit())
307 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
308 return begin() + 8;
309 else if (TFI->hasFP(MF) || MFI->getReserveFP())
310 // If so, don't allocate SPL or BPL.
311 return array_endof(X86_GR8_AO_64) - 1;
312 else
313 // If not, just don't allocate SPL.
314 return array_endof(X86_GR8_AO_64);
315 }
316 }];
317 }
319 def GR16 : RegisterClass<"X86", [i16], 16,
320 [AX, CX, DX, SI, DI, BX, BP, SP,
321 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
322 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
323 let MethodProtos = [{
324 iterator allocation_order_begin(const MachineFunction &MF) const;
325 iterator allocation_order_end(const MachineFunction &MF) const;
326 }];
327 let MethodBodies = [{
328 static const unsigned X86_GR16_AO_64[] = {
329 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
330 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
331 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
332 };
334 GR16Class::iterator
335 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
336 const TargetMachine &TM = MF.getTarget();
337 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
338 if (Subtarget.is64Bit())
339 return X86_GR16_AO_64;
340 else
341 return begin();
342 }
344 GR16Class::iterator
345 GR16Class::allocation_order_end(const MachineFunction &MF) const {
346 const TargetMachine &TM = MF.getTarget();
347 const TargetFrameLowering *TFI = TM.getFrameLowering();
348 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
349 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
350 if (Subtarget.is64Bit()) {
351 // Does the function dedicate RBP to being a frame ptr?
352 if (TFI->hasFP(MF) || MFI->getReserveFP())
353 // If so, don't allocate SP or BP.
354 return array_endof(X86_GR16_AO_64) - 1;
355 else
356 // If not, just don't allocate SP.
357 return array_endof(X86_GR16_AO_64);
358 } else {
359 // Does the function dedicate EBP to being a frame ptr?
360 if (TFI->hasFP(MF) || MFI->getReserveFP())
361 // If so, don't allocate SP or BP.
362 return begin() + 6;
363 else
364 // If not, just don't allocate SP.
365 return begin() + 7;
366 }
367 }
368 }];
369 }
371 def GR32 : RegisterClass<"X86", [i32], 32,
372 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
373 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
374 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
375 let MethodProtos = [{
376 iterator allocation_order_begin(const MachineFunction &MF) const;
377 iterator allocation_order_end(const MachineFunction &MF) const;
378 }];
379 let MethodBodies = [{
380 static const unsigned X86_GR32_AO_64[] = {
381 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
382 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
383 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
384 };
386 GR32Class::iterator
387 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
388 const TargetMachine &TM = MF.getTarget();
389 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
390 if (Subtarget.is64Bit())
391 return X86_GR32_AO_64;
392 else
393 return begin();
394 }
396 GR32Class::iterator
397 GR32Class::allocation_order_end(const MachineFunction &MF) const {
398 const TargetMachine &TM = MF.getTarget();
399 const TargetFrameLowering *TFI = TM.getFrameLowering();
400 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
401 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
402 if (Subtarget.is64Bit()) {
403 // Does the function dedicate RBP to being a frame ptr?
404 if (TFI->hasFP(MF) || MFI->getReserveFP())
405 // If so, don't allocate ESP or EBP.
406 return array_endof(X86_GR32_AO_64) - 1;
407 else
408 // If not, just don't allocate ESP.
409 return array_endof(X86_GR32_AO_64);
410 } else {
411 // Does the function dedicate EBP to being a frame ptr?
412 if (TFI->hasFP(MF) || MFI->getReserveFP())
413 // If so, don't allocate ESP or EBP.
414 return begin() + 6;
415 else
416 // If not, just don't allocate ESP.
417 return begin() + 7;
418 }
419 }
420 }];
421 }
423 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
424 // RIP isn't really a register and it can't be used anywhere except in an
425 // address, but it doesn't cause trouble.
426 def GR64 : RegisterClass<"X86", [i64], 64,
427 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
428 RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
429 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
430 (GR16 sub_16bit),
431 (GR32 sub_32bit)];
432 let MethodProtos = [{
433 iterator allocation_order_end(const MachineFunction &MF) const;
434 }];
435 let MethodBodies = [{
436 GR64Class::iterator
437 GR64Class::allocation_order_end(const MachineFunction &MF) const {
438 const TargetMachine &TM = MF.getTarget();
439 const TargetFrameLowering *TFI = TM.getFrameLowering();
440 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
441 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
442 if (!Subtarget.is64Bit())
443 return begin(); // None of these are allocatable in 32-bit.
444 // Does the function dedicate RBP to being a frame ptr?
445 if (TFI->hasFP(MF) || MFI->getReserveFP())
446 return end()-3; // If so, don't allocate RIP, RSP or RBP
447 else
448 return end()-2; // If not, just don't allocate RIP or RSP
449 }
450 }];
451 }
453 // Segment registers for use by MOV instructions (and others) that have a
454 // segment register as one operand. Always contain a 16-bit segment
455 // descriptor.
456 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]>;
458 // Debug registers.
459 def DEBUG_REG : RegisterClass<"X86", [i32], 32,
460 [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]>;
462 // Control registers.
463 def CONTROL_REG : RegisterClass<"X86", [i64], 64,
464 [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8,
465 CR9, CR10, CR11, CR12, CR13, CR14, CR15]>;
467 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
468 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
469 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
470 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
471 // and GR64_ABCD are classes for registers that support 8-bit h-register
472 // operations.
473 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]>;
474 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]>;
475 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
476 let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
477 }
478 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
479 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
480 (GR8_ABCD_H sub_8bit_hi),
481 (GR16_ABCD sub_16bit)];
482 }
483 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
484 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
485 (GR8_ABCD_H sub_8bit_hi),
486 (GR16_ABCD sub_16bit),
487 (GR32_ABCD sub_32bit)];
488 }
489 def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
490 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
491 }
492 def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
493 R8, R9, R11]> {
494 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
495 (GR16 sub_16bit),
496 (GR32_TC sub_32bit)];
497 }
499 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX,
500 R8, R9, R11]>;
502 // GR8_NOREX - GR8 registers which do not require a REX prefix.
503 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
504 [AL, CL, DL, AH, CH, DH, BL, BH]> {
505 let MethodProtos = [{
506 iterator allocation_order_begin(const MachineFunction &MF) const;
507 iterator allocation_order_end(const MachineFunction &MF) const;
508 }];
509 let MethodBodies = [{
510 // In 64-bit mode, it's not safe to blindly allocate H registers.
511 static const unsigned X86_GR8_NOREX_AO_64[] = {
512 X86::AL, X86::CL, X86::DL, X86::BL
513 };
515 GR8_NOREXClass::iterator
516 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
517 const TargetMachine &TM = MF.getTarget();
518 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
519 if (Subtarget.is64Bit())
520 return X86_GR8_NOREX_AO_64;
521 else
522 return begin();
523 }
525 GR8_NOREXClass::iterator
526 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
527 const TargetMachine &TM = MF.getTarget();
528 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
529 if (Subtarget.is64Bit())
530 return array_endof(X86_GR8_NOREX_AO_64);
531 else
532 return end();
533 }
534 }];
535 }
536 // GR16_NOREX - GR16 registers which do not require a REX prefix.
537 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
538 [AX, CX, DX, SI, DI, BX, BP, SP]> {
539 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
540 let MethodProtos = [{
541 iterator allocation_order_end(const MachineFunction &MF) const;
542 }];
543 let MethodBodies = [{
544 GR16_NOREXClass::iterator
545 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
546 const TargetMachine &TM = MF.getTarget();
547 const TargetFrameLowering *TFI = TM.getFrameLowering();
548 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
549 // Does the function dedicate RBP / EBP to being a frame ptr?
550 if (TFI->hasFP(MF) || MFI->getReserveFP())
551 // If so, don't allocate SP or BP.
552 return end() - 2;
553 else
554 // If not, just don't allocate SP.
555 return end() - 1;
556 }
557 }];
558 }
559 // GR32_NOREX - GR32 registers which do not require a REX prefix.
560 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
561 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
562 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
563 (GR16_NOREX sub_16bit)];
564 let MethodProtos = [{
565 iterator allocation_order_end(const MachineFunction &MF) const;
566 }];
567 let MethodBodies = [{
568 GR32_NOREXClass::iterator
569 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
570 const TargetMachine &TM = MF.getTarget();
571 const TargetFrameLowering *TFI = TM.getFrameLowering();
572 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
573 // Does the function dedicate RBP / EBP to being a frame ptr?
574 if (TFI->hasFP(MF) || MFI->getReserveFP())
575 // If so, don't allocate ESP or EBP.
576 return end() - 2;
577 else
578 // If not, just don't allocate ESP.
579 return end() - 1;
580 }
581 }];
582 }
583 // GR64_NOREX - GR64 registers which do not require a REX prefix.
584 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
585 [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
586 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
587 (GR16_NOREX sub_16bit),
588 (GR32_NOREX sub_32bit)];
589 let MethodProtos = [{
590 iterator allocation_order_end(const MachineFunction &MF) const;
591 }];
592 let MethodBodies = [{
593 GR64_NOREXClass::iterator
594 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
595 const TargetMachine &TM = MF.getTarget();
596 const TargetFrameLowering *TFI = TM.getFrameLowering();
597 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
598 // Does the function dedicate RBP to being a frame ptr?
599 if (TFI->hasFP(MF) || MFI->getReserveFP())
600 // If so, don't allocate RIP, RSP or RBP.
601 return end() - 3;
602 else
603 // If not, just don't allocate RIP or RSP.
604 return end() - 2;
605 }
606 }];
607 }
609 // GR32_NOSP - GR32 registers except ESP.
610 def GR32_NOSP : RegisterClass<"X86", [i32], 32,
611 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
612 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
613 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
614 let MethodProtos = [{
615 iterator allocation_order_begin(const MachineFunction &MF) const;
616 iterator allocation_order_end(const MachineFunction &MF) const;
617 }];
618 let MethodBodies = [{
619 static const unsigned X86_GR32_NOSP_AO_64[] = {
620 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
621 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
622 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
623 };
625 GR32_NOSPClass::iterator
626 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
627 const TargetMachine &TM = MF.getTarget();
628 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
629 if (Subtarget.is64Bit())
630 return X86_GR32_NOSP_AO_64;
631 else
632 return begin();
633 }
635 GR32_NOSPClass::iterator
636 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
637 const TargetMachine &TM = MF.getTarget();
638 const TargetFrameLowering *TFI = TM.getFrameLowering();
639 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
640 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
641 if (Subtarget.is64Bit()) {
642 // Does the function dedicate RBP to being a frame ptr?
643 if (TFI->hasFP(MF) || MFI->getReserveFP())
644 // If so, don't allocate EBP.
645 return array_endof(X86_GR32_NOSP_AO_64) - 1;
646 else
647 // If not, any reg in this class is ok.
648 return array_endof(X86_GR32_NOSP_AO_64);
649 } else {
650 // Does the function dedicate EBP to being a frame ptr?
651 if (TFI->hasFP(MF) || MFI->getReserveFP())
652 // If so, don't allocate EBP.
653 return begin() + 6;
654 else
655 // If not, any reg in this class is ok.
656 return begin() + 7;
657 }
658 }
659 }];
660 }
662 // GR64_NOSP - GR64 registers except RSP (and RIP).
663 def GR64_NOSP : RegisterClass<"X86", [i64], 64,
664 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
665 RBX, R14, R15, R12, R13, RBP]> {
666 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
667 (GR16 sub_16bit),
668 (GR32_NOSP sub_32bit)];
669 let MethodProtos = [{
670 iterator allocation_order_end(const MachineFunction &MF) const;
671 }];
672 let MethodBodies = [{
673 GR64_NOSPClass::iterator
674 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
675 const TargetMachine &TM = MF.getTarget();
676 const TargetFrameLowering *TFI = TM.getFrameLowering();
677 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
678 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
679 if (!Subtarget.is64Bit())
680 return begin(); // None of these are allocatable in 32-bit.
681 // Does the function dedicate RBP to being a frame ptr?
682 if (TFI->hasFP(MF) || MFI->getReserveFP())
683 return end()-1; // If so, don't allocate RBP
684 else
685 return end(); // If not, any reg in this class is ok.
686 }
687 }];
688 }
690 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
691 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
692 [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
693 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
694 (GR16_NOREX sub_16bit),
695 (GR32_NOREX sub_32bit)];
696 let MethodProtos = [{
697 iterator allocation_order_end(const MachineFunction &MF) const;
698 }];
699 let MethodBodies = [{
700 GR64_NOREX_NOSPClass::iterator
701 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
702 {
703 const TargetMachine &TM = MF.getTarget();
704 const TargetFrameLowering *TFI = TM.getFrameLowering();
705 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
706 // Does the function dedicate RBP to being a frame ptr?
707 if (TFI->hasFP(MF) || MFI->getReserveFP())
708 // If so, don't allocate RBP.
709 return end() - 1;
710 else
711 // If not, any reg in this class is ok.
712 return end();
713 }
714 }];
715 }
717 // A class to support the 'A' assembler constraint: EAX then EDX.
718 def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
719 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
720 (GR8_ABCD_H sub_8bit_hi),
721 (GR16_ABCD sub_16bit)];
722 }
724 // Scalar SSE2 floating point registers.
725 def FR32 : RegisterClass<"X86", [f32], 32,
726 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
727 XMM8, XMM9, XMM10, XMM11,
728 XMM12, XMM13, XMM14, XMM15]> {
729 let MethodProtos = [{
730 iterator allocation_order_end(const MachineFunction &MF) const;
731 }];
732 let MethodBodies = [{
733 FR32Class::iterator
734 FR32Class::allocation_order_end(const MachineFunction &MF) const {
735 const TargetMachine &TM = MF.getTarget();
736 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
737 if (!Subtarget.is64Bit())
738 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
739 else
740 return end();
741 }
742 }];
743 }
745 def FR64 : RegisterClass<"X86", [f64], 64,
746 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
747 XMM8, XMM9, XMM10, XMM11,
748 XMM12, XMM13, XMM14, XMM15]> {
749 let MethodProtos = [{
750 iterator allocation_order_end(const MachineFunction &MF) const;
751 }];
752 let MethodBodies = [{
753 FR64Class::iterator
754 FR64Class::allocation_order_end(const MachineFunction &MF) const {
755 const TargetMachine &TM = MF.getTarget();
756 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
757 if (!Subtarget.is64Bit())
758 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
759 else
760 return end();
761 }
762 }];
763 }
766 // FIXME: This sets up the floating point register files as though they are f64
767 // values, though they really are f80 values. This will cause us to spill
768 // values as 64-bit quantities instead of 80-bit quantities, which is much much
769 // faster on common hardware. In reality, this should be controlled by a
770 // command line option or something.
772 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
773 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
774 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
776 // Floating point stack registers (these are not allocatable by the
777 // register allocator - the floating point stackifier is responsible
778 // for transforming FPn allocations to STn registers)
779 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
780 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
781 let MethodProtos = [{
782 iterator allocation_order_end(const MachineFunction &MF) const;
783 }];
784 let MethodBodies = [{
785 RSTClass::iterator
786 RSTClass::allocation_order_end(const MachineFunction &MF) const {
787 return begin();
788 }
789 }];
790 }
792 // Generic vector registers: VR64 and VR128.
793 def VR64: RegisterClass<"X86", [x86mmx], 64,
794 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
795 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
796 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
797 XMM8, XMM9, XMM10, XMM11,
798 XMM12, XMM13, XMM14, XMM15]> {
799 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
801 let MethodProtos = [{
802 iterator allocation_order_end(const MachineFunction &MF) const;
803 }];
804 let MethodBodies = [{
805 VR128Class::iterator
806 VR128Class::allocation_order_end(const MachineFunction &MF) const {
807 const TargetMachine &TM = MF.getTarget();
808 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
809 if (!Subtarget.is64Bit())
810 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
811 else
812 return end();
813 }
814 }];
815 }
817 def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
818 [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
819 YMM8, YMM9, YMM10, YMM11,
820 YMM12, YMM13, YMM14, YMM15]> {
821 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
823 let MethodProtos = [{
824 iterator allocation_order_end(const MachineFunction &MF) const;
825 }];
826 let MethodBodies = [{
827 VR256Class::iterator
828 VR256Class::allocation_order_end(const MachineFunction &MF) const {
829 const TargetMachine &TM = MF.getTarget();
830 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
831 if (!Subtarget.is64Bit())
832 return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
833 else
834 return end();
835 }
836 }];
837 }
839 // Status flags registers.
840 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
841 let CopyCost = -1; // Don't allow copying of status registers.
843 // EFLAGS is not allocatable.
844 let MethodProtos = [{
845 iterator allocation_order_end(const MachineFunction &MF) const;
846 }];
847 let MethodBodies = [{
848 CCRClass::iterator
849 CCRClass::allocation_order_end(const MachineFunction &MF) const {
850 return allocation_order_begin(MF);
851 }
852 }];
853 }