lib/Target/XCore/XCoreInstrInfo.h

   1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the XCore implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef XCOREINSTRUCTIONINFO_H
  15 #define XCOREINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "XCoreRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 class XCoreInstrInfo : public TargetInstrInfoImpl {
  23   const XCoreRegisterInfo RI;
  24 public:
  25   XCoreInstrInfo();
  26
  27   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  28   /// such, whenever a client has an instance of instruction info, it should
  29   /// always be able to get register info as well (through this method).
  30   ///
  31   virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
  32
  33   /// isLoadFromStackSlot - If the specified machine instruction is a direct
  34   /// load from a stack slot, return the virtual or physical register number of
  35   /// the destination along with the FrameIndex of the loaded stack slot.  If
  36   /// not, return 0.  This predicate must return 0 if the instruction has
  37   /// any side effects other than loading from the stack slot.
  38   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  39                                        int &FrameIndex) const;
  40
  41   /// isStoreToStackSlot - If the specified machine instruction is a direct
  42   /// store to a stack slot, return the virtual or physical register number of
  43   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  44   /// not, return 0.  This predicate must return 0 if the instruction has
  45   /// any side effects other than storing to the stack slot.
  46   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  47                                       int &FrameIndex) const;
  48
  49   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  50                              MachineBasicBlock *&FBB,
  51                              SmallVectorImpl<MachineOperand> &Cond,
  52                              bool AllowModify) const;
  53
  54   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  55                                 MachineBasicBlock *FBB,
  56                                 const SmallVectorImpl<MachineOperand> &Cond,
  57                                 DebugLoc DL) const;
  58
  59   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  60
  61   virtual void copyPhysReg(MachineBasicBlock &MBB,
  62                            MachineBasicBlock::iterator I, DebugLoc DL,
  63                            unsigned DestReg, unsigned SrcReg,
  64                            bool KillSrc) const;
  65
  66   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  67                                    MachineBasicBlock::iterator MI,
  68                                    unsigned SrcReg, bool isKill, int FrameIndex,
  69                                    const TargetRegisterClass *RC,
  70                                    const TargetRegisterInfo *TRI) const;
  71
  72   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  73                                     MachineBasicBlock::iterator MI,
  74                                     unsigned DestReg, int FrameIndex,
  75                                     const TargetRegisterClass *RC,
  76                                     const TargetRegisterInfo *TRI) const;
  77
  78
  79   virtual bool ReverseBranchCondition(
  80                             SmallVectorImpl<MachineOperand> &Cond) const;
  81 };
  82
  83 }
  84
  85 #endif