lib/Target/XCore/XCoreRegisterInfo.cpp

   1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the XCore implementation of the MRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "XCoreRegisterInfo.h"
  15 #include "XCoreMachineFunctionInfo.h"
  16 #include "XCore.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/CodeGen/MachineModuleInfo.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/RegisterScavenging.h"
  24 #include "llvm/Target/TargetFrameLowering.h"
  25 #include "llvm/Target/TargetMachine.h"
  26 #include "llvm/Target/TargetOptions.h"
  27 #include "llvm/Target/TargetInstrInfo.h"
  28 #include "llvm/Type.h"
  29 #include "llvm/Function.h"
  30 #include "llvm/ADT/BitVector.h"
  31 #include "llvm/ADT/STLExtras.h"
  32 #include "llvm/Support/Debug.h"
  33 #include "llvm/Support/ErrorHandling.h"
  34 #include "llvm/Support/raw_ostream.h"
  35
  36 using namespace llvm;
  37
  38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
  39   : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
  40     TII(tii) {
  41 }
  42
  43 // helper functions
  44 static inline bool isImmUs(unsigned val) {
  45   return val <= 11;
  46 }
  47
  48 static inline bool isImmU6(unsigned val) {
  49   return val < (1 << 6);
  50 }
  51
  52 static inline bool isImmU16(unsigned val) {
  53   return val < (1 << 16);
  54 }
  55
  56 static const unsigned XCore_ArgRegs[] = {
  57   XCore::R0, XCore::R1, XCore::R2, XCore::R3
  58 };
  59
  60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
  61 {
  62   return XCore_ArgRegs;
  63 }
  64
  65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
  66 {
  67   return array_lengthof(XCore_ArgRegs);
  68 }
  69
  70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
  71   return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
  72           UnwindTablesMandatory;
  73 }
  74
  75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  76                                                                          const {
  77   static const unsigned CalleeSavedRegs[] = {
  78     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
  79     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
  80     0
  81   };
  82   return CalleeSavedRegs;
  83 }
  84
  85 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  86   BitVector Reserved(getNumRegs());
  87   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
  88
  89   Reserved.set(XCore::CP);
  90   Reserved.set(XCore::DP);
  91   Reserved.set(XCore::SP);
  92   Reserved.set(XCore::LR);
  93   if (TFI->hasFP(MF)) {
  94     Reserved.set(XCore::R10);
  95   }
  96   return Reserved;
  97 }
  98
  99 bool
 100 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
 101   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 102
 103   // TODO can we estimate stack size?
 104   return TFI->hasFP(MF);
 105 }
 106
 107 bool
 108 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
 109   return false;
 110 }
 111
 112 // This function eliminates ADJCALLSTACKDOWN,
 113 // ADJCALLSTACKUP pseudo instructions
 114 void XCoreRegisterInfo::
 115 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 116                               MachineBasicBlock::iterator I) const {
 117   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 118
 119   if (!TFI->hasReservedCallFrame(MF)) {
 120     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
 121     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
 122     MachineInstr *Old = I;
 123     uint64_t Amount = Old->getOperand(0).getImm();
 124     if (Amount != 0) {
 125       // We need to keep the stack aligned properly.  To do this, we round the
 126       // amount of space needed for the outgoing arguments up to the next
 127       // alignment boundary.
 128       unsigned Align = TFI->getStackAlignment();
 129       Amount = (Amount+Align-1)/Align*Align;
 130
 131       assert(Amount%4 == 0);
 132       Amount /= 4;
 133
 134       bool isU6 = isImmU6(Amount);
 135       if (!isU6 && !isImmU16(Amount)) {
 136         // FIX could emit multiple instructions in this case.
 137 #ifndef NDEBUG
 138         errs() << "eliminateCallFramePseudoInstr size too big: "
 139                << Amount << "\n";
 140 #endif
 141         llvm_unreachable(0);
 142       }
 143
 144       MachineInstr *New;
 145       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
 146         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
 147         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
 148           .addImm(Amount);
 149       } else {
 150         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
 151         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
 152         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
 153           .addImm(Amount);
 154       }
 155
 156       // Replace the pseudo instruction with a new instruction...
 157       MBB.insert(I, New);
 158     }
 159   }
 160
 161   MBB.erase(I);
 162 }
 163
 164 void
 165 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 166                                        int SPAdj, RegScavenger *RS) const {
 167   assert(SPAdj == 0 && "Unexpected");
 168   MachineInstr &MI = *II;
 169   DebugLoc dl = MI.getDebugLoc();
 170   unsigned i = 0;
 171
 172   while (!MI.getOperand(i).isFI()) {
 173     ++i;
 174     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 175   }
 176
 177   MachineOperand &FrameOp = MI.getOperand(i);
 178   int FrameIndex = FrameOp.getIndex();
 179
 180   MachineFunction &MF = *MI.getParent()->getParent();
 181   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 182   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 183   int StackSize = MF.getFrameInfo()->getStackSize();
 184
 185   #ifndef NDEBUG
 186   DEBUG(errs() << "\nFunction         : "
 187         << MF.getFunction()->getName() << "\n");
 188   DEBUG(errs() << "<--------->\n");
 189   DEBUG(MI.print(errs()));
 190   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
 191   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
 192   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
 193   #endif
 194
 195   Offset += StackSize;
 196
 197   // fold constant into offset.
 198   Offset += MI.getOperand(i + 1).getImm();
 199   MI.getOperand(i + 1).ChangeToImmediate(0);
 200
 201   assert(Offset%4 == 0 && "Misaligned stack offset");
 202
 203   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
 204
 205   Offset/=4;
 206
 207   bool FP = TFI->hasFP(MF);
 208
 209   unsigned Reg = MI.getOperand(0).getReg();
 210   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
 211
 212   assert(XCore::GRRegsRegisterClass->contains(Reg) &&
 213          "Unexpected register operand");
 214
 215   MachineBasicBlock &MBB = *MI.getParent();
 216
 217   if (FP) {
 218     bool isUs = isImmUs(Offset);
 219     unsigned FramePtr = XCore::R10;
 220
 221     if (!isUs) {
 222       if (!RS)
 223         report_fatal_error("eliminateFrameIndex Frame size too big: " +
 224                            Twine(Offset));
 225       unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
 226                                                  SPAdj);
 227       loadConstant(MBB, II, ScratchReg, Offset, dl);
 228       switch (MI.getOpcode()) {
 229       case XCore::LDWFI:
 230         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
 231               .addReg(FramePtr)
 232               .addReg(ScratchReg, RegState::Kill);
 233         break;
 234       case XCore::STWFI:
 235         BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
 236               .addReg(Reg, getKillRegState(isKill))
 237               .addReg(FramePtr)
 238               .addReg(ScratchReg, RegState::Kill);
 239         break;
 240       case XCore::LDAWFI:
 241         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
 242               .addReg(FramePtr)
 243               .addReg(ScratchReg, RegState::Kill);
 244         break;
 245       default:
 246         llvm_unreachable("Unexpected Opcode");
 247       }
 248     } else {
 249       switch (MI.getOpcode()) {
 250       case XCore::LDWFI:
 251         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
 252               .addReg(FramePtr)
 253               .addImm(Offset);
 254         break;
 255       case XCore::STWFI:
 256         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
 257               .addReg(Reg, getKillRegState(isKill))
 258               .addReg(FramePtr)
 259               .addImm(Offset);
 260         break;
 261       case XCore::LDAWFI:
 262         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
 263               .addReg(FramePtr)
 264               .addImm(Offset);
 265         break;
 266       default:
 267         llvm_unreachable("Unexpected Opcode");
 268       }
 269     }
 270   } else {
 271     bool isU6 = isImmU6(Offset);
 272     if (!isU6 && !isImmU16(Offset))
 273       report_fatal_error("eliminateFrameIndex Frame size too big: " +
 274                          Twine(Offset));
 275
 276     switch (MI.getOpcode()) {
 277     int NewOpcode;
 278     case XCore::LDWFI:
 279       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
 280       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
 281             .addImm(Offset);
 282       break;
 283     case XCore::STWFI:
 284       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
 285       BuildMI(MBB, II, dl, TII.get(NewOpcode))
 286             .addReg(Reg, getKillRegState(isKill))
 287             .addImm(Offset);
 288       break;
 289     case XCore::LDAWFI:
 290       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
 291       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
 292             .addImm(Offset);
 293       break;
 294     default:
 295       llvm_unreachable("Unexpected Opcode");
 296     }
 297   }
 298   // Erase old instruction.
 299   MBB.erase(II);
 300 }
 301
 302 void XCoreRegisterInfo::
 303 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 304             unsigned DstReg, int64_t Value, DebugLoc dl) const {
 305   // TODO use mkmsk if possible.
 306   if (!isImmU16(Value)) {
 307     // TODO use constant pool.
 308     report_fatal_error("loadConstant value too big " + Twine(Value));
 309   }
 310   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
 311   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
 312 }
 313
 314 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 315   return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 316 }
 317
 318 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 319   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 320
 321   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
 322 }
 323
 324 unsigned XCoreRegisterInfo::getRARegister() const {
 325   return XCore::LR;
 326 }
 327
 328 #include "XCoreGenRegisterInfo.inc"
 329