lib/Target/Mips/MipsISelLowering.h

   1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Mips uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef MipsISELLOWERING_H
  16 #define MipsISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "Mips.h"
  21 #include "MipsSubtarget.h"
  22
  23 namespace llvm {
  24   namespace MipsISD {
  25     enum NodeType {
  26       // Start the numbering from where ISD NodeType finishes.
  27       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  28
  29       // Jump and link (call)
  30       JmpLink,
  31
  32       // Get the Higher 16 bits from a 32-bit immediate
  33       // No relation with Mips Hi register
  34       Hi,
  35
  36       // Get the Lower 16 bits from a 32-bit immediate
  37       // No relation with Mips Lo register
  38       Lo,
  39
  40       // Handle gp_rel (small data/bss sections) relocation.
  41       GPRel,
  42
  43       // Floating Point Branch Conditional
  44       FPBrcond,
  45
  46       // Floating Point Compare
  47       FPCmp,
  48
  49       // Floating Point Conditional Moves
  50       CMovFP_T,
  51       CMovFP_F,
  52
  53       // Floating Point Rounding
  54       FPRound,
  55
  56       // Return
  57       Ret,
  58
  59       // MAdd/Sub nodes
  60       MAdd,
  61       MAddu,
  62       MSub,
  63       MSubu,
  64
  65       // DivRem(u)
  66       DivRem,
  67       DivRemU
  68     };
  69   }
  70
  71   //===--------------------------------------------------------------------===//
  72   // TargetLowering Implementation
  73   //===--------------------------------------------------------------------===//
  74
  75   class MipsTargetLowering : public TargetLowering  {
  76   public:
  77     explicit MipsTargetLowering(MipsTargetMachine &TM);
  78
  79     /// LowerOperation - Provide custom lowering hooks for some operations.
  80     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  81
  82     /// getTargetNodeName - This method returns the name of a target specific
  83     //  DAG node.
  84     virtual const char *getTargetNodeName(unsigned Opcode) const;
  85
  86     /// getSetCCResultType - get the ISD::SETCC result ValueType
  87     MVT::SimpleValueType getSetCCResultType(EVT VT) const;
  88
  89     /// getFunctionAlignment - Return the Log2 alignment of this function.
  90     virtual unsigned getFunctionAlignment(const Function *F) const;
  91
  92     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  93   private:
  94     // Subtarget Info
  95     const MipsSubtarget *Subtarget;
  96
  97
  98     // Lower Operand helpers
  99     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 100                             CallingConv::ID CallConv, bool isVarArg,
 101                             const SmallVectorImpl<ISD::InputArg> &Ins,
 102                             DebugLoc dl, SelectionDAG &DAG,
 103                             SmallVectorImpl<SDValue> &InVals) const;
 104
 105     // Lower Operand specifics
 106     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 107     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 108     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 109     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 110     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 111     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 112     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 113     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 114     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 115     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 116
 117     virtual SDValue
 118       LowerFormalArguments(SDValue Chain,
 119                            CallingConv::ID CallConv, bool isVarArg,
 120                            const SmallVectorImpl<ISD::InputArg> &Ins,
 121                            DebugLoc dl, SelectionDAG &DAG,
 122                            SmallVectorImpl<SDValue> &InVals) const;
 123
 124     virtual SDValue
 125       LowerCall(SDValue Chain, SDValue Callee,
 126                 CallingConv::ID CallConv, bool isVarArg,
 127                 bool &isTailCall,
 128                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 129                 const SmallVectorImpl<SDValue> &OutVals,
 130                 const SmallVectorImpl<ISD::InputArg> &Ins,
 131                 DebugLoc dl, SelectionDAG &DAG,
 132                 SmallVectorImpl<SDValue> &InVals) const;
 133
 134     virtual SDValue
 135       LowerReturn(SDValue Chain,
 136                   CallingConv::ID CallConv, bool isVarArg,
 137                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 138                   const SmallVectorImpl<SDValue> &OutVals,
 139                   DebugLoc dl, SelectionDAG &DAG) const;
 140
 141     virtual MachineBasicBlock *
 142       EmitInstrWithCustomInserter(MachineInstr *MI,
 143                                   MachineBasicBlock *MBB) const;
 144
 145     // Inline asm support
 146     ConstraintType getConstraintType(const std::string &Constraint) const;
 147
 148     /// Examine constraint string and operand type and determine a weight value.
 149     /// The operand object must already have been set up with the operand type.
 150     ConstraintWeight getSingleConstraintMatchWeight(
 151       AsmOperandInfo &info, const char *constraint) const;
 152
 153     std::pair<unsigned, const TargetRegisterClass*>
 154               getRegForInlineAsmConstraint(const std::string &Constraint,
 155               EVT VT) const;
 156
 157     std::vector<unsigned>
 158     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 159               EVT VT) const;
 160
 161     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 162
 163     /// isFPImmLegal - Returns true if the target can instruction select the
 164     /// specified FP immediate natively. If false, the legalizer will
 165     /// materialize the FP immediate as a load from a constant pool.
 166     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 167   };
 168 }
 169
 170 #endif // MipsISELLOWERING_H