lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

   1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the SelectionDAG::LegalizeVectors method.
  11 //
  12 // The vector legalizer looks for vector operations which might need to be
  13 // scalarized and legalizes them. This is a separate step from Legalize because
  14 // scalarizing can introduce illegal types.  For example, suppose we have an
  15 // ISD::SDIV of type v2i64 on x86-32.  The type is legal (for example, addition
  16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
  17 // operation, which introduces nodes with the illegal type i64 which must be
  18 // expanded.  Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
  19 // the operation must be unrolled, which introduces nodes with the illegal
  20 // type i8 which must be promoted.
  21 //
  22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
  23 // or operations that happen to take a vector which are custom-lowered;
  24 // the legalization for such operations never produces nodes
  25 // with illegal types, so it's okay to put off legalizing them until
  26 // SelectionDAG::Legalize runs.
  27 //
  28 //===----------------------------------------------------------------------===//
  29
  30 #include "llvm/CodeGen/SelectionDAG.h"
  31 #include "llvm/Target/TargetLowering.h"
  32 using namespace llvm;
  33
  34 namespace {
  35 class VectorLegalizer {
  36   SelectionDAG& DAG;
  37   const TargetLowering &TLI;
  38   bool Changed; // Keep track of whether anything changed
  39
  40   /// LegalizedNodes - For nodes that are of legal width, and that have more
  41   /// than one use, this map indicates what regularized operand to use.  This
  42   /// allows us to avoid legalizing the same thing more than once.
  43   DenseMap<SDValue, SDValue> LegalizedNodes;
  44
  45   // Adds a node to the translation cache
  46   void AddLegalizedOperand(SDValue From, SDValue To) {
  47     LegalizedNodes.insert(std::make_pair(From, To));
  48     // If someone requests legalization of the new node, return itself.
  49     if (From != To)
  50       LegalizedNodes.insert(std::make_pair(To, To));
  51   }
  52
  53   // Legalizes the given node
  54   SDValue LegalizeOp(SDValue Op);
  55   // Assuming the node is legal, "legalize" the results
  56   SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
  57   // Implements unrolling a VSETCC.
  58   SDValue UnrollVSETCC(SDValue Op);
  59   // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
  60   // isn't legal.
  61   // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
  62   // SINT_TO_FLOAT and SHR on vectors isn't legal.
  63   SDValue ExpandUINT_TO_FLOAT(SDValue Op);
  64   SDValue ExpandFNEG(SDValue Op);
  65   // Implements vector promotion; this is essentially just bitcasting the
  66   // operands to a different type and bitcasting the result back to the
  67   // original type.
  68   SDValue PromoteVectorOp(SDValue Op);
  69
  70   public:
  71   bool Run();
  72   VectorLegalizer(SelectionDAG& dag) :
  73       DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
  74 };
  75
  76 bool VectorLegalizer::Run() {
  77   // The legalize process is inherently a bottom-up recursive process (users
  78   // legalize their uses before themselves).  Given infinite stack space, we
  79   // could just start legalizing on the root and traverse the whole graph.  In
  80   // practice however, this causes us to run out of stack space on large basic
  81   // blocks.  To avoid this problem, compute an ordering of the nodes where each
  82   // node is only legalized after all of its operands are legalized.
  83   DAG.AssignTopologicalOrder();
  84   for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
  85        E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
  86     LegalizeOp(SDValue(I, 0));
  87
  88   // Finally, it's possible the root changed.  Get the new root.
  89   SDValue OldRoot = DAG.getRoot();
  90   assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
  91   DAG.setRoot(LegalizedNodes[OldRoot]);
  92
  93   LegalizedNodes.clear();
  94
  95   // Remove dead nodes now.
  96   DAG.RemoveDeadNodes();
  97
  98   return Changed;
  99 }
 100
 101 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
 102   // Generic legalization: just pass the operand through.
 103   for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
 104     AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
 105   return Result.getValue(Op.getResNo());
 106 }
 107
 108 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
 109   // Note that LegalizeOp may be reentered even from single-use nodes, which
 110   // means that we always must cache transformed nodes.
 111   DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
 112   if (I != LegalizedNodes.end()) return I->second;
 113
 114   SDNode* Node = Op.getNode();
 115
 116   // Legalize the operands
 117   SmallVector<SDValue, 8> Ops;
 118   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
 119     Ops.push_back(LegalizeOp(Node->getOperand(i)));
 120
 121   SDValue Result =
 122     SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
 123
 124   bool HasVectorValue = false;
 125   for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
 126        J != E;
 127        ++J)
 128     HasVectorValue |= J->isVector();
 129   if (!HasVectorValue)
 130     return TranslateLegalizeResults(Op, Result);
 131
 132   EVT QueryType;
 133   switch (Op.getOpcode()) {
 134   default:
 135     return TranslateLegalizeResults(Op, Result);
 136   case ISD::ADD:
 137   case ISD::SUB:
 138   case ISD::MUL:
 139   case ISD::SDIV:
 140   case ISD::UDIV:
 141   case ISD::SREM:
 142   case ISD::UREM:
 143   case ISD::FADD:
 144   case ISD::FSUB:
 145   case ISD::FMUL:
 146   case ISD::FDIV:
 147   case ISD::FREM:
 148   case ISD::AND:
 149   case ISD::OR:
 150   case ISD::XOR:
 151   case ISD::SHL:
 152   case ISD::SRA:
 153   case ISD::SRL:
 154   case ISD::ROTL:
 155   case ISD::ROTR:
 156   case ISD::CTTZ:
 157   case ISD::CTLZ:
 158   case ISD::CTPOP:
 159   case ISD::SELECT:
 160   case ISD::SELECT_CC:
 161   case ISD::VSETCC:
 162   case ISD::ZERO_EXTEND:
 163   case ISD::ANY_EXTEND:
 164   case ISD::TRUNCATE:
 165   case ISD::SIGN_EXTEND:
 166   case ISD::FP_TO_SINT:
 167   case ISD::FP_TO_UINT:
 168   case ISD::FNEG:
 169   case ISD::FABS:
 170   case ISD::FSQRT:
 171   case ISD::FSIN:
 172   case ISD::FCOS:
 173   case ISD::FPOWI:
 174   case ISD::FPOW:
 175   case ISD::FLOG:
 176   case ISD::FLOG2:
 177   case ISD::FLOG10:
 178   case ISD::FEXP:
 179   case ISD::FEXP2:
 180   case ISD::FCEIL:
 181   case ISD::FTRUNC:
 182   case ISD::FRINT:
 183   case ISD::FNEARBYINT:
 184   case ISD::FFLOOR:
 185     QueryType = Node->getValueType(0);
 186     break;
 187   case ISD::SIGN_EXTEND_INREG:
 188   case ISD::FP_ROUND_INREG:
 189     QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
 190     break;
 191   case ISD::SINT_TO_FP:
 192   case ISD::UINT_TO_FP:
 193     QueryType = Node->getOperand(0).getValueType();
 194     break;
 195   }
 196
 197   switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
 198   case TargetLowering::Promote:
 199     // "Promote" the operation by bitcasting
 200     Result = PromoteVectorOp(Op);
 201     Changed = true;
 202     break;
 203   case TargetLowering::Legal: break;
 204   case TargetLowering::Custom: {
 205     SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
 206     if (Tmp1.getNode()) {
 207       Result = Tmp1;
 208       break;
 209     }
 210     // FALL THROUGH
 211   }
 212   case TargetLowering::Expand:
 213     if (Node->getOpcode() == ISD::UINT_TO_FP)
 214       Result = ExpandUINT_TO_FLOAT(Op);
 215     else if (Node->getOpcode() == ISD::FNEG)
 216       Result = ExpandFNEG(Op);
 217     else if (Node->getOpcode() == ISD::VSETCC)
 218       Result = UnrollVSETCC(Op);
 219     else
 220       Result = DAG.UnrollVectorOp(Op.getNode());
 221     break;
 222   }
 223
 224   // Make sure that the generated code is itself legal.
 225   if (Result != Op) {
 226     Result = LegalizeOp(Result);
 227     Changed = true;
 228   }
 229
 230   // Note that LegalizeOp may be reentered even from single-use nodes, which
 231   // means that we always must cache transformed nodes.
 232   AddLegalizedOperand(Op, Result);
 233   return Result;
 234 }
 235
 236 SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
 237   // Vector "promotion" is basically just bitcasting and doing the operation
 238   // in a different type.  For example, x86 promotes ISD::AND on v2i32 to
 239   // v1i64.
 240   EVT VT = Op.getValueType();
 241   assert(Op.getNode()->getNumValues() == 1 &&
 242          "Can't promote a vector with multiple results!");
 243   EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
 244   DebugLoc dl = Op.getDebugLoc();
 245   SmallVector<SDValue, 4> Operands(Op.getNumOperands());
 246
 247   for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
 248     if (Op.getOperand(j).getValueType().isVector())
 249       Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
 250     else
 251       Operands[j] = Op.getOperand(j);
 252   }
 253
 254   Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
 255
 256   return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 257 }
 258
 259 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
 260
 261
 262   EVT VT = Op.getOperand(0).getValueType();
 263   DebugLoc DL = Op.getDebugLoc();
 264
 265   // Make sure that the SINT_TO_FP and SRL instructions are available.
 266   if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) ||
 267       !TLI.isOperationLegalOrCustom(ISD::SRL, VT))
 268       return DAG.UnrollVectorOp(Op.getNode());
 269
 270  EVT SVT = VT.getScalarType();
 271   assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
 272       "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
 273
 274   unsigned BW = SVT.getSizeInBits();
 275   SDValue HalfWord = DAG.getConstant(BW/2, VT);
 276
 277   // Constants to clear the upper part of the word.
 278   // Notice that we can also use SHL+SHR, but using a constant is slightly
 279   // faster on x86.
 280   uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
 281   SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
 282
 283   // Two to the power of half-word-size.
 284   SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
 285
 286   // Clear upper part of LO, lower HI
 287   SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
 288   SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
 289
 290   // Convert hi and lo to floats
 291   // Convert the hi part back to the upper values
 292   SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
 293           fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
 294   SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
 295
 296   // Add the two halves
 297   return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
 298 }
 299
 300
 301 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
 302   if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
 303     SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
 304     return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
 305                        Zero, Op.getOperand(0));
 306   }
 307   return DAG.UnrollVectorOp(Op.getNode());
 308 }
 309
 310 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
 311   EVT VT = Op.getValueType();
 312   unsigned NumElems = VT.getVectorNumElements();
 313   EVT EltVT = VT.getVectorElementType();
 314   SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
 315   EVT TmpEltVT = LHS.getValueType().getVectorElementType();
 316   DebugLoc dl = Op.getDebugLoc();
 317   SmallVector<SDValue, 8> Ops(NumElems);
 318   for (unsigned i = 0; i < NumElems; ++i) {
 319     SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
 320                                   DAG.getIntPtrConstant(i));
 321     SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
 322                                   DAG.getIntPtrConstant(i));
 323     Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
 324                          LHSElem, RHSElem, CC);
 325     Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
 326                          DAG.getConstant(APInt::getAllOnesValue
 327                                          (EltVT.getSizeInBits()), EltVT),
 328                          DAG.getConstant(0, EltVT));
 329   }
 330   return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
 331 }
 332
 333 }
 334
 335 bool SelectionDAG::LegalizeVectors() {
 336   return VectorLegalizer(*this).Run();
 337 }