lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

   1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SELECTIONDAGBUILDER_H
  15 #define SELECTIONDAGBUILDER_H
  16
  17 #include "llvm/Constants.h"
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/ADT/APInt.h"
  20 #include "llvm/ADT/DenseMap.h"
  21 #include "llvm/CodeGen/SelectionDAGNodes.h"
  22 #include "llvm/CodeGen/ValueTypes.h"
  23 #include "llvm/Support/CallSite.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include <vector>
  26
  27 namespace llvm {
  28
  29 class AliasAnalysis;
  30 class AllocaInst;
  31 class BasicBlock;
  32 class BitCastInst;
  33 class BranchInst;
  34 class CallInst;
  35 class DbgValueInst;
  36 class ExtractElementInst;
  37 class ExtractValueInst;
  38 class FCmpInst;
  39 class FPExtInst;
  40 class FPToSIInst;
  41 class FPToUIInst;
  42 class FPTruncInst;
  43 class Function;
  44 class FunctionLoweringInfo;
  45 class GetElementPtrInst;
  46 class GCFunctionInfo;
  47 class ICmpInst;
  48 class IntToPtrInst;
  49 class IndirectBrInst;
  50 class InvokeInst;
  51 class InsertElementInst;
  52 class InsertValueInst;
  53 class Instruction;
  54 class LoadInst;
  55 class MachineBasicBlock;
  56 class MachineInstr;
  57 class MachineRegisterInfo;
  58 class MDNode;
  59 class PHINode;
  60 class PtrToIntInst;
  61 class ReturnInst;
  62 class SDDbgValue;
  63 class SExtInst;
  64 class SelectInst;
  65 class ShuffleVectorInst;
  66 class SIToFPInst;
  67 class StoreInst;
  68 class SwitchInst;
  69 class TargetData;
  70 class TargetLowering;
  71 class TruncInst;
  72 class UIToFPInst;
  73 class UnreachableInst;
  74 class UnwindInst;
  75 class VAArgInst;
  76 class ZExtInst;
  77
  78 //===----------------------------------------------------------------------===//
  79 /// SelectionDAGBuilder - This is the common target-independent lowering
  80 /// implementation that is parameterized by a TargetLowering object.
  81 ///
  82 class SelectionDAGBuilder {
  83   /// CurDebugLoc - current file + line number.  Changes as we build the DAG.
  84   DebugLoc CurDebugLoc;
  85
  86   DenseMap<const Value*, SDValue> NodeMap;
  87
  88   /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
  89   /// to preserve debug information for incoming arguments.
  90   DenseMap<const Value*, SDValue> UnusedArgNodeMap;
  91
  92   /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
  93   class DanglingDebugInfo {
  94     const DbgValueInst* DI;
  95     DebugLoc dl;
  96     unsigned SDNodeOrder;
  97   public:
  98     DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
  99     DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
 100       DI(di), dl(DL), SDNodeOrder(SDNO) { }
 101     const DbgValueInst* getDI() { return DI; }
 102     DebugLoc getdl() { return dl; }
 103     unsigned getSDNodeOrder() { return SDNodeOrder; }
 104   };
 105
 106   /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
 107   /// yet seen the referent.  We defer handling these until we do see it.
 108   DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
 109
 110 public:
 111   /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
 112   /// them up and then emit token factor nodes when possible.  This allows us to
 113   /// get simple disambiguation between loads without worrying about alias
 114   /// analysis.
 115   SmallVector<SDValue, 8> PendingLoads;
 116 private:
 117
 118   /// PendingExports - CopyToReg nodes that copy values to virtual registers
 119   /// for export to other blocks need to be emitted before any terminator
 120   /// instruction, but they have no other ordering requirements. We bunch them
 121   /// up and the emit a single tokenfactor for them just before terminator
 122   /// instructions.
 123   SmallVector<SDValue, 8> PendingExports;
 124
 125   /// SDNodeOrder - A unique monotonically increasing number used to order the
 126   /// SDNodes we create.
 127   unsigned SDNodeOrder;
 128
 129   /// Case - A struct to record the Value for a switch case, and the
 130   /// case's target basic block.
 131   struct Case {
 132     Constant* Low;
 133     Constant* High;
 134     MachineBasicBlock* BB;
 135
 136     Case() : Low(0), High(0), BB(0) { }
 137     Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
 138       Low(low), High(high), BB(bb) { }
 139     APInt size() const {
 140       const APInt &rHigh = cast<ConstantInt>(High)->getValue();
 141       const APInt &rLow  = cast<ConstantInt>(Low)->getValue();
 142       return (rHigh - rLow + 1ULL);
 143     }
 144   };
 145
 146   struct CaseBits {
 147     uint64_t Mask;
 148     MachineBasicBlock* BB;
 149     unsigned Bits;
 150
 151     CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
 152       Mask(mask), BB(bb), Bits(bits) { }
 153   };
 154
 155   typedef std::vector<Case>           CaseVector;
 156   typedef std::vector<CaseBits>       CaseBitsVector;
 157   typedef CaseVector::iterator        CaseItr;
 158   typedef std::pair<CaseItr, CaseItr> CaseRange;
 159
 160   /// CaseRec - A struct with ctor used in lowering switches to a binary tree
 161   /// of conditional branches.
 162   struct CaseRec {
 163     CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
 164             CaseRange r) :
 165     CaseBB(bb), LT(lt), GE(ge), Range(r) {}
 166
 167     /// CaseBB - The MBB in which to emit the compare and branch
 168     MachineBasicBlock *CaseBB;
 169     /// LT, GE - If nonzero, we know the current case value must be less-than or
 170     /// greater-than-or-equal-to these Constants.
 171     const Constant *LT;
 172     const Constant *GE;
 173     /// Range - A pair of iterators representing the range of case values to be
 174     /// processed at this point in the binary search tree.
 175     CaseRange Range;
 176   };
 177
 178   typedef std::vector<CaseRec> CaseRecVector;
 179
 180   /// The comparison function for sorting the switch case values in the vector.
 181   /// WARNING: Case ranges should be disjoint!
 182   struct CaseCmp {
 183     bool operator()(const Case &C1, const Case &C2) {
 184       assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
 185       const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
 186       const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
 187       return CI1->getValue().slt(CI2->getValue());
 188     }
 189   };
 190
 191   struct CaseBitsCmp {
 192     bool operator()(const CaseBits &C1, const CaseBits &C2) {
 193       return C1.Bits > C2.Bits;
 194     }
 195   };
 196
 197   size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
 198
 199   /// CaseBlock - This structure is used to communicate between
 200   /// SelectionDAGBuilder and SDISel for the code generation of additional basic
 201   /// blocks needed by multi-case switch statements.
 202   struct CaseBlock {
 203     CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
 204               const Value *cmpmiddle,
 205               MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
 206               MachineBasicBlock *me)
 207       : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
 208         TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
 209     // CC - the condition code to use for the case block's setcc node
 210     ISD::CondCode CC;
 211     // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
 212     // Emit by default LHS op RHS. MHS is used for range comparisons:
 213     // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
 214     const Value *CmpLHS, *CmpMHS, *CmpRHS;
 215     // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
 216     MachineBasicBlock *TrueBB, *FalseBB;
 217     // ThisBB - the block into which to emit the code for the setcc and branches
 218     MachineBasicBlock *ThisBB;
 219   };
 220   struct JumpTable {
 221     JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
 222               MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
 223
 224     /// Reg - the virtual register containing the index of the jump table entry
 225     //. to jump to.
 226     unsigned Reg;
 227     /// JTI - the JumpTableIndex for this jump table in the function.
 228     unsigned JTI;
 229     /// MBB - the MBB into which to emit the code for the indirect jump.
 230     MachineBasicBlock *MBB;
 231     /// Default - the MBB of the default bb, which is a successor of the range
 232     /// check MBB.  This is when updating PHI nodes in successors.
 233     MachineBasicBlock *Default;
 234   };
 235   struct JumpTableHeader {
 236     JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
 237                     bool E = false):
 238       First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
 239     APInt First;
 240     APInt Last;
 241     const Value *SValue;
 242     MachineBasicBlock *HeaderBB;
 243     bool Emitted;
 244   };
 245   typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
 246
 247   struct BitTestCase {
 248     BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
 249       Mask(M), ThisBB(T), TargetBB(Tr) { }
 250     uint64_t Mask;
 251     MachineBasicBlock *ThisBB;
 252     MachineBasicBlock *TargetBB;
 253   };
 254
 255   typedef SmallVector<BitTestCase, 3> BitTestInfo;
 256
 257   struct BitTestBlock {
 258     BitTestBlock(APInt F, APInt R, const Value* SV,
 259                  unsigned Rg, EVT RgVT, bool E,
 260                  MachineBasicBlock* P, MachineBasicBlock* D,
 261                  const BitTestInfo& C):
 262       First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
 263       Parent(P), Default(D), Cases(C) { }
 264     APInt First;
 265     APInt Range;
 266     const Value *SValue;
 267     unsigned Reg;
 268     EVT RegVT;
 269     bool Emitted;
 270     MachineBasicBlock *Parent;
 271     MachineBasicBlock *Default;
 272     BitTestInfo Cases;
 273   };
 274
 275 public:
 276   // TLI - This is information that describes the available target features we
 277   // need for lowering.  This indicates when operations are unavailable,
 278   // implemented with a libcall, etc.
 279   const TargetMachine &TM;
 280   const TargetLowering &TLI;
 281   SelectionDAG &DAG;
 282   const TargetData *TD;
 283   AliasAnalysis *AA;
 284
 285   /// SwitchCases - Vector of CaseBlock structures used to communicate
 286   /// SwitchInst code generation information.
 287   std::vector<CaseBlock> SwitchCases;
 288   /// JTCases - Vector of JumpTable structures used to communicate
 289   /// SwitchInst code generation information.
 290   std::vector<JumpTableBlock> JTCases;
 291   /// BitTestCases - Vector of BitTestBlock structures used to communicate
 292   /// SwitchInst code generation information.
 293   std::vector<BitTestBlock> BitTestCases;
 294
 295   // Emit PHI-node-operand constants only once even if used by multiple
 296   // PHI nodes.
 297   DenseMap<const Constant *, unsigned> ConstantsOut;
 298
 299   /// FuncInfo - Information about the function as a whole.
 300   ///
 301   FunctionLoweringInfo &FuncInfo;
 302
 303   /// OptLevel - What optimization level we're generating code for.
 304   ///
 305   CodeGenOpt::Level OptLevel;
 306
 307   /// GFI - Garbage collection metadata for the function.
 308   GCFunctionInfo *GFI;
 309
 310   /// HasTailCall - This is set to true if a call in the current
 311   /// block has been translated as a tail call. In this case,
 312   /// no subsequent DAG nodes should be created.
 313   ///
 314   bool HasTailCall;
 315
 316   LLVMContext *Context;
 317
 318   SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
 319                       CodeGenOpt::Level ol)
 320     : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
 321       DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
 322       HasTailCall(false), Context(dag.getContext()) {
 323   }
 324
 325   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
 326
 327   /// clear - Clear out the current SelectionDAG and the associated
 328   /// state and prepare this SelectionDAGBuilder object to be used
 329   /// for a new block. This doesn't clear out information about
 330   /// additional blocks that are needed to complete switch lowering
 331   /// or PHI node updating; that information is cleared out as it is
 332   /// consumed.
 333   void clear();
 334
 335   /// clearDanglingDebugInfo - Clear the dangling debug information
 336   /// map. This function is seperated from the clear so that debug
 337   /// information that is dangling in a basic block can be properly
 338   /// resolved in a different basic block. This allows the
 339   /// SelectionDAG to resolve dangling debug information attached
 340   /// to PHI nodes.
 341   void clearDanglingDebugInfo();
 342
 343   /// getRoot - Return the current virtual root of the Selection DAG,
 344   /// flushing any PendingLoad items. This must be done before emitting
 345   /// a store or any other node that may need to be ordered after any
 346   /// prior load instructions.
 347   ///
 348   SDValue getRoot();
 349
 350   /// getControlRoot - Similar to getRoot, but instead of flushing all the
 351   /// PendingLoad items, flush all the PendingExports items. It is necessary
 352   /// to do this before emitting a terminator instruction.
 353   ///
 354   SDValue getControlRoot();
 355
 356   DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
 357
 358   unsigned getSDNodeOrder() const { return SDNodeOrder; }
 359
 360   void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
 361
 362   /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
 363   /// from how the code appeared in the source. The ordering is used by the
 364   /// scheduler to effectively turn off scheduling.
 365   void AssignOrderingToNode(const SDNode *Node);
 366
 367   void visit(const Instruction &I);
 368
 369   void visit(unsigned Opcode, const User &I);
 370
 371   // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
 372   // generate the debug data structures now that we've seen its definition.
 373   void resolveDanglingDebugInfo(const Value *V, SDValue Val);
 374   SDValue getValue(const Value *V);
 375   SDValue getNonRegisterValue(const Value *V);
 376   SDValue getValueImpl(const Value *V);
 377
 378   void setValue(const Value *V, SDValue NewN) {
 379     SDValue &N = NodeMap[V];
 380     assert(N.getNode() == 0 && "Already set a value for this node!");
 381     N = NewN;
 382   }
 383
 384   void setUnusedArgValue(const Value *V, SDValue NewN) {
 385     SDValue &N = UnusedArgNodeMap[V];
 386     assert(N.getNode() == 0 && "Already set a value for this node!");
 387     N = NewN;
 388   }
 389
 390   void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
 391                             MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
 392                             MachineBasicBlock *SwitchBB, unsigned Opc);
 393   void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
 394                                     MachineBasicBlock *FBB,
 395                                     MachineBasicBlock *CurBB,
 396                                     MachineBasicBlock *SwitchBB);
 397   bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
 398   bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
 399   void CopyToExportRegsIfNeeded(const Value *V);
 400   void ExportFromCurrentBlock(const Value *V);
 401   void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
 402                    MachineBasicBlock *LandingPad = NULL);
 403
 404   /// UpdateSplitBlock - When an MBB was split during scheduling, update the
 405   /// references that ned to refer to the last resulting block.
 406   void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
 407
 408 private:
 409   // Terminator instructions.
 410   void visitRet(const ReturnInst &I);
 411   void visitBr(const BranchInst &I);
 412   void visitSwitch(const SwitchInst &I);
 413   void visitIndirectBr(const IndirectBrInst &I);
 414   void visitUnreachable(const UnreachableInst &I) { /* noop */ }
 415
 416   // Helpers for visitSwitch
 417   bool handleSmallSwitchRange(CaseRec& CR,
 418                               CaseRecVector& WorkList,
 419                               const Value* SV,
 420                               MachineBasicBlock* Default,
 421                               MachineBasicBlock *SwitchBB);
 422   bool handleJTSwitchCase(CaseRec& CR,
 423                           CaseRecVector& WorkList,
 424                           const Value* SV,
 425                           MachineBasicBlock* Default,
 426                           MachineBasicBlock *SwitchBB);
 427   bool handleBTSplitSwitchCase(CaseRec& CR,
 428                                CaseRecVector& WorkList,
 429                                const Value* SV,
 430                                MachineBasicBlock* Default,
 431                                MachineBasicBlock *SwitchBB);
 432   bool handleBitTestsSwitchCase(CaseRec& CR,
 433                                 CaseRecVector& WorkList,
 434                                 const Value* SV,
 435                                 MachineBasicBlock* Default,
 436                                 MachineBasicBlock *SwitchBB);
 437
 438   uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst);
 439   void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst);
 440 public:
 441   void visitSwitchCase(CaseBlock &CB,
 442                        MachineBasicBlock *SwitchBB);
 443   void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
 444   void visitBitTestCase(BitTestBlock &BB,
 445                         MachineBasicBlock* NextMBB,
 446                         unsigned Reg,
 447                         BitTestCase &B,
 448                         MachineBasicBlock *SwitchBB);
 449   void visitJumpTable(JumpTable &JT);
 450   void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
 451                             MachineBasicBlock *SwitchBB);
 452
 453 private:
 454   // These all get lowered before this pass.
 455   void visitInvoke(const InvokeInst &I);
 456   void visitUnwind(const UnwindInst &I);
 457
 458   void visitBinary(const User &I, unsigned OpCode);
 459   void visitShift(const User &I, unsigned Opcode);
 460   void visitAdd(const User &I)  { visitBinary(I, ISD::ADD); }
 461   void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
 462   void visitSub(const User &I)  { visitBinary(I, ISD::SUB); }
 463   void visitFSub(const User &I);
 464   void visitMul(const User &I)  { visitBinary(I, ISD::MUL); }
 465   void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
 466   void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
 467   void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
 468   void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
 469   void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
 470   void visitSDiv(const User &I);
 471   void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
 472   void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
 473   void visitOr  (const User &I) { visitBinary(I, ISD::OR); }
 474   void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
 475   void visitShl (const User &I) { visitShift(I, ISD::SHL); }
 476   void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
 477   void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
 478   void visitICmp(const User &I);
 479   void visitFCmp(const User &I);
 480   // Visit the conversion instructions
 481   void visitTrunc(const User &I);
 482   void visitZExt(const User &I);
 483   void visitSExt(const User &I);
 484   void visitFPTrunc(const User &I);
 485   void visitFPExt(const User &I);
 486   void visitFPToUI(const User &I);
 487   void visitFPToSI(const User &I);
 488   void visitUIToFP(const User &I);
 489   void visitSIToFP(const User &I);
 490   void visitPtrToInt(const User &I);
 491   void visitIntToPtr(const User &I);
 492   void visitBitCast(const User &I);
 493
 494   void visitExtractElement(const User &I);
 495   void visitInsertElement(const User &I);
 496   void visitShuffleVector(const User &I);
 497
 498   void visitExtractValue(const ExtractValueInst &I);
 499   void visitInsertValue(const InsertValueInst &I);
 500
 501   void visitGetElementPtr(const User &I);
 502   void visitSelect(const User &I);
 503
 504   void visitAlloca(const AllocaInst &I);
 505   void visitLoad(const LoadInst &I);
 506   void visitStore(const StoreInst &I);
 507   void visitPHI(const PHINode &I);
 508   void visitCall(const CallInst &I);
 509   bool visitMemCmpCall(const CallInst &I);
 510
 511   void visitInlineAsm(ImmutableCallSite CS);
 512   const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
 513   void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
 514
 515   void visitPow(const CallInst &I);
 516   void visitExp2(const CallInst &I);
 517   void visitExp(const CallInst &I);
 518   void visitLog(const CallInst &I);
 519   void visitLog2(const CallInst &I);
 520   void visitLog10(const CallInst &I);
 521
 522   void visitVAStart(const CallInst &I);
 523   void visitVAArg(const VAArgInst &I);
 524   void visitVAEnd(const CallInst &I);
 525   void visitVACopy(const CallInst &I);
 526
 527   void visitUserOp1(const Instruction &I) {
 528     llvm_unreachable("UserOp1 should not exist at instruction selection time!");
 529   }
 530   void visitUserOp2(const Instruction &I) {
 531     llvm_unreachable("UserOp2 should not exist at instruction selection time!");
 532   }
 533
 534   const char *implVisitBinaryAtomic(const CallInst& I, ISD::NodeType Op);
 535   const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
 536
 537   void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
 538
 539   /// EmitFuncArgumentDbgValue - If V is an function argument then create
 540   /// corresponding DBG_VALUE machine instruction for it now. At the end of
 541   /// instruction selection, they will be inserted to the entry BB.
 542   bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
 543                                 int64_t Offset, const SDValue &N);
 544 };
 545
 546 } // end namespace llvm
 547
 548 #endif