lib/Target/ARM/ARMMCCodeEmitter.cpp

   1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the ARMMCCodeEmitter class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "mccodeemitter"
  15 #include "ARM.h"
  16 #include "ARMAddressingModes.h"
  17 #include "ARMFixupKinds.h"
  18 #include "ARMInstrInfo.h"
  19 #include "ARMMCExpr.h"
  20 #include "ARMSubtarget.h"
  21 #include "llvm/MC/MCCodeEmitter.h"
  22 #include "llvm/MC/MCExpr.h"
  23 #include "llvm/MC/MCInst.h"
  24 #include "llvm/ADT/Statistic.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
  29 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
  30
  31 namespace {
  32 class ARMMCCodeEmitter : public MCCodeEmitter {
  33   ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
  34   void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
  35   const TargetMachine &TM;
  36   const TargetInstrInfo &TII;
  37   const ARMSubtarget *Subtarget;
  38   MCContext &Ctx;
  39
  40 public:
  41   ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
  42     : TM(tm), TII(*TM.getInstrInfo()),
  43       Subtarget(&TM.getSubtarget<ARMSubtarget>()), Ctx(ctx) {
  44   }
  45
  46   ~ARMMCCodeEmitter() {}
  47
  48   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
  49
  50   // getBinaryCodeForInstr - TableGen'erated function for getting the
  51   // binary encoding for an instruction.
  52   unsigned getBinaryCodeForInstr(const MCInst &MI,
  53                                  SmallVectorImpl<MCFixup> &Fixups) const;
  54
  55   /// getMachineOpValue - Return binary encoding of operand. If the machine
  56   /// operand requires relocation, record the relocation and return zero.
  57   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
  58                              SmallVectorImpl<MCFixup> &Fixups) const;
  59
  60   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
  61   /// the specified operand. This is used for operands with :lower16: and
  62   /// :upper16: prefixes.
  63   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
  64                                SmallVectorImpl<MCFixup> &Fixups) const;
  65
  66   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
  67                               unsigned &Reg, unsigned &Imm,
  68                               SmallVectorImpl<MCFixup> &Fixups) const;
  69
  70   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
  71   /// BL branch target.
  72   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
  73                                    SmallVectorImpl<MCFixup> &Fixups) const;
  74
  75   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
  76   /// BLX branch target.
  77   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
  78                                     SmallVectorImpl<MCFixup> &Fixups) const;
  79
  80   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
  81   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
  82                                    SmallVectorImpl<MCFixup> &Fixups) const;
  83
  84   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
  85   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
  86                                     SmallVectorImpl<MCFixup> &Fixups) const;
  87
  88   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
  89   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
  90                                    SmallVectorImpl<MCFixup> &Fixups) const;
  91
  92   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
  93   /// branch target.
  94   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
  95                                   SmallVectorImpl<MCFixup> &Fixups) const;
  96
  97   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
  98   /// immediate Thumb2 direct branch target.
  99   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 100                                   SmallVectorImpl<MCFixup> &Fixups) const;
 101
 102   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
 103   /// branch target.
 104   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 105                                      SmallVectorImpl<MCFixup> &Fixups) const;
 106
 107   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
 108   /// ADR label target.
 109   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 110                               SmallVectorImpl<MCFixup> &Fixups) const;
 111   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 112                               SmallVectorImpl<MCFixup> &Fixups) const;
 113   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 114                               SmallVectorImpl<MCFixup> &Fixups) const;
 115
 116
 117   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
 118   /// operand.
 119   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
 120                                    SmallVectorImpl<MCFixup> &Fixups) const;
 121
 122   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
 123   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
 124                                          SmallVectorImpl<MCFixup> &Fixups)const;
 125
 126   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
 127   /// operand.
 128   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
 129                                    SmallVectorImpl<MCFixup> &Fixups) const;
 130
 131
 132   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
 133   /// operand as needed by load/store instructions.
 134   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
 135                                SmallVectorImpl<MCFixup> &Fixups) const;
 136
 137   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
 138   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
 139                                SmallVectorImpl<MCFixup> &Fixups) const {
 140     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
 141     switch (Mode) {
 142     default: assert(0 && "Unknown addressing sub-mode!");
 143     case ARM_AM::da: return 0;
 144     case ARM_AM::ia: return 1;
 145     case ARM_AM::db: return 2;
 146     case ARM_AM::ib: return 3;
 147     }
 148   }
 149   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 150   ///
 151   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
 152     switch (ShOpc) {
 153     default: llvm_unreachable("Unknown shift opc!");
 154     case ARM_AM::no_shift:
 155     case ARM_AM::lsl: return 0;
 156     case ARM_AM::lsr: return 1;
 157     case ARM_AM::asr: return 2;
 158     case ARM_AM::ror:
 159     case ARM_AM::rrx: return 3;
 160     }
 161     return 0;
 162   }
 163
 164   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
 165   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
 166                                SmallVectorImpl<MCFixup> &Fixups) const;
 167
 168   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
 169   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
 170                                      SmallVectorImpl<MCFixup> &Fixups) const;
 171
 172   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
 173   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
 174                                      SmallVectorImpl<MCFixup> &Fixups) const;
 175
 176   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
 177   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
 178                                SmallVectorImpl<MCFixup> &Fixups) const;
 179
 180   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
 181   /// operand.
 182   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
 183                                      SmallVectorImpl<MCFixup> &Fixups) const;
 184
 185   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
 186   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
 187                                 SmallVectorImpl<MCFixup> &Fixups) const;
 188
 189   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
 190   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
 191                                 SmallVectorImpl<MCFixup> &Fixups) const;
 192
 193   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
 194   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
 195                                SmallVectorImpl<MCFixup> &Fixups) const;
 196
 197   /// getCCOutOpValue - Return encoding of the 's' bit.
 198   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
 199                            SmallVectorImpl<MCFixup> &Fixups) const {
 200     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
 201     // '1' respectively.
 202     return MI.getOperand(Op).getReg() == ARM::CPSR;
 203   }
 204
 205   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
 206   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
 207                            SmallVectorImpl<MCFixup> &Fixups) const {
 208     unsigned SoImm = MI.getOperand(Op).getImm();
 209     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
 210     assert(SoImmVal != -1 && "Not a valid so_imm value!");
 211
 212     // Encode rotate_imm.
 213     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
 214       << ARMII::SoRotImmShift;
 215
 216     // Encode immed_8.
 217     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
 218     return Binary;
 219   }
 220
 221   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
 222   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
 223                            SmallVectorImpl<MCFixup> &Fixups) const {
 224     unsigned SoImm = MI.getOperand(Op).getImm();
 225     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
 226     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
 227     return Encoded;
 228   }
 229
 230   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
 231     SmallVectorImpl<MCFixup> &Fixups) const;
 232   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
 233     SmallVectorImpl<MCFixup> &Fixups) const;
 234   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
 235     SmallVectorImpl<MCFixup> &Fixups) const;
 236   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
 237     SmallVectorImpl<MCFixup> &Fixups) const;
 238
 239   /// getSORegOpValue - Return an encoded so_reg shifted register value.
 240   unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
 241                            SmallVectorImpl<MCFixup> &Fixups) const;
 242   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
 243                              SmallVectorImpl<MCFixup> &Fixups) const;
 244
 245   unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
 246                             SmallVectorImpl<MCFixup> &Fixups) const {
 247     switch (MI.getOperand(Op).getImm()) {
 248     default: assert (0 && "Not a valid rot_imm value!");
 249     case 0:  return 0;
 250     case 8:  return 1;
 251     case 16: return 2;
 252     case 24: return 3;
 253     }
 254   }
 255
 256   unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
 257                                  SmallVectorImpl<MCFixup> &Fixups) const {
 258     return MI.getOperand(Op).getImm() - 1;
 259   }
 260
 261   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
 262                                    SmallVectorImpl<MCFixup> &Fixups) const {
 263     return 64 - MI.getOperand(Op).getImm();
 264   }
 265
 266   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
 267                                       SmallVectorImpl<MCFixup> &Fixups) const;
 268
 269   unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
 270                          SmallVectorImpl<MCFixup> &Fixups) const;
 271
 272   unsigned getSsatBitPosValue(const MCInst &MI, unsigned Op,
 273                               SmallVectorImpl<MCFixup> &Fixups) const;
 274
 275   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
 276                                   SmallVectorImpl<MCFixup> &Fixups) const;
 277   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
 278                                       SmallVectorImpl<MCFixup> &Fixups) const;
 279   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
 280                                         SmallVectorImpl<MCFixup> &Fixups) const;
 281   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
 282                                         SmallVectorImpl<MCFixup> &Fixups) const;
 283   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
 284                                      SmallVectorImpl<MCFixup> &Fixups) const;
 285
 286   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
 287                              SmallVectorImpl<MCFixup> &Fixups) const;
 288   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
 289                               SmallVectorImpl<MCFixup> &Fixups) const;
 290   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
 291                               SmallVectorImpl<MCFixup> &Fixups) const;
 292   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
 293                               SmallVectorImpl<MCFixup> &Fixups) const;
 294
 295   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
 296                                       unsigned EncodedValue) const;
 297   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
 298                                           unsigned EncodedValue) const;
 299   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
 300                                     unsigned EncodedValue) const;
 301
 302   unsigned VFPThumb2PostEncoder(const MCInst &MI,
 303                                 unsigned EncodedValue) const;
 304
 305   void EmitByte(unsigned char C, raw_ostream &OS) const {
 306     OS << (char)C;
 307   }
 308
 309   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
 310     // Output the constant in little endian byte order.
 311     for (unsigned i = 0; i != Size; ++i) {
 312       EmitByte(Val & 255, OS);
 313       Val >>= 8;
 314     }
 315   }
 316
 317   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
 318                          SmallVectorImpl<MCFixup> &Fixups) const;
 319 };
 320
 321 } // end anonymous namespace
 322
 323 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
 324                                             MCContext &Ctx) {
 325   return new ARMMCCodeEmitter(TM, Ctx);
 326 }
 327
 328 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
 329 /// instructions, and rewrite them to their Thumb2 form if we are currently in
 330 /// Thumb2 mode.
 331 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
 332                                                  unsigned EncodedValue) const {
 333   if (Subtarget->isThumb2()) {
 334     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
 335     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
 336     // set to 1111.
 337     unsigned Bit24 = EncodedValue & 0x01000000;
 338     unsigned Bit28 = Bit24 << 4;
 339     EncodedValue &= 0xEFFFFFFF;
 340     EncodedValue |= Bit28;
 341     EncodedValue |= 0x0F000000;
 342   }
 343
 344   return EncodedValue;
 345 }
 346
 347 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
 348 /// instructions, and rewrite them to their Thumb2 form if we are currently in
 349 /// Thumb2 mode.
 350 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
 351                                                  unsigned EncodedValue) const {
 352   if (Subtarget->isThumb2()) {
 353     EncodedValue &= 0xF0FFFFFF;
 354     EncodedValue |= 0x09000000;
 355   }
 356
 357   return EncodedValue;
 358 }
 359
 360 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
 361 /// instructions, and rewrite them to their Thumb2 form if we are currently in
 362 /// Thumb2 mode.
 363 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
 364                                                  unsigned EncodedValue) const {
 365   if (Subtarget->isThumb2()) {
 366     EncodedValue &= 0x00FFFFFF;
 367     EncodedValue |= 0xEE000000;
 368   }
 369
 370   return EncodedValue;
 371 }
 372
 373 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
 374 /// them to their Thumb2 form if we are currently in Thumb2 mode.
 375 unsigned ARMMCCodeEmitter::
 376 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
 377   if (Subtarget->isThumb2()) {
 378     EncodedValue &= 0x0FFFFFFF;
 379     EncodedValue |= 0xE0000000;
 380   }
 381   return EncodedValue;
 382 }
 383
 384 /// getMachineOpValue - Return binary encoding of operand. If the machine
 385 /// operand requires relocation, record the relocation and return zero.
 386 unsigned ARMMCCodeEmitter::
 387 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
 388                   SmallVectorImpl<MCFixup> &Fixups) const {
 389   if (MO.isReg()) {
 390     unsigned Reg = MO.getReg();
 391     unsigned RegNo = getARMRegisterNumbering(Reg);
 392
 393     // Q registers are encoded as 2x their register number.
 394     switch (Reg) {
 395     default:
 396       return RegNo;
 397     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
 398     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
 399     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
 400     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
 401       return 2 * RegNo;
 402     }
 403   } else if (MO.isImm()) {
 404     return static_cast<unsigned>(MO.getImm());
 405   } else if (MO.isFPImm()) {
 406     return static_cast<unsigned>(APFloat(MO.getFPImm())
 407                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
 408   }
 409
 410   llvm_unreachable("Unable to encode MCOperand!");
 411   return 0;
 412 }
 413
 414 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
 415 bool ARMMCCodeEmitter::
 416 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
 417                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
 418   const MCOperand &MO  = MI.getOperand(OpIdx);
 419   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 420
 421   Reg = getARMRegisterNumbering(MO.getReg());
 422
 423   int32_t SImm = MO1.getImm();
 424   bool isAdd = true;
 425
 426   // Special value for #-0
 427   if (SImm == INT32_MIN)
 428     SImm = 0;
 429
 430   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 431   if (SImm < 0) {
 432     SImm = -SImm;
 433     isAdd = false;
 434   }
 435
 436   Imm = SImm;
 437   return isAdd;
 438 }
 439
 440 /// getBranchTargetOpValue - Helper function to get the branch target operand,
 441 /// which is either an immediate or requires a fixup.
 442 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 443                                        unsigned FixupKind,
 444                                        SmallVectorImpl<MCFixup> &Fixups) {
 445   const MCOperand &MO = MI.getOperand(OpIdx);
 446
 447   // If the destination is an immediate, we have nothing to do.
 448   if (MO.isImm()) return MO.getImm();
 449   assert(MO.isExpr() && "Unexpected branch target type!");
 450   const MCExpr *Expr = MO.getExpr();
 451   MCFixupKind Kind = MCFixupKind(FixupKind);
 452   Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 453
 454   // All of the information is in the fixup.
 455   return 0;
 456 }
 457
 458 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
 459 uint32_t ARMMCCodeEmitter::
 460 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
 461                         SmallVectorImpl<MCFixup> &Fixups) const {
 462   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
 463 }
 464
 465 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
 466 /// BLX branch target.
 467 uint32_t ARMMCCodeEmitter::
 468 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
 469                          SmallVectorImpl<MCFixup> &Fixups) const {
 470   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
 471 }
 472
 473 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
 474 uint32_t ARMMCCodeEmitter::
 475 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
 476                         SmallVectorImpl<MCFixup> &Fixups) const {
 477   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
 478 }
 479
 480 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
 481 uint32_t ARMMCCodeEmitter::
 482 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
 483                          SmallVectorImpl<MCFixup> &Fixups) const {
 484   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
 485 }
 486
 487 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
 488 uint32_t ARMMCCodeEmitter::
 489 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
 490                         SmallVectorImpl<MCFixup> &Fixups) const {
 491   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
 492 }
 493
 494 /// Return true if this branch has a non-always predication
 495 static bool HasConditionalBranch(const MCInst &MI) {
 496   int NumOp = MI.getNumOperands();
 497   if (NumOp >= 2) {
 498     for (int i = 0; i < NumOp-1; ++i) {
 499       const MCOperand &MCOp1 = MI.getOperand(i);
 500       const MCOperand &MCOp2 = MI.getOperand(i + 1);
 501       if (MCOp1.isImm() && MCOp2.isReg() &&
 502           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
 503         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
 504           return true;
 505       }
 506     }
 507   }
 508   return false;
 509 }
 510
 511 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
 512 /// target.
 513 uint32_t ARMMCCodeEmitter::
 514 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 515                        SmallVectorImpl<MCFixup> &Fixups) const {
 516   // FIXME: This really, really shouldn't use TargetMachine. We don't want
 517   // coupling between MC and TM anywhere we can help it.
 518   if (Subtarget->isThumb2())
 519     return
 520       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
 521   return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
 522 }
 523
 524 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
 525 /// target.
 526 uint32_t ARMMCCodeEmitter::
 527 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 528                           SmallVectorImpl<MCFixup> &Fixups) const {
 529   if (HasConditionalBranch(MI))
 530     return ::getBranchTargetOpValue(MI, OpIdx,
 531                                     ARM::fixup_arm_condbranch, Fixups);
 532   return ::getBranchTargetOpValue(MI, OpIdx,
 533                                   ARM::fixup_arm_uncondbranch, Fixups);
 534 }
 535
 536
 537
 538
 539 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
 540 /// immediate branch target.
 541 uint32_t ARMMCCodeEmitter::
 542 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
 543                        SmallVectorImpl<MCFixup> &Fixups) const {
 544   unsigned Val =
 545     ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
 546   bool I  = (Val & 0x800000);
 547   bool J1 = (Val & 0x400000);
 548   bool J2 = (Val & 0x200000);
 549   if (I ^ J1)
 550     Val &= ~0x400000;
 551   else
 552     Val |= 0x400000;
 553
 554   if (I ^ J2)
 555     Val &= ~0x200000;
 556   else
 557     Val |= 0x200000;
 558
 559   return Val;
 560 }
 561
 562 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
 563 /// target.
 564 uint32_t ARMMCCodeEmitter::
 565 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 566                    SmallVectorImpl<MCFixup> &Fixups) const {
 567   assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
 568   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
 569                                   Fixups);
 570 }
 571
 572 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
 573 /// target.
 574 uint32_t ARMMCCodeEmitter::
 575 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 576                    SmallVectorImpl<MCFixup> &Fixups) const {
 577   assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
 578   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
 579                                   Fixups);
 580 }
 581
 582 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
 583 /// target.
 584 uint32_t ARMMCCodeEmitter::
 585 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
 586                    SmallVectorImpl<MCFixup> &Fixups) const {
 587   assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
 588   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
 589                                   Fixups);
 590 }
 591
 592 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
 593 /// operand.
 594 uint32_t ARMMCCodeEmitter::
 595 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
 596                               SmallVectorImpl<MCFixup> &) const {
 597   // [Rn, Rm]
 598   //   {5-3} = Rm
 599   //   {2-0} = Rn
 600   const MCOperand &MO1 = MI.getOperand(OpIdx);
 601   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
 602   unsigned Rn = getARMRegisterNumbering(MO1.getReg());
 603   unsigned Rm = getARMRegisterNumbering(MO2.getReg());
 604   return (Rm << 3) | Rn;
 605 }
 606
 607 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
 608 uint32_t ARMMCCodeEmitter::
 609 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
 610                         SmallVectorImpl<MCFixup> &Fixups) const {
 611   // {17-13} = reg
 612   // {12}    = (U)nsigned (add == '1', sub == '0')
 613   // {11-0}  = imm12
 614   unsigned Reg, Imm12;
 615   bool isAdd = true;
 616   // If The first operand isn't a register, we have a label reference.
 617   const MCOperand &MO = MI.getOperand(OpIdx);
 618   if (!MO.isReg()) {
 619     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
 620     Imm12 = 0;
 621     isAdd = false ; // 'U' bit is set as part of the fixup.
 622
 623     assert(MO.isExpr() && "Unexpected machine operand type!");
 624     const MCExpr *Expr = MO.getExpr();
 625
 626     MCFixupKind Kind;
 627     if (Subtarget->isThumb2())
 628       Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
 629     else
 630       Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
 631     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 632
 633     ++MCNumCPRelocations;
 634   } else
 635     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
 636
 637   uint32_t Binary = Imm12 & 0xfff;
 638   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 639   if (isAdd)
 640     Binary |= (1 << 12);
 641   Binary |= (Reg << 13);
 642   return Binary;
 643 }
 644
 645 /// getT2AddrModeImm8s4OpValue - Return encoding info for
 646 /// 'reg +/- imm8<<2' operand.
 647 uint32_t ARMMCCodeEmitter::
 648 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
 649                         SmallVectorImpl<MCFixup> &Fixups) const {
 650   // {12-9} = reg
 651   // {8}    = (U)nsigned (add == '1', sub == '0')
 652   // {7-0}  = imm8
 653   unsigned Reg, Imm8;
 654   bool isAdd = true;
 655   // If The first operand isn't a register, we have a label reference.
 656   const MCOperand &MO = MI.getOperand(OpIdx);
 657   if (!MO.isReg()) {
 658     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
 659     Imm8 = 0;
 660     isAdd = false ; // 'U' bit is set as part of the fixup.
 661
 662     assert(MO.isExpr() && "Unexpected machine operand type!");
 663     const MCExpr *Expr = MO.getExpr();
 664     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
 665     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 666
 667     ++MCNumCPRelocations;
 668   } else
 669     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
 670
 671   uint32_t Binary = (Imm8 >> 2) & 0xff;
 672   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 673   if (isAdd)
 674     Binary |= (1 << 8);
 675   Binary |= (Reg << 9);
 676   return Binary;
 677 }
 678
 679 // FIXME: This routine assumes that a binary
 680 // expression will always result in a PCRel expression
 681 // In reality, its only true if one or more subexpressions
 682 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
 683 // but this is good enough for now.
 684 static bool EvaluateAsPCRel(const MCExpr *Expr) {
 685   switch (Expr->getKind()) {
 686   default: assert(0 && "Unexpected expression type");
 687   case MCExpr::SymbolRef: return false;
 688   case MCExpr::Binary: return true;
 689   }
 690 }
 691
 692 uint32_t
 693 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
 694                                       SmallVectorImpl<MCFixup> &Fixups) const {
 695   // {20-16} = imm{15-12}
 696   // {11-0}  = imm{11-0}
 697   const MCOperand &MO = MI.getOperand(OpIdx);
 698   if (MO.isImm())
 699     // Hi / lo 16 bits already extracted during earlier passes.
 700     return static_cast<unsigned>(MO.getImm());
 701
 702   // Handle :upper16: and :lower16: assembly prefixes.
 703   const MCExpr *E = MO.getExpr();
 704   if (E->getKind() == MCExpr::Target) {
 705     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
 706     E = ARM16Expr->getSubExpr();
 707
 708     MCFixupKind Kind;
 709     switch (ARM16Expr->getKind()) {
 710     default: assert(0 && "Unsupported ARMFixup");
 711     case ARMMCExpr::VK_ARM_HI16:
 712       if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
 713         Kind = MCFixupKind(Subtarget->isThumb2()
 714                            ? ARM::fixup_t2_movt_hi16_pcrel
 715                            : ARM::fixup_arm_movt_hi16_pcrel);
 716       else
 717         Kind = MCFixupKind(Subtarget->isThumb2()
 718                            ? ARM::fixup_t2_movt_hi16
 719                            : ARM::fixup_arm_movt_hi16);
 720       break;
 721     case ARMMCExpr::VK_ARM_LO16:
 722       if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
 723         Kind = MCFixupKind(Subtarget->isThumb2()
 724                            ? ARM::fixup_t2_movw_lo16_pcrel
 725                            : ARM::fixup_arm_movw_lo16_pcrel);
 726       else
 727         Kind = MCFixupKind(Subtarget->isThumb2()
 728                            ? ARM::fixup_t2_movw_lo16
 729                            : ARM::fixup_arm_movw_lo16);
 730       break;
 731     }
 732     Fixups.push_back(MCFixup::Create(0, E, Kind));
 733     return 0;
 734   };
 735
 736   llvm_unreachable("Unsupported MCExpr type in MCOperand!");
 737   return 0;
 738 }
 739
 740 uint32_t ARMMCCodeEmitter::
 741 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
 742                     SmallVectorImpl<MCFixup> &Fixups) const {
 743   const MCOperand &MO = MI.getOperand(OpIdx);
 744   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
 745   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
 746   unsigned Rn = getARMRegisterNumbering(MO.getReg());
 747   unsigned Rm = getARMRegisterNumbering(MO1.getReg());
 748   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
 749   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
 750   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
 751   unsigned SBits = getShiftOp(ShOp);
 752
 753   // {16-13} = Rn
 754   // {12}    = isAdd
 755   // {11-0}  = shifter
 756   //  {3-0}  = Rm
 757   //  {4}    = 0
 758   //  {6-5}  = type
 759   //  {11-7} = imm
 760   uint32_t Binary = Rm;
 761   Binary |= Rn << 13;
 762   Binary |= SBits << 5;
 763   Binary |= ShImm << 7;
 764   if (isAdd)
 765     Binary |= 1 << 12;
 766   return Binary;
 767 }
 768
 769 uint32_t ARMMCCodeEmitter::
 770 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
 771                     SmallVectorImpl<MCFixup> &Fixups) const {
 772   // {17-14}  Rn
 773   // {13}     1 == imm12, 0 == Rm
 774   // {12}     isAdd
 775   // {11-0}   imm12/Rm
 776   const MCOperand &MO = MI.getOperand(OpIdx);
 777   unsigned Rn = getARMRegisterNumbering(MO.getReg());
 778   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
 779   Binary |= Rn << 14;
 780   return Binary;
 781 }
 782
 783 uint32_t ARMMCCodeEmitter::
 784 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
 785                           SmallVectorImpl<MCFixup> &Fixups) const {
 786   // {13}     1 == imm12, 0 == Rm
 787   // {12}     isAdd
 788   // {11-0}   imm12/Rm
 789   const MCOperand &MO = MI.getOperand(OpIdx);
 790   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
 791   unsigned Imm = MO1.getImm();
 792   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
 793   bool isReg = MO.getReg() != 0;
 794   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
 795   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
 796   if (isReg) {
 797     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
 798     Binary <<= 7;                    // Shift amount is bits [11:7]
 799     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
 800     Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
 801   }
 802   return Binary | (isAdd << 12) | (isReg << 13);
 803 }
 804
 805 uint32_t ARMMCCodeEmitter::
 806 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
 807                           SmallVectorImpl<MCFixup> &Fixups) const {
 808   // {9}      1 == imm8, 0 == Rm
 809   // {8}      isAdd
 810   // {7-4}    imm7_4/zero
 811   // {3-0}    imm3_0/Rm
 812   const MCOperand &MO = MI.getOperand(OpIdx);
 813   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
 814   unsigned Imm = MO1.getImm();
 815   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
 816   bool isImm = MO.getReg() == 0;
 817   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
 818   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
 819   if (!isImm)
 820     Imm8 = getARMRegisterNumbering(MO.getReg());
 821   return Imm8 | (isAdd << 8) | (isImm << 9);
 822 }
 823
 824 uint32_t ARMMCCodeEmitter::
 825 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
 826                     SmallVectorImpl<MCFixup> &Fixups) const {
 827   // {13}     1 == imm8, 0 == Rm
 828   // {12-9}   Rn
 829   // {8}      isAdd
 830   // {7-4}    imm7_4/zero
 831   // {3-0}    imm3_0/Rm
 832   const MCOperand &MO = MI.getOperand(OpIdx);
 833   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
 834   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
 835   unsigned Rn = getARMRegisterNumbering(MO.getReg());
 836   unsigned Imm = MO2.getImm();
 837   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
 838   bool isImm = MO1.getReg() == 0;
 839   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
 840   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
 841   if (!isImm)
 842     Imm8 = getARMRegisterNumbering(MO1.getReg());
 843   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
 844 }
 845
 846 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
 847 uint32_t ARMMCCodeEmitter::
 848 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
 849                           SmallVectorImpl<MCFixup> &Fixups) const {
 850   // [SP, #imm]
 851   //   {7-0} = imm8
 852   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 853   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
 854          "Unexpected base register!");
 855
 856   // The immediate is already shifted for the implicit zeroes, so no change
 857   // here.
 858   return MO1.getImm() & 0xff;
 859 }
 860
 861 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
 862 uint32_t ARMMCCodeEmitter::
 863 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
 864                      SmallVectorImpl<MCFixup> &Fixups) const {
 865   // [Rn, #imm]
 866   //   {7-3} = imm5
 867   //   {2-0} = Rn
 868   const MCOperand &MO = MI.getOperand(OpIdx);
 869   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 870   unsigned Rn = getARMRegisterNumbering(MO.getReg());
 871   unsigned Imm5 = MO1.getImm();
 872   return ((Imm5 & 0x1f) << 3) | Rn;
 873 }
 874
 875 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
 876 uint32_t ARMMCCodeEmitter::
 877 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
 878                      SmallVectorImpl<MCFixup> &Fixups) const {
 879   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
 880 }
 881
 882 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
 883 uint32_t ARMMCCodeEmitter::
 884 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
 885                     SmallVectorImpl<MCFixup> &Fixups) const {
 886   // {12-9} = reg
 887   // {8}    = (U)nsigned (add == '1', sub == '0')
 888   // {7-0}  = imm8
 889   unsigned Reg, Imm8;
 890   bool isAdd;
 891   // If The first operand isn't a register, we have a label reference.
 892   const MCOperand &MO = MI.getOperand(OpIdx);
 893   if (!MO.isReg()) {
 894     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
 895     Imm8 = 0;
 896     isAdd = false; // 'U' bit is handled as part of the fixup.
 897
 898     assert(MO.isExpr() && "Unexpected machine operand type!");
 899     const MCExpr *Expr = MO.getExpr();
 900     MCFixupKind Kind;
 901     if (Subtarget->isThumb2())
 902       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
 903     else
 904       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
 905     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 906
 907     ++MCNumCPRelocations;
 908   } else {
 909     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
 910     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
 911   }
 912
 913   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
 914   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 915   if (isAdd)
 916     Binary |= (1 << 8);
 917   Binary |= (Reg << 9);
 918   return Binary;
 919 }
 920
 921 unsigned ARMMCCodeEmitter::
 922 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
 923                 SmallVectorImpl<MCFixup> &Fixups) const {
 924   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
 925   // shifted. The second is either Rs, the amount to shift by, or reg0 in which
 926   // case the imm contains the amount to shift by.
 927   //
 928   // {3-0} = Rm.
 929   // {4}   = 1 if reg shift, 0 if imm shift
 930   // {6-5} = type
 931   //    If reg shift:
 932   //      {11-8} = Rs
 933   //      {7}    = 0
 934   //    else (imm shift)
 935   //      {11-7} = imm
 936
 937   const MCOperand &MO  = MI.getOperand(OpIdx);
 938   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 939   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
 940   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
 941
 942   // Encode Rm.
 943   unsigned Binary = getARMRegisterNumbering(MO.getReg());
 944
 945   // Encode the shift opcode.
 946   unsigned SBits = 0;
 947   unsigned Rs = MO1.getReg();
 948   if (Rs) {
 949     // Set shift operand (bit[7:4]).
 950     // LSL - 0001
 951     // LSR - 0011
 952     // ASR - 0101
 953     // ROR - 0111
 954     // RRX - 0110 and bit[11:8] clear.
 955     switch (SOpc) {
 956     default: llvm_unreachable("Unknown shift opc!");
 957     case ARM_AM::lsl: SBits = 0x1; break;
 958     case ARM_AM::lsr: SBits = 0x3; break;
 959     case ARM_AM::asr: SBits = 0x5; break;
 960     case ARM_AM::ror: SBits = 0x7; break;
 961     case ARM_AM::rrx: SBits = 0x6; break;
 962     }
 963   } else {
 964     // Set shift operand (bit[6:4]).
 965     // LSL - 000
 966     // LSR - 010
 967     // ASR - 100
 968     // ROR - 110
 969     switch (SOpc) {
 970     default: llvm_unreachable("Unknown shift opc!");
 971     case ARM_AM::lsl: SBits = 0x0; break;
 972     case ARM_AM::lsr: SBits = 0x2; break;
 973     case ARM_AM::asr: SBits = 0x4; break;
 974     case ARM_AM::ror: SBits = 0x6; break;
 975     }
 976   }
 977
 978   Binary |= SBits << 4;
 979   if (SOpc == ARM_AM::rrx)
 980     return Binary;
 981
 982   // Encode the shift operation Rs or shift_imm (except rrx).
 983   if (Rs) {
 984     // Encode Rs bit[11:8].
 985     assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
 986     return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
 987   }
 988
 989   // Encode shift_imm bit[11:7].
 990   return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
 991 }
 992
 993 unsigned ARMMCCodeEmitter::
 994 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
 995                 SmallVectorImpl<MCFixup> &Fixups) const {
 996   const MCOperand &MO1 = MI.getOperand(OpNum);
 997   const MCOperand &MO2 = MI.getOperand(OpNum+1);
 998   const MCOperand &MO3 = MI.getOperand(OpNum+2);
 999
1000   // Encoded as [Rn, Rm, imm].
1001   // FIXME: Needs fixup support.
1002   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1003   Value <<= 4;
1004   Value |= getARMRegisterNumbering(MO2.getReg());
1005   Value <<= 2;
1006   Value |= MO3.getImm();
1007
1008   return Value;
1009 }
1010
1011 unsigned ARMMCCodeEmitter::
1012 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1013                          SmallVectorImpl<MCFixup> &Fixups) const {
1014   const MCOperand &MO1 = MI.getOperand(OpNum);
1015   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1016
1017   // FIXME: Needs fixup support.
1018   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1019
1020   // Even though the immediate is 8 bits long, we need 9 bits in order
1021   // to represent the (inverse of the) sign bit.
1022   Value <<= 9;
1023   int32_t tmp = (int32_t)MO2.getImm();
1024   if (tmp < 0)
1025     tmp = abs(tmp);
1026   else
1027     Value |= 256; // Set the ADD bit
1028   Value |= tmp & 255;
1029   return Value;
1030 }
1031
1032 unsigned ARMMCCodeEmitter::
1033 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1034                          SmallVectorImpl<MCFixup> &Fixups) const {
1035   const MCOperand &MO1 = MI.getOperand(OpNum);
1036
1037   // FIXME: Needs fixup support.
1038   unsigned Value = 0;
1039   int32_t tmp = (int32_t)MO1.getImm();
1040   if (tmp < 0)
1041     tmp = abs(tmp);
1042   else
1043     Value |= 256; // Set the ADD bit
1044   Value |= tmp & 255;
1045   return Value;
1046 }
1047
1048 unsigned ARMMCCodeEmitter::
1049 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1050                          SmallVectorImpl<MCFixup> &Fixups) const {
1051   const MCOperand &MO1 = MI.getOperand(OpNum);
1052
1053   // FIXME: Needs fixup support.
1054   unsigned Value = 0;
1055   int32_t tmp = (int32_t)MO1.getImm();
1056   if (tmp < 0)
1057     tmp = abs(tmp);
1058   else
1059     Value |= 4096; // Set the ADD bit
1060   Value |= tmp & 4095;
1061   return Value;
1062 }
1063
1064 unsigned ARMMCCodeEmitter::
1065 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1066                 SmallVectorImpl<MCFixup> &Fixups) const {
1067   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1068   // shifted. The second is the amount to shift by.
1069   //
1070   // {3-0} = Rm.
1071   // {4}   = 0
1072   // {6-5} = type
1073   // {11-7} = imm
1074
1075   const MCOperand &MO  = MI.getOperand(OpIdx);
1076   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1077   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1078
1079   // Encode Rm.
1080   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1081
1082   // Encode the shift opcode.
1083   unsigned SBits = 0;
1084   // Set shift operand (bit[6:4]).
1085   // LSL - 000
1086   // LSR - 010
1087   // ASR - 100
1088   // ROR - 110
1089   switch (SOpc) {
1090   default: llvm_unreachable("Unknown shift opc!");
1091   case ARM_AM::lsl: SBits = 0x0; break;
1092   case ARM_AM::lsr: SBits = 0x2; break;
1093   case ARM_AM::asr: SBits = 0x4; break;
1094   case ARM_AM::ror: SBits = 0x6; break;
1095   }
1096
1097   Binary |= SBits << 4;
1098   if (SOpc == ARM_AM::rrx)
1099     return Binary;
1100
1101   // Encode shift_imm bit[11:7].
1102   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1103 }
1104
1105 unsigned ARMMCCodeEmitter::
1106 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1107                                SmallVectorImpl<MCFixup> &Fixups) const {
1108   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1109   // msb of the mask.
1110   const MCOperand &MO = MI.getOperand(Op);
1111   uint32_t v = ~MO.getImm();
1112   uint32_t lsb = CountTrailingZeros_32(v);
1113   uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1114   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1115   return lsb | (msb << 5);
1116 }
1117
1118 unsigned ARMMCCodeEmitter::
1119 getMsbOpValue(const MCInst &MI, unsigned Op,
1120               SmallVectorImpl<MCFixup> &Fixups) const {
1121   // MSB - 5 bits.
1122   uint32_t lsb = MI.getOperand(Op-1).getImm();
1123   uint32_t width = MI.getOperand(Op).getImm();
1124   uint32_t msb = lsb+width-1;
1125   assert (width != 0 && msb < 32 && "Illegal bit width!");
1126   return msb;
1127 }
1128
1129 unsigned ARMMCCodeEmitter::
1130 getSsatBitPosValue(const MCInst &MI, unsigned Op,
1131                    SmallVectorImpl<MCFixup> &Fixups) const {
1132   // For ssat instructions, the bit position should be encoded decremented by 1
1133   return MI.getOperand(Op).getImm()-1;
1134 }
1135
1136 unsigned ARMMCCodeEmitter::
1137 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1138                        SmallVectorImpl<MCFixup> &Fixups) const {
1139   // VLDM/VSTM:
1140   //   {12-8} = Vd
1141   //   {7-0}  = Number of registers
1142   //
1143   // LDM/STM:
1144   //   {15-0}  = Bitfield of GPRs.
1145   unsigned Reg = MI.getOperand(Op).getReg();
1146   bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1147   bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1148
1149   unsigned Binary = 0;
1150
1151   if (SPRRegs || DPRRegs) {
1152     // VLDM/VSTM
1153     unsigned RegNo = getARMRegisterNumbering(Reg);
1154     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1155     Binary |= (RegNo & 0x1f) << 8;
1156     if (SPRRegs)
1157       Binary |= NumRegs;
1158     else
1159       Binary |= NumRegs * 2;
1160   } else {
1161     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1162       unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1163       Binary |= 1 << RegNo;
1164     }
1165   }
1166
1167   return Binary;
1168 }
1169
1170 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1171 /// with the alignment operand.
1172 unsigned ARMMCCodeEmitter::
1173 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1174                            SmallVectorImpl<MCFixup> &Fixups) const {
1175   const MCOperand &Reg = MI.getOperand(Op);
1176   const MCOperand &Imm = MI.getOperand(Op + 1);
1177
1178   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1179   unsigned Align = 0;
1180
1181   switch (Imm.getImm()) {
1182   default: break;
1183   case 2:
1184   case 4:
1185   case 8:  Align = 0x01; break;
1186   case 16: Align = 0x02; break;
1187   case 32: Align = 0x03; break;
1188   }
1189
1190   return RegNo | (Align << 4);
1191 }
1192
1193 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1194 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1195 unsigned ARMMCCodeEmitter::
1196 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1197                                     SmallVectorImpl<MCFixup> &Fixups) const {
1198   const MCOperand &Reg = MI.getOperand(Op);
1199   const MCOperand &Imm = MI.getOperand(Op + 1);
1200
1201   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1202   unsigned Align = 0;
1203
1204   switch (Imm.getImm()) {
1205   default: break;
1206   case 2:
1207   case 4:
1208   case 8:
1209   case 16: Align = 0x00; break;
1210   case 32: Align = 0x03; break;
1211   }
1212
1213   return RegNo | (Align << 4);
1214 }
1215
1216
1217 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1218 /// alignment operand for use in VLD-dup instructions.  This is the same as
1219 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1220 /// different for VLD4-dup.
1221 unsigned ARMMCCodeEmitter::
1222 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1223                               SmallVectorImpl<MCFixup> &Fixups) const {
1224   const MCOperand &Reg = MI.getOperand(Op);
1225   const MCOperand &Imm = MI.getOperand(Op + 1);
1226
1227   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1228   unsigned Align = 0;
1229
1230   switch (Imm.getImm()) {
1231   default: break;
1232   case 2:
1233   case 4:
1234   case 8:  Align = 0x01; break;
1235   case 16: Align = 0x03; break;
1236   }
1237
1238   return RegNo | (Align << 4);
1239 }
1240
1241 unsigned ARMMCCodeEmitter::
1242 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1243                           SmallVectorImpl<MCFixup> &Fixups) const {
1244   const MCOperand &MO = MI.getOperand(Op);
1245   if (MO.getReg() == 0) return 0x0D;
1246   return MO.getReg();
1247 }
1248
1249 unsigned ARMMCCodeEmitter::
1250 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1251                   SmallVectorImpl<MCFixup> &Fixups) const {
1252   return 8 - MI.getOperand(Op).getImm();
1253 }
1254
1255 unsigned ARMMCCodeEmitter::
1256 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1257                    SmallVectorImpl<MCFixup> &Fixups) const {
1258   return 16 - MI.getOperand(Op).getImm();
1259 }
1260
1261 unsigned ARMMCCodeEmitter::
1262 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1263                    SmallVectorImpl<MCFixup> &Fixups) const {
1264   return 32 - MI.getOperand(Op).getImm();
1265 }
1266
1267 unsigned ARMMCCodeEmitter::
1268 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1269                    SmallVectorImpl<MCFixup> &Fixups) const {
1270   return 64 - MI.getOperand(Op).getImm();
1271 }
1272
1273 void ARMMCCodeEmitter::
1274 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1275                   SmallVectorImpl<MCFixup> &Fixups) const {
1276   // Pseudo instructions don't get encoded.
1277   const MCInstrDesc &Desc = TII.get(MI.getOpcode());
1278   uint64_t TSFlags = Desc.TSFlags;
1279   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1280     return;
1281   int Size;
1282   // Basic size info comes from the TSFlags field.
1283   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1284   default: llvm_unreachable("Unexpected instruction size!");
1285   case ARMII::Size2Bytes: Size = 2; break;
1286   case ARMII::Size4Bytes: Size = 4; break;
1287   }
1288   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1289   // Thumb 32-bit wide instructions need to emit the high order halfword
1290   // first.
1291   if (Subtarget->isThumb() && Size == 4) {
1292     EmitConstant(Binary >> 16, 2, OS);
1293     EmitConstant(Binary & 0xffff, 2, OS);
1294   } else
1295     EmitConstant(Binary, Size, OS);
1296   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1297 }
1298
1299 #include "ARMGenMCCodeEmitter.inc"