lib/Target/Alpha/AlphaISelDAGToDAG.cpp

   1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for Alpha,
  11 // converting from a legalized dag to a Alpha dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "Alpha.h"
  16 #include "AlphaTargetMachine.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/CodeGen/SelectionDAG.h"
  22 #include "llvm/CodeGen/SelectionDAGISel.h"
  23 #include "llvm/Target/TargetOptions.h"
  24 #include "llvm/Constants.h"
  25 #include "llvm/DerivedTypes.h"
  26 #include "llvm/GlobalValue.h"
  27 #include "llvm/Intrinsics.h"
  28 #include "llvm/LLVMContext.h"
  29 #include "llvm/Support/Compiler.h"
  30 #include "llvm/Support/Debug.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/raw_ostream.h"
  34 #include <algorithm>
  35 using namespace llvm;
  36
  37 namespace {
  38
  39   //===--------------------------------------------------------------------===//
  40   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
  41   /// instructions for SelectionDAG operations.
  42   class AlphaDAGToDAGISel : public SelectionDAGISel {
  43     static const int64_t IMM_LOW  = -32768;
  44     static const int64_t IMM_HIGH = 32767;
  45     static const int64_t IMM_MULT = 65536;
  46     static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
  47     static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW  * IMM_MULT;
  48
  49     static int64_t get_ldah16(int64_t x) {
  50       int64_t y = x / IMM_MULT;
  51       if (x % IMM_MULT > IMM_HIGH)
  52         ++y;
  53       return y;
  54     }
  55
  56     static int64_t get_lda16(int64_t x) {
  57       return x - get_ldah16(x) * IMM_MULT;
  58     }
  59
  60     /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
  61     /// instruction (if not, return 0).  Note that this code accepts partial
  62     /// zap masks.  For example (and LHS, 1) is a valid zap, as long we know
  63     /// that the bits 1-7 of LHS are already zero.  If LHS is non-null, we are
  64     /// in checking mode.  If LHS is null, we assume that the mask has already
  65     /// been validated before.
  66     uint64_t get_zapImm(SDValue LHS, uint64_t Constant) const {
  67       uint64_t BitsToCheck = 0;
  68       unsigned Result = 0;
  69       for (unsigned i = 0; i != 8; ++i) {
  70         if (((Constant >> 8*i) & 0xFF) == 0) {
  71           // nothing to do.
  72         } else {
  73           Result |= 1 << i;
  74           if (((Constant >> 8*i) & 0xFF) == 0xFF) {
  75             // If the entire byte is set, zapnot the byte.
  76           } else if (LHS.getNode() == 0) {
  77             // Otherwise, if the mask was previously validated, we know its okay
  78             // to zapnot this entire byte even though all the bits aren't set.
  79           } else {
  80             // Otherwise we don't know that the it's okay to zapnot this entire
  81             // byte.  Only do this iff we can prove that the missing bits are
  82             // already null, so the bytezap doesn't need to really null them.
  83             BitsToCheck |= ~Constant & (0xFF << 8*i);
  84           }
  85         }
  86       }
  87
  88       // If there are missing bits in a byte (for example, X & 0xEF00), check to
  89       // see if the missing bits (0x1000) are already known zero if not, the zap
  90       // isn't okay to do, as it won't clear all the required bits.
  91       if (BitsToCheck &&
  92           !CurDAG->MaskedValueIsZero(LHS,
  93                                      APInt(LHS.getValueSizeInBits(),
  94                                            BitsToCheck)))
  95         return 0;
  96
  97       return Result;
  98     }
  99
 100     static uint64_t get_zapImm(uint64_t x) {
 101       unsigned build = 0;
 102       for(int i = 0; i != 8; ++i) {
 103         if ((x & 0x00FF) == 0x00FF)
 104           build |= 1 << i;
 105         else if ((x & 0x00FF) != 0)
 106           return 0;
 107         x >>= 8;
 108       }
 109       return build;
 110     }
 111
 112
 113     static uint64_t getNearPower2(uint64_t x) {
 114       if (!x) return 0;
 115       unsigned at = CountLeadingZeros_64(x);
 116       uint64_t complow = 1ULL << (63 - at);
 117       uint64_t comphigh = 1ULL << (64 - at);
 118       //cerr << x << ":" << complow << ":" << comphigh << "\n";
 119       if (abs64(complow - x) <= abs64(comphigh - x))
 120         return complow;
 121       else
 122         return comphigh;
 123     }
 124
 125     static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
 126       uint64_t y = getNearPower2(x);
 127       if (swap)
 128         return (y - x) == r;
 129       else
 130         return (x - y) == r;
 131     }
 132
 133   public:
 134     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
 135       : SelectionDAGISel(TM)
 136     {}
 137
 138     /// getI64Imm - Return a target constant with the specified value, of type
 139     /// i64.
 140     inline SDValue getI64Imm(int64_t Imm) {
 141       return CurDAG->getTargetConstant(Imm, MVT::i64);
 142     }
 143
 144     // Select - Convert the specified operand from a target-independent to a
 145     // target-specific node if it hasn't already been changed.
 146     SDNode *Select(SDNode *N);
 147
 148     virtual const char *getPassName() const {
 149       return "Alpha DAG->DAG Pattern Instruction Selection";
 150     }
 151
 152     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 153     /// inline asm expressions.
 154     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 155                                               char ConstraintCode,
 156                                               std::vector<SDValue> &OutOps) {
 157       SDValue Op0;
 158       switch (ConstraintCode) {
 159       default: return true;
 160       case 'm':   // memory
 161         Op0 = Op;
 162         break;
 163       }
 164
 165       OutOps.push_back(Op0);
 166       return false;
 167     }
 168
 169 // Include the pieces autogenerated from the target description.
 170 #include "AlphaGenDAGISel.inc"
 171
 172 private:
 173     /// getTargetMachine - Return a reference to the TargetMachine, casted
 174     /// to the target-specific type.
 175     const AlphaTargetMachine &getTargetMachine() {
 176       return static_cast<const AlphaTargetMachine &>(TM);
 177     }
 178
 179     /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
 180     /// to the target-specific type.
 181     const AlphaInstrInfo *getInstrInfo() {
 182       return getTargetMachine().getInstrInfo();
 183     }
 184
 185     SDNode *getGlobalBaseReg();
 186     SDNode *getGlobalRetAddr();
 187     void SelectCALL(SDNode *Op);
 188
 189   };
 190 }
 191
 192 /// getGlobalBaseReg - Output the instructions required to put the
 193 /// GOT address into a register.
 194 ///
 195 SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
 196   unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
 197   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 198 }
 199
 200 /// getGlobalRetAddr - Grab the return address.
 201 ///
 202 SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
 203   unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
 204   return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
 205 }
 206
 207 // Select - Convert the specified operand from a target-independent to a
 208 // target-specific node if it hasn't already been changed.
 209 SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
 210   if (N->isMachineOpcode())
 211     return NULL;   // Already selected.
 212   DebugLoc dl = N->getDebugLoc();
 213
 214   switch (N->getOpcode()) {
 215   default: break;
 216   case AlphaISD::CALL:
 217     SelectCALL(N);
 218     return NULL;
 219
 220   case ISD::FrameIndex: {
 221     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 222     return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
 223                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
 224                                 getI64Imm(0));
 225   }
 226   case ISD::GLOBAL_OFFSET_TABLE:
 227     return getGlobalBaseReg();
 228   case AlphaISD::GlobalRetAddr:
 229     return getGlobalRetAddr();
 230
 231   case AlphaISD::DivCall: {
 232     SDValue Chain = CurDAG->getEntryNode();
 233     SDValue N0 = N->getOperand(0);
 234     SDValue N1 = N->getOperand(1);
 235     SDValue N2 = N->getOperand(2);
 236     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
 237                                  SDValue(0,0));
 238     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
 239                                  Chain.getValue(1));
 240     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
 241                                  Chain.getValue(1));
 242     SDNode *CNode =
 243       CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Glue,
 244                              Chain, Chain.getValue(1));
 245     Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
 246                                    SDValue(CNode, 1));
 247     return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
 248   }
 249
 250   case ISD::READCYCLECOUNTER: {
 251     SDValue Chain = N->getOperand(0);
 252     return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
 253                                   Chain);
 254   }
 255
 256   case ISD::Constant: {
 257     uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
 258
 259     if (uval == 0) {
 260       SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
 261                                                 Alpha::R31, MVT::i64);
 262       ReplaceUses(SDValue(N, 0), Result);
 263       return NULL;
 264     }
 265
 266     int64_t val = (int64_t)uval;
 267     int32_t val32 = (int32_t)val;
 268     if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
 269         val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
 270       break; //(LDAH (LDA))
 271     if ((uval >> 32) == 0 && //empty upper bits
 272         val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
 273       // val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
 274       break; //(zext (LDAH (LDA)))
 275     //Else use the constant pool
 276     ConstantInt *C = ConstantInt::get(
 277                                 Type::getInt64Ty(*CurDAG->getContext()), uval);
 278     SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
 279     SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI,
 280                                          SDValue(getGlobalBaseReg(), 0));
 281     return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
 282                                 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
 283   }
 284   case ISD::TargetConstantFP:
 285   case ISD::ConstantFP: {
 286     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
 287     bool isDouble = N->getValueType(0) == MVT::f64;
 288     EVT T = isDouble ? MVT::f64 : MVT::f32;
 289     if (CN->getValueAPF().isPosZero()) {
 290       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
 291                                   T, CurDAG->getRegister(Alpha::F31, T),
 292                                   CurDAG->getRegister(Alpha::F31, T));
 293     } else if (CN->getValueAPF().isNegZero()) {
 294       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
 295                                   T, CurDAG->getRegister(Alpha::F31, T),
 296                                   CurDAG->getRegister(Alpha::F31, T));
 297     } else {
 298       report_fatal_error("Unhandled FP constant type");
 299     }
 300     break;
 301   }
 302
 303   case ISD::SETCC:
 304     if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
 305       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
 306
 307       unsigned Opc = Alpha::WTF;
 308       bool rev = false;
 309       bool inv = false;
 310       switch(CC) {
 311       default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
 312       case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
 313         Opc = Alpha::CMPTEQ; break;
 314       case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
 315         Opc = Alpha::CMPTLT; break;
 316       case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
 317         Opc = Alpha::CMPTLE; break;
 318       case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
 319         Opc = Alpha::CMPTLT; rev = true; break;
 320       case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
 321         Opc = Alpha::CMPTLE; rev = true; break;
 322       case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
 323         Opc = Alpha::CMPTEQ; inv = true; break;
 324       case ISD::SETO:
 325         Opc = Alpha::CMPTUN; inv = true; break;
 326       case ISD::SETUO:
 327         Opc = Alpha::CMPTUN; break;
 328       };
 329       SDValue tmp1 = N->getOperand(rev?1:0);
 330       SDValue tmp2 = N->getOperand(rev?0:1);
 331       SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2);
 332       if (inv)
 333         cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl,
 334                                      MVT::f64, SDValue(cmp, 0),
 335                                      CurDAG->getRegister(Alpha::F31, MVT::f64));
 336       switch(CC) {
 337       case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
 338       case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
 339        {
 340          SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64,
 341                                                tmp1, tmp2);
 342          cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64,
 343                                       SDValue(cmp2, 0), SDValue(cmp, 0));
 344          break;
 345        }
 346       default: break;
 347       }
 348
 349       SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl,
 350                                           MVT::i64, SDValue(cmp, 0));
 351       return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64,
 352                                     CurDAG->getRegister(Alpha::R31, MVT::i64),
 353                                     SDValue(LD,0));
 354     }
 355     break;
 356
 357   case ISD::AND: {
 358     ConstantSDNode* SC = NULL;
 359     ConstantSDNode* MC = NULL;
 360     if (N->getOperand(0).getOpcode() == ISD::SRL &&
 361         (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
 362         (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
 363       uint64_t sval = SC->getZExtValue();
 364       uint64_t mval = MC->getZExtValue();
 365       // If the result is a zap, let the autogened stuff handle it.
 366       if (get_zapImm(N->getOperand(0), mval))
 367         break;
 368       // given mask X, and shift S, we want to see if there is any zap in the
 369       // mask if we play around with the botton S bits
 370       uint64_t dontcare = (~0ULL) >> (64 - sval);
 371       uint64_t mask = mval << sval;
 372
 373       if (get_zapImm(mask | dontcare))
 374         mask = mask | dontcare;
 375
 376       if (get_zapImm(mask)) {
 377         SDValue Z =
 378           SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64,
 379                                          N->getOperand(0).getOperand(0),
 380                                          getI64Imm(get_zapImm(mask))), 0);
 381         return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z,
 382                                       getI64Imm(sval));
 383       }
 384     }
 385     break;
 386   }
 387
 388   }
 389
 390   return SelectCode(N);
 391 }
 392
 393 void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
 394   //TODO: add flag stuff to prevent nondeturministic breakage!
 395
 396   SDValue Chain = N->getOperand(0);
 397   SDValue Addr = N->getOperand(1);
 398   SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
 399   DebugLoc dl = N->getDebugLoc();
 400
 401    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
 402      SDValue GOT = SDValue(getGlobalBaseReg(), 0);
 403      Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
 404      InFlag = Chain.getValue(1);
 405      Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other,
 406                                             MVT::Glue, Addr.getOperand(0),
 407                                             Chain, InFlag), 0);
 408    } else {
 409      Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
 410      InFlag = Chain.getValue(1);
 411      Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other,
 412                                             MVT::Glue, Chain, InFlag), 0);
 413    }
 414    InFlag = Chain.getValue(1);
 415
 416   ReplaceUses(SDValue(N, 0), Chain);
 417   ReplaceUses(SDValue(N, 1), InFlag);
 418 }
 419
 420
 421 /// createAlphaISelDag - This pass converts a legalized DAG into a
 422 /// Alpha-specific DAG, ready for instruction scheduling.
 423 ///
 424 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
 425   return new AlphaDAGToDAGISel(TM);
 426 }