lib/Target/Blackfin/BlackfinISelLowering.cpp

   1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the interfaces that Blackfin uses to lower LLVM code
  11 // into a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "BlackfinISelLowering.h"
  16 #include "BlackfinTargetMachine.h"
  17 #include "llvm/Function.h"
  18 #include "llvm/Type.h"
  19 #include "llvm/CodeGen/CallingConvLower.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/CodeGen/PseudoSourceValue.h"
  25 #include "llvm/CodeGen/SelectionDAG.h"
  26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  27 #include "llvm/ADT/VectorExtras.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 using namespace llvm;
  31
  32 //===----------------------------------------------------------------------===//
  33 // Calling Convention Implementation
  34 //===----------------------------------------------------------------------===//
  35
  36 #include "BlackfinGenCallingConv.inc"
  37
  38 //===----------------------------------------------------------------------===//
  39 // TargetLowering Implementation
  40 //===----------------------------------------------------------------------===//
  41
  42 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
  43   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
  44   setBooleanContents(ZeroOrOneBooleanContent);
  45   setStackPointerRegisterToSaveRestore(BF::SP);
  46   setIntDivIsCheap(false);
  47
  48   // Set up the legal register classes.
  49   addRegisterClass(MVT::i32, BF::DRegisterClass);
  50   addRegisterClass(MVT::i16, BF::D16RegisterClass);
  51
  52   computeRegisterProperties();
  53
  54   // Blackfin doesn't have i1 loads or stores
  55   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
  56   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  57   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  58
  59   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
  60   setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
  61
  62   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  63   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
  64   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
  65
  66   // i16 registers don't do much
  67   setOperationAction(ISD::AND,   MVT::i16, Promote);
  68   setOperationAction(ISD::OR,    MVT::i16, Promote);
  69   setOperationAction(ISD::XOR,   MVT::i16, Promote);
  70   setOperationAction(ISD::CTPOP, MVT::i16, Promote);
  71   // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
  72   // immediately.
  73   setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
  74   setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
  75   setOperationAction(ISD::SETCC, MVT::i16, Promote);
  76
  77   // Blackfin has no division
  78   setOperationAction(ISD::SDIV,    MVT::i16, Expand);
  79   setOperationAction(ISD::SDIV,    MVT::i32, Expand);
  80   setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
  81   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  82   setOperationAction(ISD::SREM,    MVT::i16, Expand);
  83   setOperationAction(ISD::SREM,    MVT::i32, Expand);
  84   setOperationAction(ISD::UDIV,    MVT::i16, Expand);
  85   setOperationAction(ISD::UDIV,    MVT::i32, Expand);
  86   setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
  87   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  88   setOperationAction(ISD::UREM,    MVT::i16, Expand);
  89   setOperationAction(ISD::UREM,    MVT::i32, Expand);
  90
  91   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  92   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
  93   setOperationAction(ISD::MULHU,     MVT::i32, Expand);
  94   setOperationAction(ISD::MULHS,     MVT::i32, Expand);
  95
  96   // No carry-in operations.
  97   setOperationAction(ISD::ADDE, MVT::i32, Custom);
  98   setOperationAction(ISD::SUBE, MVT::i32, Custom);
  99
 100   // Blackfin has no intrinsics for these particular operations.
 101   setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
 102   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 103
 104   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
 105   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 106   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 107
 108   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 109
 110   // i32 has native CTPOP, but not CTLZ/CTTZ
 111   setOperationAction(ISD::CTLZ, MVT::i32, Expand);
 112   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
 113
 114   // READCYCLECOUNTER needs special type legalization.
 115   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
 116
 117   setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
 118
 119   // Use the default implementation.
 120   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 121   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 122   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
 123   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 124
 125   setMinFunctionAlignment(2);
 126 }
 127
 128 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
 129   switch (Opcode) {
 130   default: return 0;
 131   case BFISD::CALL:     return "BFISD::CALL";
 132   case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
 133   case BFISD::Wrapper:  return "BFISD::Wrapper";
 134   }
 135 }
 136
 137 MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
 138   // SETCC always sets the CC register. Technically that is an i1 register, but
 139   // that type is not legal, so we treat it as an i32 register.
 140   return MVT::i32;
 141 }
 142
 143 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
 144                                                    SelectionDAG &DAG) const {
 145   DebugLoc DL = Op.getDebugLoc();
 146   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 147
 148   Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
 149   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 150 }
 151
 152 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
 153                                                SelectionDAG &DAG) const {
 154   DebugLoc DL = Op.getDebugLoc();
 155   int JTI = cast<JumpTableSDNode>(Op)->getIndex();
 156
 157   Op = DAG.getTargetJumpTable(JTI, MVT::i32);
 158   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 159 }
 160
 161 SDValue
 162 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
 163                                              CallingConv::ID CallConv, bool isVarArg,
 164                                             const SmallVectorImpl<ISD::InputArg>
 165                                                &Ins,
 166                                              DebugLoc dl, SelectionDAG &DAG,
 167                                              SmallVectorImpl<SDValue> &InVals)
 168                                                const {
 169
 170   MachineFunction &MF = DAG.getMachineFunction();
 171   MachineFrameInfo *MFI = MF.getFrameInfo();
 172
 173   SmallVector<CCValAssign, 16> ArgLocs;
 174   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 175                  getTargetMachine(), ArgLocs, *DAG.getContext());
 176   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 177   CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
 178
 179   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 180     CCValAssign &VA = ArgLocs[i];
 181
 182     if (VA.isRegLoc()) {
 183       EVT RegVT = VA.getLocVT();
 184       TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
 185         BF::PRegisterClass : BF::DRegisterClass;
 186       assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
 187       assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
 188
 189       unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
 190       MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
 191       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
 192
 193       // If this is an 8 or 16-bit value, it is really passed promoted to 32
 194       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
 195       // right size.
 196       if (VA.getLocInfo() == CCValAssign::SExt)
 197         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 198                                DAG.getValueType(VA.getValVT()));
 199       else if (VA.getLocInfo() == CCValAssign::ZExt)
 200         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 201                                DAG.getValueType(VA.getValVT()));
 202
 203       if (VA.getLocInfo() != CCValAssign::Full)
 204         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 205
 206       InVals.push_back(ArgValue);
 207     } else {
 208       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 209       unsigned ObjSize = VA.getLocVT().getStoreSize();
 210       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 211       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 212       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
 213                                    MachinePointerInfo(),
 214                                    false, false, 0));
 215     }
 216   }
 217
 218   return Chain;
 219 }
 220
 221 SDValue
 222 BlackfinTargetLowering::LowerReturn(SDValue Chain,
 223                                     CallingConv::ID CallConv, bool isVarArg,
 224                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 225                                     const SmallVectorImpl<SDValue> &OutVals,
 226                                     DebugLoc dl, SelectionDAG &DAG) const {
 227
 228   // CCValAssign - represent the assignment of the return value to locations.
 229   SmallVector<CCValAssign, 16> RVLocs;
 230
 231   // CCState - Info about the registers and stack slot.
 232   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 233                  DAG.getTarget(), RVLocs, *DAG.getContext());
 234
 235   // Analize return values.
 236   CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
 237
 238   // If this is the first return lowered for this function, add the regs to the
 239   // liveout set for the function.
 240   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 241     for (unsigned i = 0; i != RVLocs.size(); ++i)
 242       DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 243   }
 244
 245   SDValue Flag;
 246
 247   // Copy the result values into the output registers.
 248   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 249     CCValAssign &VA = RVLocs[i];
 250     assert(VA.isRegLoc() && "Can only return in registers!");
 251     SDValue Opi = OutVals[i];
 252
 253     // Expand to i32 if necessary
 254     switch (VA.getLocInfo()) {
 255     default: llvm_unreachable("Unknown loc info!");
 256     case CCValAssign::Full: break;
 257     case CCValAssign::SExt:
 258       Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
 259       break;
 260     case CCValAssign::ZExt:
 261       Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
 262       break;
 263     case CCValAssign::AExt:
 264       Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
 265       break;
 266     }
 267     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
 268     // Guarantee that all emitted copies are stuck together with flags.
 269     Flag = Chain.getValue(1);
 270   }
 271
 272   if (Flag.getNode()) {
 273     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 274   } else {
 275     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
 276   }
 277 }
 278
 279 SDValue
 280 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
 281                                   CallingConv::ID CallConv, bool isVarArg,
 282                                   bool &isTailCall,
 283                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 284                                   const SmallVectorImpl<SDValue> &OutVals,
 285                                   const SmallVectorImpl<ISD::InputArg> &Ins,
 286                                   DebugLoc dl, SelectionDAG &DAG,
 287                                   SmallVectorImpl<SDValue> &InVals) const {
 288   // Blackfin target does not yet support tail call optimization.
 289   isTailCall = false;
 290
 291   // Analyze operands of the call, assigning locations to each operand.
 292   SmallVector<CCValAssign, 16> ArgLocs;
 293   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 294                  DAG.getTarget(), ArgLocs, *DAG.getContext());
 295   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 296   CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
 297
 298   // Get the size of the outgoing arguments stack space requirement.
 299   unsigned ArgsSize = CCInfo.getNextStackOffset();
 300
 301   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
 302   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
 303   SmallVector<SDValue, 8> MemOpChains;
 304
 305   // Walk the register/memloc assignments, inserting copies/loads.
 306   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 307     CCValAssign &VA = ArgLocs[i];
 308     SDValue Arg = OutVals[i];
 309
 310     // Promote the value if needed.
 311     switch (VA.getLocInfo()) {
 312     default: llvm_unreachable("Unknown loc info!");
 313     case CCValAssign::Full: break;
 314     case CCValAssign::SExt:
 315       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 316       break;
 317     case CCValAssign::ZExt:
 318       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 319       break;
 320     case CCValAssign::AExt:
 321       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 322       break;
 323     }
 324
 325     // Arguments that can be passed on register must be kept at
 326     // RegsToPass vector
 327     if (VA.isRegLoc()) {
 328       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 329     } else {
 330       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 331       int Offset = VA.getLocMemOffset();
 332       assert(Offset%4 == 0 && "Unaligned LocMemOffset");
 333       assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
 334       SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
 335       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
 336       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
 337       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
 338                                          MachinePointerInfo(),false, false, 0));
 339     }
 340   }
 341
 342   // Transform all store nodes into one single node because
 343   // all store nodes are independent of each other.
 344   if (!MemOpChains.empty())
 345     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 346                         &MemOpChains[0], MemOpChains.size());
 347
 348   // Build a sequence of copy-to-reg nodes chained together with token
 349   // chain and flag operands which copy the outgoing args into registers.
 350   // The InFlag in necessary since all emitted instructions must be
 351   // stuck together.
 352   SDValue InFlag;
 353   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 354     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 355                              RegsToPass[i].second, InFlag);
 356     InFlag = Chain.getValue(1);
 357   }
 358
 359   // If the callee is a GlobalAddress node (quite common, every direct call is)
 360   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 361   // Likewise ExternalSymbol -> TargetExternalSymbol.
 362   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 363     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
 364   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 365     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
 366
 367   std::vector<EVT> NodeTys;
 368   NodeTys.push_back(MVT::Other);   // Returns a chain
 369   NodeTys.push_back(MVT::Glue);    // Returns a flag for retval copy to use.
 370   SDValue Ops[] = { Chain, Callee, InFlag };
 371   Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
 372                       InFlag.getNode() ? 3 : 2);
 373   InFlag = Chain.getValue(1);
 374
 375   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
 376                              DAG.getIntPtrConstant(0, true), InFlag);
 377   InFlag = Chain.getValue(1);
 378
 379   // Assign locations to each value returned by this call.
 380   SmallVector<CCValAssign, 16> RVLocs;
 381   CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 382                  DAG.getTarget(), RVLocs, *DAG.getContext());
 383
 384   RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
 385
 386   // Copy all of the result registers out of their specified physreg.
 387   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 388     CCValAssign &RV = RVLocs[i];
 389     unsigned Reg = RV.getLocReg();
 390
 391     Chain = DAG.getCopyFromReg(Chain, dl, Reg,
 392                                RVLocs[i].getLocVT(), InFlag);
 393     SDValue Val = Chain.getValue(0);
 394     InFlag = Chain.getValue(2);
 395     Chain = Chain.getValue(1);
 396
 397     // Callee is responsible for extending any i16 return values.
 398     switch (RV.getLocInfo()) {
 399     case CCValAssign::SExt:
 400       Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
 401                         DAG.getValueType(RV.getValVT()));
 402       break;
 403     case CCValAssign::ZExt:
 404       Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
 405                         DAG.getValueType(RV.getValVT()));
 406       break;
 407     default:
 408       break;
 409     }
 410
 411     // Truncate to valtype
 412     if (RV.getLocInfo() != CCValAssign::Full)
 413       Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
 414     InVals.push_back(Val);
 415   }
 416
 417   return Chain;
 418 }
 419
 420 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
 421 // add-with-carry instructions.
 422 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
 423   // Operands: lhs, rhs, carry-in (AC0 flag)
 424   // Results: sum, carry-out (AC0 flag)
 425   DebugLoc dl = Op.getDebugLoc();
 426
 427   unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
 428
 429   // zext incoming carry flag in AC0 to 32 bits
 430   SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 431                                        /* flag= */ Op.getOperand(2));
 432   CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
 433                                SDValue(CarryIn, 0));
 434
 435   // Add operands, produce sum and carry flag
 436   SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
 437                                    Op.getOperand(0), Op.getOperand(1));
 438
 439   // Store intermediate carry from Sum
 440   SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 441                                       /* flag= */ SDValue(Sum, 1));
 442
 443   // Add incoming carry, again producing an output flag
 444   Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
 445                            SDValue(Sum, 0), SDValue(CarryIn, 0));
 446
 447   // Update AC0 with the intermediate carry, producing a flag.
 448   SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Glue,
 449                                         SDValue(Carry1, 0));
 450
 451   // Compose (i32, flag) pair
 452   SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
 453   return DAG.getMergeValues(ops, 2, dl);
 454 }
 455
 456 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
 457                                                SelectionDAG &DAG) const {
 458   switch (Op.getOpcode()) {
 459   default:
 460     Op.getNode()->dump();
 461     llvm_unreachable("Should not custom lower this!");
 462   case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
 463   case ISD::GlobalTLSAddress:
 464     llvm_unreachable("TLS not implemented for Blackfin.");
 465   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
 466     // Frame & Return address.  Currently unimplemented
 467   case ISD::FRAMEADDR:          return SDValue();
 468   case ISD::RETURNADDR:         return SDValue();
 469   case ISD::ADDE:
 470   case ISD::SUBE:               return LowerADDE(Op, DAG);
 471   }
 472 }
 473
 474 void
 475 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
 476                                            SmallVectorImpl<SDValue> &Results,
 477                                            SelectionDAG &DAG) const {
 478   DebugLoc dl = N->getDebugLoc();
 479   switch (N->getOpcode()) {
 480   default:
 481     llvm_unreachable("Do not know how to custom type legalize this operation!");
 482     return;
 483   case ISD::READCYCLECOUNTER: {
 484     // The low part of the cycle counter is in CYCLES, the high part in
 485     // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
 486     // CYCLES2 last.
 487     SDValue TheChain = N->getOperand(0);
 488     SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
 489     SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
 490     // Use a buildpair to merge the two 32-bit values into a 64-bit one.
 491     Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
 492     // Outgoing chain. If we were to use the chain from lo instead, it would be
 493     // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
 494     // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
 495     // read beyond the next CYCLES read, leading to invalid results.
 496     Results.push_back(hi.getValue(1));
 497     return;
 498   }
 499   }
 500 }
 501
 502 //===----------------------------------------------------------------------===//
 503 //                         Blackfin Inline Assembly Support
 504 //===----------------------------------------------------------------------===//
 505
 506 /// getConstraintType - Given a constraint letter, return the type of
 507 /// constraint it is for this target.
 508 BlackfinTargetLowering::ConstraintType
 509 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
 510   if (Constraint.size() != 1)
 511     return TargetLowering::getConstraintType(Constraint);
 512
 513   switch (Constraint[0]) {
 514     // Standard constraints
 515   case 'r':
 516     return C_RegisterClass;
 517
 518     // Blackfin-specific constraints
 519   case 'a':
 520   case 'd':
 521   case 'z':
 522   case 'D':
 523   case 'W':
 524   case 'e':
 525   case 'b':
 526   case 'v':
 527   case 'f':
 528   case 'c':
 529   case 't':
 530   case 'u':
 531   case 'k':
 532   case 'x':
 533   case 'y':
 534   case 'w':
 535     return C_RegisterClass;
 536   case 'A':
 537   case 'B':
 538   case 'C':
 539   case 'Z':
 540   case 'Y':
 541     return C_Register;
 542   }
 543
 544   // Not implemented: q0-q7, qA. Use {R2} etc instead
 545
 546   return TargetLowering::getConstraintType(Constraint);
 547 }
 548
 549 /// Examine constraint type and operand type and determine a weight value.
 550 /// This object must already have been set up with the operand type
 551 /// and the current alternative constraint selected.
 552 TargetLowering::ConstraintWeight
 553 BlackfinTargetLowering::getSingleConstraintMatchWeight(
 554     AsmOperandInfo &info, const char *constraint) const {
 555   ConstraintWeight weight = CW_Invalid;
 556   Value *CallOperandVal = info.CallOperandVal;
 557     // If we don't have a value, we can't do a match,
 558     // but allow it at the lowest weight.
 559   if (CallOperandVal == NULL)
 560     return CW_Default;
 561   // Look at the constraint type.
 562   switch (*constraint) {
 563   default:
 564     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
 565     break;
 566
 567     // Blackfin-specific constraints
 568   case 'a':
 569   case 'd':
 570   case 'z':
 571   case 'D':
 572   case 'W':
 573   case 'e':
 574   case 'b':
 575   case 'v':
 576   case 'f':
 577   case 'c':
 578   case 't':
 579   case 'u':
 580   case 'k':
 581   case 'x':
 582   case 'y':
 583   case 'w':
 584     return CW_Register;
 585   case 'A':
 586   case 'B':
 587   case 'C':
 588   case 'Z':
 589   case 'Y':
 590     return CW_SpecificReg;
 591   }
 592   return weight;
 593 }
 594
 595 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
 596 /// constraint.
 597 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
 598 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
 599   typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
 600   using namespace BF;
 601
 602   if (Constraint.size() != 1)
 603     return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 604
 605   switch (Constraint[0]) {
 606     // Standard constraints
 607   case 'r':
 608     return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
 609
 610     // Blackfin-specific constraints
 611   case 'a': return Pair(0U, PRegisterClass);
 612   case 'd': return Pair(0U, DRegisterClass);
 613   case 'e': return Pair(0U, AccuRegisterClass);
 614   case 'A': return Pair(A0, AccuRegisterClass);
 615   case 'B': return Pair(A1, AccuRegisterClass);
 616   case 'b': return Pair(0U, IRegisterClass);
 617   case 'v': return Pair(0U, BRegisterClass);
 618   case 'f': return Pair(0U, MRegisterClass);
 619   case 'C': return Pair(CC, JustCCRegisterClass);
 620   case 'x': return Pair(0U, GRRegisterClass);
 621   case 'w': return Pair(0U, ALLRegisterClass);
 622   case 'Z': return Pair(P3, PRegisterClass);
 623   case 'Y': return Pair(P1, PRegisterClass);
 624   case 'z': return Pair(0U, zConsRegisterClass);
 625   case 'D': return Pair(0U, DConsRegisterClass);
 626   case 'W': return Pair(0U, WConsRegisterClass);
 627   case 'c': return Pair(0U, cConsRegisterClass);
 628   case 't': return Pair(0U, tConsRegisterClass);
 629   case 'u': return Pair(0U, uConsRegisterClass);
 630   case 'k': return Pair(0U, kConsRegisterClass);
 631   case 'y': return Pair(0U, yConsRegisterClass);
 632   }
 633
 634   // Not implemented: q0-q7, qA. Use {R2} etc instead.
 635
 636   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 637 }
 638
 639 bool BlackfinTargetLowering::
 640 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
 641   // The Blackfin target isn't yet aware of offsets.
 642   return false;
 643 }