lib/Target/Mips/MipsAsmPrinter.cpp

   1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains a printer that converts from our internal representation
  11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "mips-asm-printer"
  16 #include "MipsAsmPrinter.h"
  17 #include "Mips.h"
  18 #include "MipsInstrInfo.h"
  19 #include "MipsMachineFunction.h"
  20 #include "MipsMCInstLower.h"
  21 #include "InstPrinter/MipsInstPrinter.h"
  22 #include "llvm/BasicBlock.h"
  23 #include "llvm/Instructions.h"
  24 #include "llvm/CodeGen/MachineFunctionPass.h"
  25 #include "llvm/CodeGen/MachineConstantPool.h"
  26 #include "llvm/CodeGen/MachineFrameInfo.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/MC/MCStreamer.h"
  29 #include "llvm/MC/MCAsmInfo.h"
  30 #include "llvm/MC/MCInst.h"
  31 #include "llvm/MC/MCSymbol.h"
  32 #include "llvm/Target/Mangler.h"
  33 #include "llvm/Target/TargetData.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35 #include "llvm/Target/TargetOptions.h"
  36 #include "llvm/Target/TargetRegistry.h"
  37 #include "llvm/ADT/SmallString.h"
  38 #include "llvm/ADT/StringExtras.h"
  39 #include "llvm/ADT/Twine.h"
  40 #include "llvm/Support/raw_ostream.h"
  41 #include "llvm/Analysis/DebugInfo.h"
  42
  43 using namespace llvm;
  44
  45 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
  46   SmallString<128> Str;
  47   raw_svector_ostream OS(Str);
  48
  49   if (MI->isDebugValue()) {
  50     PrintDebugValueComment(MI, OS);
  51     return;
  52   }
  53
  54   MipsMCInstLower MCInstLowering(Mang, *MF, *this);
  55   MCInst TmpInst0;
  56   MCInstLowering.Lower(MI, TmpInst0);
  57   OutStreamer.EmitInstruction(TmpInst0);
  58 }
  59
  60 //===----------------------------------------------------------------------===//
  61 //
  62 //  Mips Asm Directives
  63 //
  64 //  -- Frame directive "frame Stackpointer, Stacksize, RARegister"
  65 //  Describe the stack frame.
  66 //
  67 //  -- Mask directives "(f)mask  bitmask, offset"
  68 //  Tells the assembler which registers are saved and where.
  69 //  bitmask - contain a little endian bitset indicating which registers are
  70 //            saved on function prologue (e.g. with a 0x80000000 mask, the
  71 //            assembler knows the register 31 (RA) is saved at prologue.
  72 //  offset  - the position before stack pointer subtraction indicating where
  73 //            the first saved register on prologue is located. (e.g. with a
  74 //
  75 //  Consider the following function prologue:
  76 //
  77 //    .frame  $fp,48,$ra
  78 //    .mask   0xc0000000,-8
  79 //       addiu $sp, $sp, -48
  80 //       sw $ra, 40($sp)
  81 //       sw $fp, 36($sp)
  82 //
  83 //    With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
  84 //    30 (FP) are saved at prologue. As the save order on prologue is from
  85 //    left to right, RA is saved first. A -8 offset means that after the
  86 //    stack pointer subtration, the first register in the mask (RA) will be
  87 //    saved at address 48-8=40.
  88 //
  89 //===----------------------------------------------------------------------===//
  90
  91 //===----------------------------------------------------------------------===//
  92 // Mask directives
  93 //===----------------------------------------------------------------------===//
  94
  95 // Create a bitmask with all callee saved registers for CPU or Floating Point
  96 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
  97 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
  98   // CPU and FPU Saved Registers Bitmasks
  99   unsigned CPUBitmask = 0, FPUBitmask = 0;
 100   int CPUTopSavedRegOff, FPUTopSavedRegOff;
 101
 102   // Set the CPU and FPU Bitmasks
 103   const MachineFrameInfo *MFI = MF->getFrameInfo();
 104   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 105   // size of stack area to which FP callee-saved regs are saved.
 106   unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
 107   unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
 108   unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
 109   bool HasAFGR64Reg = false;
 110   unsigned CSFPRegsSize = 0;
 111   unsigned i, e = CSI.size();
 112
 113   // Set FPU Bitmask.
 114   for (i = 0; i != e; ++i) {
 115     unsigned Reg = CSI[i].getReg();
 116     if (Mips::CPURegsRegisterClass->contains(Reg))
 117       break;
 118
 119     unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
 120     if (Mips::AFGR64RegisterClass->contains(Reg)) {
 121       FPUBitmask |= (3 << RegNum);
 122       CSFPRegsSize += AFGR64RegSize;
 123       HasAFGR64Reg = true;
 124       continue;
 125     }
 126
 127     FPUBitmask |= (1 << RegNum);
 128     CSFPRegsSize += FGR32RegSize;
 129   }
 130
 131   // Set CPU Bitmask.
 132   for (; i != e; ++i) {
 133     unsigned Reg = CSI[i].getReg();
 134     unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
 135     CPUBitmask |= (1 << RegNum);
 136   }
 137
 138   // FP Regs are saved right below where the virtual frame pointer points to.
 139   FPUTopSavedRegOff = FPUBitmask ?
 140     (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
 141
 142   // CPU Regs are saved below FP Regs.
 143   CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
 144
 145   // Print CPUBitmask
 146   O << "\t.mask \t"; printHex32(CPUBitmask, O);
 147   O << ',' << CPUTopSavedRegOff << '\n';
 148
 149   // Print FPUBitmask
 150   O << "\t.fmask\t"; printHex32(FPUBitmask, O);
 151   O << "," << FPUTopSavedRegOff << '\n';
 152 }
 153
 154 // Print a 32 bit hex number with all numbers.
 155 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
 156   O << "0x";
 157   for (int i = 7; i >= 0; i--)
 158     O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
 159 }
 160
 161 //===----------------------------------------------------------------------===//
 162 // Frame and Set directives
 163 //===----------------------------------------------------------------------===//
 164
 165 /// Frame Directive
 166 void MipsAsmPrinter::emitFrameDirective() {
 167   const TargetRegisterInfo &RI = *TM.getRegisterInfo();
 168
 169   unsigned stackReg  = RI.getFrameRegister(*MF);
 170   unsigned returnReg = RI.getRARegister();
 171   unsigned stackSize = MF->getFrameInfo()->getStackSize();
 172
 173   OutStreamer.EmitRawText("\t.frame\t$" +
 174            Twine(LowercaseString(MipsInstPrinter::getRegisterName(stackReg))) +
 175            "," + Twine(stackSize) + ",$" +
 176            Twine(LowercaseString(MipsInstPrinter::getRegisterName(returnReg))));
 177 }
 178
 179 /// Emit Set directives.
 180 const char *MipsAsmPrinter::getCurrentABIString() const {
 181   switch (Subtarget->getTargetABI()) {
 182   case MipsSubtarget::O32:  return "abi32";
 183   case MipsSubtarget::O64:  return "abiO64";
 184   case MipsSubtarget::N32:  return "abiN32";
 185   case MipsSubtarget::N64:  return "abi64";
 186   case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
 187   default: break;
 188   }
 189
 190   llvm_unreachable("Unknown Mips ABI");
 191   return NULL;
 192 }
 193
 194 void MipsAsmPrinter::EmitFunctionEntryLabel() {
 195   OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
 196   OutStreamer.EmitLabel(CurrentFnSym);
 197 }
 198
 199 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
 200 /// the first basic block in the function.
 201 void MipsAsmPrinter::EmitFunctionBodyStart() {
 202   emitFrameDirective();
 203
 204   SmallString<128> Str;
 205   raw_svector_ostream OS(Str);
 206   printSavedRegsBitmask(OS);
 207   OutStreamer.EmitRawText(OS.str());
 208 }
 209
 210 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
 211 /// the last basic block in the function.
 212 void MipsAsmPrinter::EmitFunctionBodyEnd() {
 213   // There are instruction for this macros, but they must
 214   // always be at the function end, and we can't emit and
 215   // break with BB logic.
 216   OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
 217   OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
 218   OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
 219 }
 220
 221
 222 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
 223 /// exactly one predecessor and the control transfer mechanism between
 224 /// the predecessor and this block is a fall-through.
 225 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
 226                                                        MBB) const {
 227   // The predecessor has to be immediately before this block.
 228   const MachineBasicBlock *Pred = *MBB->pred_begin();
 229
 230   // If the predecessor is a switch statement, assume a jump table
 231   // implementation, so it is not a fall through.
 232   if (const BasicBlock *bb = Pred->getBasicBlock())
 233     if (isa<SwitchInst>(bb->getTerminator()))
 234       return false;
 235
 236   // If this is a landing pad, it isn't a fall through.  If it has no preds,
 237   // then nothing falls through to it.
 238   if (MBB->isLandingPad() || MBB->pred_empty())
 239     return false;
 240
 241   // If there isn't exactly one predecessor, it can't be a fall through.
 242   MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
 243   ++PI2;
 244
 245   if (PI2 != MBB->pred_end())
 246     return false;
 247
 248   // The predecessor has to be immediately before this block.
 249   if (!Pred->isLayoutSuccessor(MBB))
 250     return false;
 251
 252   // If the block is completely empty, then it definitely does fall through.
 253   if (Pred->empty())
 254     return true;
 255
 256   // Otherwise, check the last instruction.
 257   // Check if the last terminator is an unconditional branch.
 258   MachineBasicBlock::const_iterator I = Pred->end();
 259   while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
 260
 261   return !I->getDesc().isBarrier();
 262 }
 263
 264 // Print out an operand for an inline asm expression.
 265 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
 266                                      unsigned AsmVariant,const char *ExtraCode,
 267                                      raw_ostream &O) {
 268   // Does this asm operand have a single letter operand modifier?
 269   if (ExtraCode && ExtraCode[0])
 270     return true; // Unknown modifier.
 271
 272   printOperand(MI, OpNo, O);
 273   return false;
 274 }
 275
 276 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 277                                            unsigned OpNum, unsigned AsmVariant,
 278                                            const char *ExtraCode,
 279                                            raw_ostream &O) {
 280   if (ExtraCode && ExtraCode[0])
 281      return true; // Unknown modifier.
 282
 283   const MachineOperand &MO = MI->getOperand(OpNum);
 284   assert(MO.isReg() && "unexpected inline asm memory operand");
 285   O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
 286   return false;
 287 }
 288
 289 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
 290                                   raw_ostream &O) {
 291   const MachineOperand &MO = MI->getOperand(opNum);
 292   bool closeP = false;
 293
 294   if (MO.getTargetFlags())
 295     closeP = true;
 296
 297   switch(MO.getTargetFlags()) {
 298   case MipsII::MO_GPREL:    O << "%gp_rel("; break;
 299   case MipsII::MO_GOT_CALL: O << "%call16("; break;
 300   case MipsII::MO_GOT:      O << "%got(";    break;
 301   case MipsII::MO_ABS_HI:   O << "%hi(";     break;
 302   case MipsII::MO_ABS_LO:   O << "%lo(";     break;
 303   case MipsII::MO_TLSGD:    O << "%tlsgd(";  break;
 304   case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
 305   case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
 306   case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
 307   }
 308
 309   switch (MO.getType()) {
 310     case MachineOperand::MO_Register:
 311       O << '$'
 312         << LowercaseString(MipsInstPrinter::getRegisterName(MO.getReg()));
 313       break;
 314
 315     case MachineOperand::MO_Immediate:
 316       O << MO.getImm();
 317       break;
 318
 319     case MachineOperand::MO_MachineBasicBlock:
 320       O << *MO.getMBB()->getSymbol();
 321       return;
 322
 323     case MachineOperand::MO_GlobalAddress:
 324       O << *Mang->getSymbol(MO.getGlobal());
 325       break;
 326
 327     case MachineOperand::MO_BlockAddress: {
 328       MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
 329       O << BA->getName();
 330       break;
 331     }
 332
 333     case MachineOperand::MO_ExternalSymbol:
 334       O << *GetExternalSymbolSymbol(MO.getSymbolName());
 335       break;
 336
 337     case MachineOperand::MO_JumpTableIndex:
 338       O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
 339         << '_' << MO.getIndex();
 340       break;
 341
 342     case MachineOperand::MO_ConstantPoolIndex:
 343       O << MAI->getPrivateGlobalPrefix() << "CPI"
 344         << getFunctionNumber() << "_" << MO.getIndex();
 345       if (MO.getOffset())
 346         O << "+" << MO.getOffset();
 347       break;
 348
 349     default:
 350       llvm_unreachable("<unknown operand type>");
 351   }
 352
 353   if (closeP) O << ")";
 354 }
 355
 356 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
 357                                       raw_ostream &O) {
 358   const MachineOperand &MO = MI->getOperand(opNum);
 359   if (MO.isImm())
 360     O << (unsigned short int)MO.getImm();
 361   else
 362     printOperand(MI, opNum, O);
 363 }
 364
 365 void MipsAsmPrinter::
 366 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
 367   // Load/Store memory operands -- imm($reg)
 368   // If PIC target the target is loaded as the
 369   // pattern lw $25,%call16($28)
 370   printOperand(MI, opNum+1, O);
 371   O << "(";
 372   printOperand(MI, opNum, O);
 373   O << ")";
 374 }
 375
 376 void MipsAsmPrinter::
 377 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
 378   // when using stack locations for not load/store instructions
 379   // print the same way as all normal 3 operand instructions.
 380   printOperand(MI, opNum, O);
 381   O << ", ";
 382   printOperand(MI, opNum+1, O);
 383   return;
 384 }
 385
 386 void MipsAsmPrinter::
 387 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
 388                 const char *Modifier) {
 389   const MachineOperand& MO = MI->getOperand(opNum);
 390   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
 391 }
 392
 393 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
 394   // FIXME: Use SwitchSection.
 395
 396   // Tell the assembler which ABI we are using
 397   OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
 398
 399   // TODO: handle O64 ABI
 400   if (Subtarget->isABI_EABI()) {
 401     if (Subtarget->isGP32bit())
 402       OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
 403     else
 404       OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
 405   }
 406
 407   // return to previous section
 408   OutStreamer.EmitRawText(StringRef("\t.previous"));
 409 }
 410
 411 MachineLocation
 412 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
 413   // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
 414   assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
 415   assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
 416          "Unexpected MachineOperand types");
 417   return MachineLocation(MI->getOperand(0).getReg(),
 418                          MI->getOperand(1).getImm());
 419 }
 420
 421 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
 422                                            raw_ostream &OS) {
 423   // TODO: implement
 424 }
 425
 426 // Force static initialization.
 427 static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
 428                                               unsigned SyntaxVariant,
 429                                               const MCAsmInfo &MAI) {
 430   return new MipsInstPrinter(MAI);
 431 }
 432
 433 extern "C" void LLVMInitializeMipsAsmPrinter() {
 434   RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
 435   RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
 436
 437   TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, createMipsMCInstPrinter);
 438   TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
 439                                         createMipsMCInstPrinter);
 440 }