lib/Target/PTX/generate-register-td.py

   1 #!/usr/bin/env python
   2 ##===- generate-register-td.py --------------------------------*-python-*--===##
   3 ##
   4 ##                     The LLVM Compiler Infrastructure
   5 ##
   6 ## This file is distributed under the University of Illinois Open Source
   7 ## License. See LICENSE.TXT for details.
   8 ##
   9 ##===----------------------------------------------------------------------===##
  10 ##
  11 ## This file describes the PTX register file generator.
  12 ##
  13 ##===----------------------------------------------------------------------===##
  14
  15 from sys import argv, exit, stdout
  16
  17
  18 if len(argv) != 5:
  19     print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
  20     exit(1)
  21
  22 try:
  23     num_pred  = int(argv[1])
  24     num_16bit = int(argv[2])
  25     num_32bit = int(argv[3])
  26     num_64bit = int(argv[4])
  27 except:
  28     print('ERROR: Invalid integer parameter')
  29     exit(1)
  30
  31 ## Print the register definition file
  32 td_file = open('PTXRegisterInfo.td', 'w')
  33
  34 td_file.write('''
  35 //===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
  36 //
  37 //                     The LLVM Compiler Infrastructure
  38 //
  39 // This file is distributed under the University of Illinois Open Source
  40 // License. See LICENSE.TXT for details.
  41 //
  42 //===----------------------------------------------------------------------===//
  43
  44 //===----------------------------------------------------------------------===//
  45 //  Declarations that describe the PTX register file
  46 //===----------------------------------------------------------------------===//
  47
  48 class PTXReg<string n> : Register<n> {
  49   let Namespace = "PTX";
  50 }
  51
  52 //===----------------------------------------------------------------------===//
  53 //  Registers
  54 //===----------------------------------------------------------------------===//
  55 ''')
  56
  57
  58 # Print predicate registers
  59 td_file.write('\n///===- Predicate Registers -----------------------------------------------===//\n\n')
  60 for r in range(0, num_pred):
  61     td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
  62
  63 # Print 16-bit registers
  64 td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
  65 for r in range(0, num_16bit):
  66     td_file.write('def RH%d : PTXReg<"rh%d">;\n' % (r, r))
  67
  68 # Print 32-bit registers
  69 td_file.write('\n///===- 32-Bit Registers --------------------------------------------------===//\n\n')
  70 for r in range(0, num_32bit):
  71     td_file.write('def R%d : PTXReg<"r%d">;\n' % (r, r))
  72
  73 # Print 64-bit registers
  74 td_file.write('\n///===- 64-Bit Registers --------------------------------------------------===//\n\n')
  75 for r in range(0, num_64bit):
  76     td_file.write('def RD%d : PTXReg<"rd%d">;\n' % (r, r))
  77
  78
  79 td_file.write('''
  80 //===----------------------------------------------------------------------===//
  81 //  Register classes
  82 //===----------------------------------------------------------------------===//
  83 ''')
  84
  85
  86 # Print register classes
  87
  88 td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
  89 td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
  90 td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
  91 td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
  92 td_file.write('def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
  93 td_file.write('def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
  94
  95
  96 td_file.close()
  97
  98 ## Now write the PTXCallingConv.td file
  99 td_file = open('PTXCallingConv.td', 'w')
 100
 101 # Reserve 10% of the available registers for return values, and the other 90%
 102 # for parameters
 103 num_ret_pred    = int(0.1 * num_pred)
 104 num_ret_16bit   = int(0.1 * num_16bit)
 105 num_ret_32bit   = int(0.1 * num_32bit)
 106 num_ret_64bit   = int(0.1 * num_64bit)
 107 num_param_pred  = num_pred - num_ret_pred
 108 num_param_16bit = num_16bit - num_ret_16bit
 109 num_param_32bit = num_32bit - num_ret_32bit
 110 num_param_64bit = num_64bit - num_ret_64bit
 111
 112 param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
 113 ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
 114 param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
 115 ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
 116 param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
 117 ret_regs_32bit   = ['R%d' % i for i in range(0, num_ret_32bit)]
 118 param_regs_64bit = [('RD%d' % (i+num_ret_64bit)) for i in range(0, num_param_64bit)]
 119 ret_regs_64bit   = ['RD%d' % i for i in range(0, num_ret_64bit)]
 120
 121 param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
 122 ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
 123 param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
 124 ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
 125 param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
 126 ret_list_32bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_32bit)
 127 param_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_64bit)
 128 ret_list_64bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_64bit)
 129
 130 td_file.write('''
 131 //===--- PTXCallingConv.td - Calling Conventions -----------*- tablegen -*-===//
 132 //
 133 //                     The LLVM Compiler Infrastructure
 134 //
 135 // This file is distributed under the University of Illinois Open Source
 136 // License. See LICENSE.TXT for details.
 137 //
 138 //===----------------------------------------------------------------------===//
 139 //
 140 // This describes the calling conventions for the PTX architecture.
 141 //
 142 //===----------------------------------------------------------------------===//
 143
 144 // PTX Formal Parameter Calling Convention
 145 def CC_PTX : CallingConv<[
 146   CCIfType<[i1],      CCAssignToReg<[%s]>>,
 147   CCIfType<[i16],     CCAssignToReg<[%s]>>,
 148   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
 149   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
 150 ]>;
 151
 152 // PTX Return Value Calling Convention
 153 def RetCC_PTX : CallingConv<[
 154   CCIfType<[i1],      CCAssignToReg<[%s]>>,
 155   CCIfType<[i16],     CCAssignToReg<[%s]>>,
 156   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
 157   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
 158 ]>;
 159 ''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
 160        ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
 161
 162
 163 td_file.close()