lib/Target/Sparc/SparcRegisterInfo.cpp

   1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Sparc.h"
  15 #include "SparcRegisterInfo.h"
  16 #include "SparcSubtarget.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23 #include "llvm/Type.h"
  24 #include "llvm/ADT/BitVector.h"
  25 #include "llvm/ADT/STLExtras.h"
  26
  27 #define GET_REGINFO_MC_DESC
  28 #define GET_REGINFO_TARGET_DESC
  29 #include "SparcGenRegisterInfo.inc"
  30
  31 using namespace llvm;
  32
  33 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
  34                                      const TargetInstrInfo &tii)
  35   : SparcGenRegisterInfo(), Subtarget(st), TII(tii) {
  36 }
  37
  38 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  39                                                                          const {
  40   static const unsigned CalleeSavedRegs[] = { 0 };
  41   return CalleeSavedRegs;
  42 }
  43
  44 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  45   BitVector Reserved(getNumRegs());
  46   // FIXME: G1 reserved for now for large imm generation by frame code.
  47   Reserved.set(SP::G1);
  48   Reserved.set(SP::G2);
  49   Reserved.set(SP::G3);
  50   Reserved.set(SP::G4);
  51   Reserved.set(SP::O6);
  52   Reserved.set(SP::I6);
  53   Reserved.set(SP::I7);
  54   Reserved.set(SP::G0);
  55   Reserved.set(SP::G5);
  56   Reserved.set(SP::G6);
  57   Reserved.set(SP::G7);
  58   return Reserved;
  59 }
  60
  61 void SparcRegisterInfo::
  62 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  63                               MachineBasicBlock::iterator I) const {
  64   MachineInstr &MI = *I;
  65   DebugLoc dl = MI.getDebugLoc();
  66   int Size = MI.getOperand(0).getImm();
  67   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
  68     Size = -Size;
  69   if (Size)
  70     BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
  71   MBB.erase(I);
  72 }
  73
  74 void
  75 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
  76                                        int SPAdj, RegScavenger *RS) const {
  77   assert(SPAdj == 0 && "Unexpected");
  78
  79   unsigned i = 0;
  80   MachineInstr &MI = *II;
  81   DebugLoc dl = MI.getDebugLoc();
  82   while (!MI.getOperand(i).isFI()) {
  83     ++i;
  84     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
  85   }
  86
  87   int FrameIndex = MI.getOperand(i).getIndex();
  88
  89   // Addressable stack objects are accessed using neg. offsets from %fp
  90   MachineFunction &MF = *MI.getParent()->getParent();
  91   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
  92                MI.getOperand(i+1).getImm();
  93
  94   // Replace frame index with a frame pointer reference.
  95   if (Offset >= -4096 && Offset <= 4095) {
  96     // If the offset is small enough to fit in the immediate field, directly
  97     // encode it.
  98     MI.getOperand(i).ChangeToRegister(SP::I6, false);
  99     MI.getOperand(i+1).ChangeToImmediate(Offset);
 100   } else {
 101     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
 102     // scavenge a register here instead of reserving G1 all of the time.
 103     unsigned OffHi = (unsigned)Offset >> 10U;
 104     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 105     // Emit G1 = G1 + I6
 106     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
 107       .addReg(SP::I6);
 108     // Insert: G1+%lo(offset) into the user.
 109     MI.getOperand(i).ChangeToRegister(SP::G1, false);
 110     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
 111   }
 112 }
 113
 114 void SparcRegisterInfo::
 115 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 116
 117 unsigned SparcRegisterInfo::getRARegister() const {
 118   return SP::I7;
 119 }
 120
 121 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 122   return SP::I6;
 123 }
 124
 125 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
 126   llvm_unreachable("What is the exception register");
 127   return 0;
 128 }
 129
 130 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
 131   llvm_unreachable("What is the exception handler register");
 132   return 0;
 133 }
 134
 135 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 136   return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 137 }
 138
 139 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
 140   return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 141 }