lib/Target/SystemZ/SystemZInstrInfo.h

   1 //===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
  15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
  16
  17 #include "SystemZ.h"
  18 #include "SystemZRegisterInfo.h"
  19 #include "llvm/ADT/IndexedMap.h"
  20 #include "llvm/Target/TargetInstrInfo.h"
  21
  22 #define GET_INSTRINFO_HEADER
  23 #include "SystemZGenInstrInfo.inc"
  24
  25 namespace llvm {
  26
  27 class SystemZTargetMachine;
  28
  29 /// SystemZII - This namespace holds all of the target specific flags that
  30 /// instruction info tracks.
  31 ///
  32 namespace SystemZII {
  33   enum {
  34     //===------------------------------------------------------------------===//
  35     // SystemZ Specific MachineOperand flags.
  36
  37     MO_NO_FLAG = 0,
  38
  39     /// MO_GOTENT - On a symbol operand this indicates that the immediate is
  40     /// the offset to the location of the symbol name from the base of the GOT.
  41     ///
  42     ///    SYMBOL_LABEL @GOTENT
  43     MO_GOTENT = 1,
  44
  45     /// MO_PLT - On a symbol operand this indicates that the immediate is
  46     /// offset to the PLT entry of symbol name from the current code location.
  47     ///
  48     ///    SYMBOL_LABEL @PLT
  49     MO_PLT = 2
  50   };
  51 }
  52
  53 class SystemZInstrInfo : public SystemZGenInstrInfo {
  54   const SystemZRegisterInfo RI;
  55   SystemZTargetMachine &TM;
  56 public:
  57   explicit SystemZInstrInfo(SystemZTargetMachine &TM);
  58
  59   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  60   /// such, whenever a client has an instance of instruction info, it should
  61   /// always be able to get register info as well (through this method).
  62   ///
  63   virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
  64
  65   virtual void copyPhysReg(MachineBasicBlock &MBB,
  66                            MachineBasicBlock::iterator I, DebugLoc DL,
  67                            unsigned DestReg, unsigned SrcReg,
  68                            bool KillSrc) const;
  69
  70   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  71   unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  72
  73   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  74                                    MachineBasicBlock::iterator MI,
  75                                    unsigned SrcReg, bool isKill,
  76                                    int FrameIndex,
  77                                    const TargetRegisterClass *RC,
  78                                    const TargetRegisterInfo *TRI) const;
  79   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  80                                     MachineBasicBlock::iterator MI,
  81                                     unsigned DestReg, int FrameIdx,
  82                                     const TargetRegisterClass *RC,
  83                                     const TargetRegisterInfo *TRI) const;
  84
  85   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  86   virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
  87   virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
  88                              MachineBasicBlock *&TBB,
  89                              MachineBasicBlock *&FBB,
  90                              SmallVectorImpl<MachineOperand> &Cond,
  91                              bool AllowModify) const;
  92   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  93                                 MachineBasicBlock *FBB,
  94                                 const SmallVectorImpl<MachineOperand> &Cond,
  95                                 DebugLoc DL) const;
  96   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  97
  98   SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
  99   SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
 100   const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
 101   const MCInstrDesc& getLongDispOpc(unsigned Opc) const;
 102
 103   const MCInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
 104     if (Offset < 0 || Offset >= 4096)
 105       return getLongDispOpc(Opc);
 106     else
 107       return get(Opc);
 108   }
 109 };
 110
 111 }
 112
 113 #endif