1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
6 %tmp1 = load <8 x i8>* %A
7 %tmp2 = load <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
12 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
15 %tmp1 = load <4 x i16>* %A
16 %tmp2 = load <4 x i16>* %B
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
21 define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
24 %tmp1 = load <2 x i32>* %A
25 %tmp2 = load <2 x i32>* %B
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
30 define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 %tmp1 = load <8 x i8>* %A
34 %tmp2 = load <8 x i8>* %B
35 %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
39 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
42 %tmp1 = load <4 x i16>* %A
43 %tmp2 = load <4 x i16>* %B
44 %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
48 define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
51 %tmp1 = load <2 x i32>* %A
52 %tmp2 = load <2 x i32>* %B
53 %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
57 define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
60 %tmp1 = load <2 x float>* %A
61 %tmp2 = load <2 x float>* %B
62 %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
66 define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
69 %tmp1 = load <16 x i8>* %A
70 %tmp2 = load <16 x i8>* %B
71 %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
75 define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
78 %tmp1 = load <8 x i16>* %A
79 %tmp2 = load <8 x i16>* %B
80 %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
84 define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
87 %tmp1 = load <4 x i32>* %A
88 %tmp2 = load <4 x i32>* %B
89 %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
93 define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
96 %tmp1 = load <16 x i8>* %A
97 %tmp2 = load <16 x i8>* %B
98 %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
102 define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
105 %tmp1 = load <8 x i16>* %A
106 %tmp2 = load <8 x i16>* %B
107 %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
111 define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
114 %tmp1 = load <4 x i32>* %A
115 %tmp2 = load <4 x i32>* %B
116 %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
120 define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
123 %tmp1 = load <4 x float>* %A
124 %tmp2 = load <4 x float>* %B
125 %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
126 ret <4 x float> %tmp3
129 declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
130 declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
131 declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
133 declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
134 declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
135 declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
137 declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
139 declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
140 declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
141 declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
143 declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
144 declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
145 declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
147 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
149 define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
152 %tmp1 = load <8 x i8>* %A
153 %tmp2 = load <8 x i8>* %B
154 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
158 define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
161 %tmp1 = load <4 x i16>* %A
162 %tmp2 = load <4 x i16>* %B
163 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
167 define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
170 %tmp1 = load <2 x i32>* %A
171 %tmp2 = load <2 x i32>* %B
172 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
176 define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
179 %tmp1 = load <8 x i8>* %A
180 %tmp2 = load <8 x i8>* %B
181 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
185 define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
188 %tmp1 = load <4 x i16>* %A
189 %tmp2 = load <4 x i16>* %B
190 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
194 define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
197 %tmp1 = load <2 x i32>* %A
198 %tmp2 = load <2 x i32>* %B
199 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
203 define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
206 %tmp1 = load <2 x float>* %A
207 %tmp2 = load <2 x float>* %B
208 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
209 ret <2 x float> %tmp3
212 define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
215 %tmp1 = load <16 x i8>* %A
216 %tmp2 = load <16 x i8>* %B
217 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
221 define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
224 %tmp1 = load <8 x i16>* %A
225 %tmp2 = load <8 x i16>* %B
226 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
230 define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
233 %tmp1 = load <4 x i32>* %A
234 %tmp2 = load <4 x i32>* %B
235 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
239 define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
242 %tmp1 = load <16 x i8>* %A
243 %tmp2 = load <16 x i8>* %B
244 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
248 define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
251 %tmp1 = load <8 x i16>* %A
252 %tmp2 = load <8 x i16>* %B
253 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
257 define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
260 %tmp1 = load <4 x i32>* %A
261 %tmp2 = load <4 x i32>* %B
262 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
266 define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
269 %tmp1 = load <4 x float>* %A
270 %tmp2 = load <4 x float>* %B
271 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
272 ret <4 x float> %tmp3
275 declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
276 declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
277 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
279 declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
280 declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
281 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
283 declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
285 declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
286 declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
287 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
289 declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
290 declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
291 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
293 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone