utils/TableGen/CodeGenRegisters.cpp

   1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines structures to encapsulate information gleaned from the
  11 // target register and register class definitions.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "CodeGenRegisters.h"
  16 #include "CodeGenTarget.h"
  17 #include "Error.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/ADT/StringExtras.h"
  20
  21 using namespace llvm;
  22
  23 //===----------------------------------------------------------------------===//
  24 //                              CodeGenRegister
  25 //===----------------------------------------------------------------------===//
  26
  27 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
  28   : TheDef(R),
  29     EnumValue(Enum),
  30     CostPerUse(R->getValueAsInt("CostPerUse")),
  31     SubRegsComplete(false)
  32 {}
  33
  34 const std::string &CodeGenRegister::getName() const {
  35   return TheDef->getName();
  36 }
  37
  38 namespace {
  39   struct Orphan {
  40     CodeGenRegister *SubReg;
  41     Record *First, *Second;
  42     Orphan(CodeGenRegister *r, Record *a, Record *b)
  43       : SubReg(r), First(a), Second(b) {}
  44   };
  45 }
  46
  47 const CodeGenRegister::SubRegMap &
  48 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
  49   // Only compute this map once.
  50   if (SubRegsComplete)
  51     return SubRegs;
  52   SubRegsComplete = true;
  53
  54   std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
  55   std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
  56   if (SubList.size() != Indices.size())
  57     throw TGError(TheDef->getLoc(), "Register " + getName() +
  58                   " SubRegIndices doesn't match SubRegs");
  59
  60   // First insert the direct subregs and make sure they are fully indexed.
  61   for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
  62     CodeGenRegister *SR = RegBank.getReg(SubList[i]);
  63     if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
  64       throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
  65                     " appears twice in Register " + getName());
  66   }
  67
  68   // Keep track of inherited subregs and how they can be reached.
  69   SmallVector<Orphan, 8> Orphans;
  70
  71   // Clone inherited subregs and place duplicate entries on Orphans.
  72   // Here the order is important - earlier subregs take precedence.
  73   for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
  74     CodeGenRegister *SR = RegBank.getReg(SubList[i]);
  75     const SubRegMap &Map = SR->getSubRegs(RegBank);
  76
  77     // Add this as a super-register of SR now all sub-registers are in the list.
  78     // This creates a topological ordering, the exact order depends on the
  79     // order getSubRegs is called on all registers.
  80     SR->SuperRegs.push_back(this);
  81
  82     for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
  83          ++SI) {
  84       if (!SubRegs.insert(*SI).second)
  85         Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
  86
  87       // Noop sub-register indexes are possible, so avoid duplicates.
  88       if (SI->second != SR)
  89         SI->second->SuperRegs.push_back(this);
  90     }
  91   }
  92
  93   // Process the composites.
  94   ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
  95   for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
  96     DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
  97     if (!Pat)
  98       throw TGError(TheDef->getLoc(), "Invalid dag '" +
  99                     Comps->getElement(i)->getAsString() +
 100                     "' in CompositeIndices");
 101     DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
 102     if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
 103       throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
 104                     Pat->getAsString());
 105
 106     // Resolve list of subreg indices into R2.
 107     CodeGenRegister *R2 = this;
 108     for (DagInit::const_arg_iterator di = Pat->arg_begin(),
 109          de = Pat->arg_end(); di != de; ++di) {
 110       DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
 111       if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
 112         throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
 113                       Pat->getAsString());
 114       const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
 115       SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
 116       if (ni == R2Subs.end())
 117         throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
 118                       " refers to bad index in " + R2->getName());
 119       R2 = ni->second;
 120     }
 121
 122     // Insert composite index. Allow overriding inherited indices etc.
 123     SubRegs[BaseIdxInit->getDef()] = R2;
 124
 125     // R2 is no longer an orphan.
 126     for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
 127       if (Orphans[j].SubReg == R2)
 128           Orphans[j].SubReg = 0;
 129   }
 130
 131   // Now Orphans contains the inherited subregisters without a direct index.
 132   // Create inferred indexes for all missing entries.
 133   for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
 134     Orphan &O = Orphans[i];
 135     if (!O.SubReg)
 136       continue;
 137     SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
 138       O.SubReg;
 139   }
 140   return SubRegs;
 141 }
 142
 143 void
 144 CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
 145   assert(SubRegsComplete && "Must precompute sub-registers");
 146   std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
 147   for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
 148     CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
 149     if (OSet.insert(SR))
 150       SR->addSubRegsPreOrder(OSet);
 151   }
 152 }
 153
 154 //===----------------------------------------------------------------------===//
 155 //                               RegisterTuples
 156 //===----------------------------------------------------------------------===//
 157
 158 // A RegisterTuples def is used to generate pseudo-registers from lists of
 159 // sub-registers. We provide a SetTheory expander class that returns the new
 160 // registers.
 161 namespace {
 162 struct TupleExpander : SetTheory::Expander {
 163   void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
 164     std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
 165     unsigned Dim = Indices.size();
 166     ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
 167     if (Dim != SubRegs->getSize())
 168       throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
 169     if (Dim < 2)
 170       throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
 171
 172     // Evaluate the sub-register lists to be zipped.
 173     unsigned Length = ~0u;
 174     SmallVector<SetTheory::RecSet, 4> Lists(Dim);
 175     for (unsigned i = 0; i != Dim; ++i) {
 176       ST.evaluate(SubRegs->getElement(i), Lists[i]);
 177       Length = std::min(Length, unsigned(Lists[i].size()));
 178     }
 179
 180     if (Length == 0)
 181       return;
 182
 183     // Precompute some types.
 184     Record *RegisterCl = Def->getRecords().getClass("Register");
 185     RecTy *RegisterRecTy = new RecordRecTy(RegisterCl);
 186     StringInit *BlankName = new StringInit("");
 187
 188     // Zip them up.
 189     for (unsigned n = 0; n != Length; ++n) {
 190       std::string Name;
 191       Record *Proto = Lists[0][n];
 192       std::vector<Init*> Tuple;
 193       unsigned CostPerUse = 0;
 194       for (unsigned i = 0; i != Dim; ++i) {
 195         Record *Reg = Lists[i][n];
 196         if (i) Name += '_';
 197         Name += Reg->getName();
 198         Tuple.push_back(new DefInit(Reg));
 199         CostPerUse = std::max(CostPerUse,
 200                               unsigned(Reg->getValueAsInt("CostPerUse")));
 201       }
 202
 203       // Create a new Record representing the synthesized register. This record
 204       // is only for consumption by CodeGenRegister, it is not added to the
 205       // RecordKeeper.
 206       Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
 207       Elts.insert(NewReg);
 208
 209       // Copy Proto super-classes.
 210       for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
 211         NewReg->addSuperClass(Proto->getSuperClasses()[i]);
 212
 213       // Copy Proto fields.
 214       for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
 215         RecordVal RV = Proto->getValues()[i];
 216
 217         // Replace the sub-register list with Tuple.
 218         if (RV.getName() == "SubRegs")
 219           RV.setValue(new ListInit(Tuple, RegisterRecTy));
 220
 221         // Provide a blank AsmName. MC hacks are required anyway.
 222         if (RV.getName() == "AsmName")
 223           RV.setValue(BlankName);
 224
 225         // CostPerUse is aggregated from all Tuple members.
 226         if (RV.getName() == "CostPerUse")
 227           RV.setValue(new IntInit(CostPerUse));
 228
 229         // Copy fields from the RegisterTuples def.
 230         if (RV.getName() == "SubRegIndices" ||
 231             RV.getName() == "CompositeIndices") {
 232           NewReg->addValue(*Def->getValue(RV.getName()));
 233           continue;
 234         }
 235
 236         // Some fields get their default uninitialized value.
 237         if (RV.getName() == "DwarfNumbers" ||
 238             RV.getName() == "DwarfAlias" ||
 239             RV.getName() == "Aliases") {
 240           if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
 241             NewReg->addValue(*DefRV);
 242           continue;
 243         }
 244
 245         // Everything else is copied from Proto.
 246         NewReg->addValue(RV);
 247       }
 248     }
 249   }
 250 };
 251 }
 252
 253 //===----------------------------------------------------------------------===//
 254 //                            CodeGenRegisterClass
 255 //===----------------------------------------------------------------------===//
 256
 257 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
 258   : TheDef(R) {
 259   // Rename anonymous register classes.
 260   if (R->getName().size() > 9 && R->getName()[9] == '.') {
 261     static unsigned AnonCounter = 0;
 262     R->setName("AnonRegClass_"+utostr(AnonCounter++));
 263   }
 264
 265   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
 266   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
 267     Record *Type = TypeList[i];
 268     if (!Type->isSubClassOf("ValueType"))
 269       throw "RegTypes list member '" + Type->getName() +
 270         "' does not derive from the ValueType class!";
 271     VTs.push_back(getValueType(Type));
 272   }
 273   assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
 274
 275   // Default allocation order always contains all registers.
 276   Elements = RegBank.getSets().expand(R);
 277   for (unsigned i = 0, e = Elements->size(); i != e; ++i)
 278     Members.insert(RegBank.getReg((*Elements)[i]));
 279
 280   // Alternative allocation orders may be subsets.
 281   ListInit *Alts = R->getValueAsListInit("AltOrders");
 282   AltOrders.resize(Alts->size());
 283   SetTheory::RecSet Order;
 284   for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
 285     RegBank.getSets().evaluate(Alts->getElement(i), Order);
 286     AltOrders[i].append(Order.begin(), Order.end());
 287     // Verify that all altorder members are regclass members.
 288     while (!Order.empty()) {
 289       CodeGenRegister *Reg = RegBank.getReg(Order.back());
 290       Order.pop_back();
 291       if (!contains(Reg))
 292         throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
 293                       " is not a class member");
 294     }
 295   }
 296
 297   // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
 298   ListInit *SRC = R->getValueAsListInit("SubRegClasses");
 299   for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
 300     DagInit *DAG = dynamic_cast<DagInit*>(*i);
 301     if (!DAG) throw "SubRegClasses must contain DAGs";
 302     DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
 303     Record *RCRec;
 304     if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
 305       throw "Operator '" + DAG->getOperator()->getAsString() +
 306         "' in SubRegClasses is not a RegisterClass";
 307     // Iterate over args, all SubRegIndex instances.
 308     for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
 309          ai != ae; ++ai) {
 310       DefInit *Idx = dynamic_cast<DefInit*>(*ai);
 311       Record *IdxRec;
 312       if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
 313         throw "Argument '" + (*ai)->getAsString() +
 314           "' in SubRegClasses is not a SubRegIndex";
 315       if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
 316         throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
 317     }
 318   }
 319
 320   // Allow targets to override the size in bits of the RegisterClass.
 321   unsigned Size = R->getValueAsInt("Size");
 322
 323   Namespace = R->getValueAsString("Namespace");
 324   SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
 325   SpillAlignment = R->getValueAsInt("Alignment");
 326   CopyCost = R->getValueAsInt("CopyCost");
 327   Allocatable = R->getValueAsBit("isAllocatable");
 328   AltOrderSelect = R->getValueAsCode("AltOrderSelect");
 329 }
 330
 331 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
 332   return Members.count(Reg);
 333 }
 334
 335 // Returns true if RC is a strict subclass.
 336 // RC is a sub-class of this class if it is a valid replacement for any
 337 // instruction operand where a register of this classis required. It must
 338 // satisfy these conditions:
 339 //
 340 // 1. All RC registers are also in this.
 341 // 2. The RC spill size must not be smaller than our spill size.
 342 // 3. RC spill alignment must be compatible with ours.
 343 //
 344 bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
 345   return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
 346     SpillSize <= RC->SpillSize &&
 347     std::includes(Members.begin(), Members.end(),
 348                   RC->Members.begin(), RC->Members.end(),
 349                   CodeGenRegister::Less());
 350 }
 351
 352 const std::string &CodeGenRegisterClass::getName() const {
 353   return TheDef->getName();
 354 }
 355
 356 //===----------------------------------------------------------------------===//
 357 //                               CodeGenRegBank
 358 //===----------------------------------------------------------------------===//
 359
 360 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
 361   // Configure register Sets to understand register classes and tuples.
 362   Sets.addFieldExpander("RegisterClass", "MemberList");
 363   Sets.addExpander("RegisterTuples", new TupleExpander());
 364
 365   // Read in the user-defined (named) sub-register indices.
 366   // More indices will be synthesized later.
 367   SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
 368   std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
 369   NumNamedIndices = SubRegIndices.size();
 370
 371   // Read in the register definitions.
 372   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
 373   std::sort(Regs.begin(), Regs.end(), LessRecord());
 374   Registers.reserve(Regs.size());
 375   // Assign the enumeration values.
 376   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
 377     getReg(Regs[i]);
 378
 379   // Expand tuples and number the new registers.
 380   std::vector<Record*> Tups =
 381     Records.getAllDerivedDefinitions("RegisterTuples");
 382   for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
 383     const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
 384     for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
 385       getReg((*TupRegs)[j]);
 386   }
 387
 388   // Read in register class definitions.
 389   std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
 390   if (RCs.empty())
 391     throw std::string("No 'RegisterClass' subclasses defined!");
 392
 393   RegClasses.reserve(RCs.size());
 394   for (unsigned i = 0, e = RCs.size(); i != e; ++i)
 395     RegClasses.push_back(CodeGenRegisterClass(*this, RCs[i]));
 396 }
 397
 398 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
 399   CodeGenRegister *&Reg = Def2Reg[Def];
 400   if (Reg)
 401     return Reg;
 402   Reg = new CodeGenRegister(Def, Registers.size() + 1);
 403   Registers.push_back(Reg);
 404   return Reg;
 405 }
 406
 407 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
 408   if (Def2RC.empty())
 409     for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
 410       Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
 411
 412   if (CodeGenRegisterClass *RC = Def2RC[Def])
 413     return RC;
 414
 415   throw TGError(Def->getLoc(), "Not a known RegisterClass!");
 416 }
 417
 418 Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
 419                                                 bool create) {
 420   // Look for an existing entry.
 421   Record *&Comp = Composite[std::make_pair(A, B)];
 422   if (Comp || !create)
 423     return Comp;
 424
 425   // None exists, synthesize one.
 426   std::string Name = A->getName() + "_then_" + B->getName();
 427   Comp = new Record(Name, SMLoc(), Records);
 428   Records.addDef(Comp);
 429   SubRegIndices.push_back(Comp);
 430   return Comp;
 431 }
 432
 433 unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
 434   std::vector<Record*>::const_iterator i =
 435     std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
 436   assert(i != SubRegIndices.end() && "Not a SubRegIndex");
 437   return (i - SubRegIndices.begin()) + 1;
 438 }
 439
 440 void CodeGenRegBank::computeComposites() {
 441   // Precompute all sub-register maps. This will create Composite entries for
 442   // all inferred sub-register indices.
 443   for (unsigned i = 0, e = Registers.size(); i != e; ++i)
 444     Registers[i]->getSubRegs(*this);
 445
 446   for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
 447     CodeGenRegister *Reg1 = Registers[i];
 448     const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
 449     for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
 450          e1 = SRM1.end(); i1 != e1; ++i1) {
 451       Record *Idx1 = i1->first;
 452       CodeGenRegister *Reg2 = i1->second;
 453       // Ignore identity compositions.
 454       if (Reg1 == Reg2)
 455         continue;
 456       const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
 457       // Try composing Idx1 with another SubRegIndex.
 458       for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
 459            e2 = SRM2.end(); i2 != e2; ++i2) {
 460         std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
 461         CodeGenRegister *Reg3 = i2->second;
 462         // Ignore identity compositions.
 463         if (Reg2 == Reg3)
 464           continue;
 465         // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
 466         for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
 467              e1d = SRM1.end(); i1d != e1d; ++i1d) {
 468           if (i1d->second == Reg3) {
 469             std::pair<CompositeMap::iterator, bool> Ins =
 470               Composite.insert(std::make_pair(IdxPair, i1d->first));
 471             // Conflicting composition? Emit a warning but allow it.
 472             if (!Ins.second && Ins.first->second != i1d->first) {
 473               errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
 474                      << " and " << getQualifiedName(IdxPair.second)
 475                      << " compose ambiguously as "
 476                      << getQualifiedName(Ins.first->second) << " or "
 477                      << getQualifiedName(i1d->first) << "\n";
 478             }
 479           }
 480         }
 481       }
 482     }
 483   }
 484
 485   // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
 486   // compositions, so remove any mappings of that form.
 487   for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
 488        i != e;) {
 489     CompositeMap::iterator j = i;
 490     ++i;
 491     if (j->first.second == j->second)
 492       Composite.erase(j);
 493   }
 494 }
 495
 496 // Compute sets of overlapping registers.
 497 //
 498 // The standard set is all super-registers and all sub-registers, but the
 499 // target description can add arbitrary overlapping registers via the 'Aliases'
 500 // field. This complicates things, but we can compute overlapping sets using
 501 // the following rules:
 502 //
 503 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
 504 //
 505 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
 506 //
 507 // Alternatively:
 508 //
 509 //    overlap(A, B) iff there exists:
 510 //    A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
 511 //    A' = B' or A' in aliases(B') or B' in aliases(A').
 512 //
 513 // Here subregs(A) is the full flattened sub-register set returned by
 514 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
 515 // description of register A.
 516 //
 517 // This also implies that registers with a common sub-register are considered
 518 // overlapping. This can happen when forming register pairs:
 519 //
 520 //    P0 = (R0, R1)
 521 //    P1 = (R1, R2)
 522 //    P2 = (R2, R3)
 523 //
 524 // In this case, we will infer an overlap between P0 and P1 because of the
 525 // shared sub-register R1. There is no overlap between P0 and P2.
 526 //
 527 void CodeGenRegBank::
 528 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
 529   assert(Map.empty());
 530
 531   // Collect overlaps that don't follow from rule 2.
 532   for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
 533     CodeGenRegister *Reg = Registers[i];
 534     CodeGenRegister::Set &Overlaps = Map[Reg];
 535
 536     // Reg overlaps itself.
 537     Overlaps.insert(Reg);
 538
 539     // All super-registers overlap.
 540     const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
 541     Overlaps.insert(Supers.begin(), Supers.end());
 542
 543     // Form symmetrical relations from the special Aliases[] lists.
 544     std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
 545     for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
 546       CodeGenRegister *Reg2 = getReg(RegList[i2]);
 547       CodeGenRegister::Set &Overlaps2 = Map[Reg2];
 548       const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
 549       // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
 550       Overlaps.insert(Reg2);
 551       Overlaps.insert(Supers2.begin(), Supers2.end());
 552       Overlaps2.insert(Reg);
 553       Overlaps2.insert(Supers.begin(), Supers.end());
 554     }
 555   }
 556
 557   // Apply rule 2. and inherit all sub-register overlaps.
 558   for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
 559     CodeGenRegister *Reg = Registers[i];
 560     CodeGenRegister::Set &Overlaps = Map[Reg];
 561     const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
 562     for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
 563          e2 = SRM.end(); i2 != e2; ++i2) {
 564       CodeGenRegister::Set &Overlaps2 = Map[i2->second];
 565       Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
 566     }
 567   }
 568 }
 569
 570 void CodeGenRegBank::computeDerivedInfo() {
 571   computeComposites();
 572 }
 573
 574 /// getRegisterClassForRegister - Find the register class that contains the
 575 /// specified physical register.  If the register is not in a register class,
 576 /// return null. If the register is in multiple classes, and the classes have a
 577 /// superset-subset relationship and the same set of types, return the
 578 /// superclass.  Otherwise return null.
 579 const CodeGenRegisterClass*
 580 CodeGenRegBank::getRegClassForRegister(Record *R) {
 581   const CodeGenRegister *Reg = getReg(R);
 582   const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
 583   const CodeGenRegisterClass *FoundRC = 0;
 584   for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
 585     const CodeGenRegisterClass &RC = RCs[i];
 586     if (!RC.contains(Reg))
 587       continue;
 588
 589     // If this is the first class that contains the register,
 590     // make a note of it and go on to the next class.
 591     if (!FoundRC) {
 592       FoundRC = &RC;
 593       continue;
 594     }
 595
 596     // If a register's classes have different types, return null.
 597     if (RC.getValueTypes() != FoundRC->getValueTypes())
 598       return 0;
 599
 600     // Check to see if the previously found class that contains
 601     // the register is a subclass of the current class. If so,
 602     // prefer the superclass.
 603     if (RC.hasSubClass(FoundRC)) {
 604       FoundRC = &RC;
 605       continue;
 606     }
 607
 608     // Check to see if the previously found class that contains
 609     // the register is a superclass of the current class. If so,
 610     // prefer the superclass.
 611     if (FoundRC->hasSubClass(&RC))
 612       continue;
 613
 614     // Multiple classes, and neither is a superclass of the other.
 615     // Return null.
 616     return 0;
 617   }
 618   return FoundRC;
 619 }