utils/TableGen/X86RecognizableInstr.cpp

   1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the X86 Disassembler Emitter.
  11 // It contains the implementation of a single recognizable instruction.
  12 // Documentation for the disassembler emitter in general can be found in
  13 //  X86DisasemblerEmitter.h.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #include "X86DisassemblerShared.h"
  18 #include "X86RecognizableInstr.h"
  19 #include "X86ModRMFilters.h"
  20
  21 #include "llvm/Support/ErrorHandling.h"
  22
  23 #include <string>
  24
  25 using namespace llvm;
  26
  27 #define MRM_MAPPING     \
  28   MAP(C1, 33)           \
  29   MAP(C2, 34)           \
  30   MAP(C3, 35)           \
  31   MAP(C4, 36)           \
  32   MAP(C8, 37)           \
  33   MAP(C9, 38)           \
  34   MAP(E8, 39)           \
  35   MAP(F0, 40)           \
  36   MAP(F8, 41)           \
  37   MAP(F9, 42)           \
  38   MAP(D0, 45)           \
  39   MAP(D1, 46)
  40
  41 // A clone of X86 since we can't depend on something that is generated.
  42 namespace X86Local {
  43   enum {
  44     Pseudo      = 0,
  45     RawFrm      = 1,
  46     AddRegFrm   = 2,
  47     MRMDestReg  = 3,
  48     MRMDestMem  = 4,
  49     MRMSrcReg   = 5,
  50     MRMSrcMem   = 6,
  51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
  52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
  53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
  54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
  55     MRMInitReg  = 32,
  56 #define MAP(from, to) MRM_##from = to,
  57     MRM_MAPPING
  58 #undef MAP
  59     RawFrmImm8  = 43,
  60     RawFrmImm16 = 44,
  61     lastMRM
  62   };
  63
  64   enum {
  65     TB  = 1,
  66     REP = 2,
  67     D8 = 3, D9 = 4, DA = 5, DB = 6,
  68     DC = 7, DD = 8, DE = 9, DF = 10,
  69     XD = 11,  XS = 12,
  70     T8 = 13,  P_TA = 14,
  71     A6 = 15,  A7 = 16
  72   };
  73 }
  74
  75 // If rows are added to the opcode extension tables, then corresponding entries
  76 // must be added here.
  77 //
  78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
  79 // that byte to ONE_BYTE_EXTENSION_TABLES.
  80 //
  81 // If the row corresponds to two bytes where the first is 0f, add an entry for
  82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
  83 //
  84 // If the row corresponds to some other set of bytes, you will need to modify
  85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
  86 // to the X86 TD files, except in two cases: if the first two bytes of such a
  87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
  88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
  89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
  90 // in RecognizableInstr::emitDecodePath().
  91
  92 #define ONE_BYTE_EXTENSION_TABLES \
  93   EXTENSION_TABLE(80)             \
  94   EXTENSION_TABLE(81)             \
  95   EXTENSION_TABLE(82)             \
  96   EXTENSION_TABLE(83)             \
  97   EXTENSION_TABLE(8f)             \
  98   EXTENSION_TABLE(c0)             \
  99   EXTENSION_TABLE(c1)             \
 100   EXTENSION_TABLE(c6)             \
 101   EXTENSION_TABLE(c7)             \
 102   EXTENSION_TABLE(d0)             \
 103   EXTENSION_TABLE(d1)             \
 104   EXTENSION_TABLE(d2)             \
 105   EXTENSION_TABLE(d3)             \
 106   EXTENSION_TABLE(f6)             \
 107   EXTENSION_TABLE(f7)             \
 108   EXTENSION_TABLE(fe)             \
 109   EXTENSION_TABLE(ff)
 110
 111 #define TWO_BYTE_EXTENSION_TABLES \
 112   EXTENSION_TABLE(00)             \
 113   EXTENSION_TABLE(01)             \
 114   EXTENSION_TABLE(18)             \
 115   EXTENSION_TABLE(71)             \
 116   EXTENSION_TABLE(72)             \
 117   EXTENSION_TABLE(73)             \
 118   EXTENSION_TABLE(ae)             \
 119   EXTENSION_TABLE(ba)             \
 120   EXTENSION_TABLE(c7)
 121
 122 using namespace X86Disassembler;
 123
 124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
 125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
 126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
 127 ///   0b11.
 128 ///
 129 /// @param form - The form of the instruction.
 130 /// @return     - true if the form implies that a ModR/M byte is required, false
 131 ///               otherwise.
 132 static bool needsModRMForDecode(uint8_t form) {
 133   if (form == X86Local::MRMDestReg    ||
 134      form == X86Local::MRMDestMem    ||
 135      form == X86Local::MRMSrcReg     ||
 136      form == X86Local::MRMSrcMem     ||
 137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
 138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
 139     return true;
 140   else
 141     return false;
 142 }
 143
 144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
 145 ///   the ModR/M byte to be 0b11.
 146 ///
 147 /// @param form - The form of the instruction.
 148 /// @return     - true if the form implies that Mod must be 0b11, false
 149 ///               otherwise.
 150 static bool isRegFormat(uint8_t form) {
 151   if (form == X86Local::MRMDestReg ||
 152      form == X86Local::MRMSrcReg  ||
 153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
 154     return true;
 155   else
 156     return false;
 157 }
 158
 159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
 160 ///   Useful for switch statements and the like.
 161 ///
 162 /// @param init - A reference to the BitsInit to be decoded.
 163 /// @return     - The field, with the first bit in the BitsInit as the lowest
 164 ///               order bit.
 165 static uint8_t byteFromBitsInit(BitsInit &init) {
 166   int width = init.getNumBits();
 167
 168   assert(width <= 8 && "Field is too large for uint8_t!");
 169
 170   int     index;
 171   uint8_t mask = 0x01;
 172
 173   uint8_t ret = 0;
 174
 175   for (index = 0; index < width; index++) {
 176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
 177       ret |= mask;
 178
 179     mask <<= 1;
 180   }
 181
 182   return ret;
 183 }
 184
 185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
 186 ///   name of the field.
 187 ///
 188 /// @param rec  - The record from which to extract the value.
 189 /// @param name - The name of the field in the record.
 190 /// @return     - The field, as translated by byteFromBitsInit().
 191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
 192   BitsInit* bits = rec->getValueAsBitsInit(name);
 193   return byteFromBitsInit(*bits);
 194 }
 195
 196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
 197                                      const CodeGenInstruction &insn,
 198                                      InstrUID uid) {
 199   UID = uid;
 200
 201   Rec = insn.TheDef;
 202   Name = Rec->getName();
 203   Spec = &tables.specForUID(UID);
 204
 205   if (!Rec->isSubClassOf("X86Inst")) {
 206     ShouldBeEmitted = false;
 207     return;
 208   }
 209
 210   Prefix   = byteFromRec(Rec, "Prefix");
 211   Opcode   = byteFromRec(Rec, "Opcode");
 212   Form     = byteFromRec(Rec, "FormBits");
 213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
 214
 215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
 216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
 217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
 218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
 219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
 220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
 221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
 222
 223   Name      = Rec->getName();
 224   AsmString = Rec->getValueAsString("AsmString");
 225
 226   Operands = &insn.Operands.OperandList;
 227
 228   IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
 229   HasFROperands    = hasFROperands();
 230   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
 231
 232   ShouldBeEmitted  = true;
 233 }
 234
 235 void RecognizableInstr::processInstr(DisassemblerTables &tables,
 236                                    const CodeGenInstruction &insn,
 237                                    InstrUID uid)
 238 {
 239   // Ignore "asm parser only" instructions.
 240   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
 241     return;
 242
 243   RecognizableInstr recogInstr(tables, insn, uid);
 244
 245   recogInstr.emitInstructionSpecifier(tables);
 246
 247   if (recogInstr.shouldBeEmitted())
 248     recogInstr.emitDecodePath(tables);
 249 }
 250
 251 InstructionContext RecognizableInstr::insnContext() const {
 252   InstructionContext insnContext;
 253
 254   if (HasVEX_4VPrefix || HasVEXPrefix) {
 255     if (HasOpSizePrefix && HasVEX_LPrefix)
 256       insnContext = IC_VEX_L_OPSIZE;
 257     else if (HasOpSizePrefix && HasVEX_WPrefix)
 258       insnContext = IC_VEX_W_OPSIZE;
 259     else if (HasOpSizePrefix)
 260       insnContext = IC_VEX_OPSIZE;
 261     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
 262       insnContext = IC_VEX_L_XS;
 263     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
 264       insnContext = IC_VEX_L_XD;
 265     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
 266       insnContext = IC_VEX_W_XS;
 267     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
 268       insnContext = IC_VEX_W_XD;
 269     else if (HasVEX_WPrefix)
 270       insnContext = IC_VEX_W;
 271     else if (HasVEX_LPrefix)
 272       insnContext = IC_VEX_L;
 273     else if (Prefix == X86Local::XD)
 274       insnContext = IC_VEX_XD;
 275     else if (Prefix == X86Local::XS)
 276       insnContext = IC_VEX_XS;
 277     else
 278       insnContext = IC_VEX;
 279   } else if (Name.find("64") != Name.npos || HasREX_WPrefix) {
 280     if (HasREX_WPrefix && HasOpSizePrefix)
 281       insnContext = IC_64BIT_REXW_OPSIZE;
 282     else if (HasOpSizePrefix)
 283       insnContext = IC_64BIT_OPSIZE;
 284     else if (HasREX_WPrefix && Prefix == X86Local::XS)
 285       insnContext = IC_64BIT_REXW_XS;
 286     else if (HasREX_WPrefix && Prefix == X86Local::XD)
 287       insnContext = IC_64BIT_REXW_XD;
 288     else if (Prefix == X86Local::XD)
 289       insnContext = IC_64BIT_XD;
 290     else if (Prefix == X86Local::XS)
 291       insnContext = IC_64BIT_XS;
 292     else if (HasREX_WPrefix)
 293       insnContext = IC_64BIT_REXW;
 294     else
 295       insnContext = IC_64BIT;
 296   } else {
 297     if (HasOpSizePrefix)
 298       insnContext = IC_OPSIZE;
 299     else if (Prefix == X86Local::XD)
 300       insnContext = IC_XD;
 301     else if (Prefix == X86Local::XS)
 302       insnContext = IC_XS;
 303     else
 304       insnContext = IC;
 305   }
 306
 307   return insnContext;
 308 }
 309
 310 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
 311   ///////////////////
 312   // FILTER_STRONG
 313   //
 314
 315   // Filter out intrinsics
 316
 317   if (!Rec->isSubClassOf("X86Inst"))
 318     return FILTER_STRONG;
 319
 320   if (Form == X86Local::Pseudo ||
 321       IsCodeGenOnly)
 322     return FILTER_STRONG;
 323
 324   if (Form == X86Local::MRMInitReg)
 325     return FILTER_STRONG;
 326
 327
 328   // TEMPORARY pending bug fixes
 329
 330   if (Name.find("VMOVDQU") != Name.npos ||
 331       Name.find("VMOVDQA") != Name.npos ||
 332       Name.find("VROUND") != Name.npos)
 333     return FILTER_STRONG;
 334
 335   // Filter out artificial instructions
 336
 337   if (Name.find("TAILJMP") != Name.npos    ||
 338       Name.find("_Int") != Name.npos       ||
 339       Name.find("_int") != Name.npos       ||
 340       Name.find("Int_") != Name.npos       ||
 341       Name.find("_NOREX") != Name.npos     ||
 342       Name.find("_TC") != Name.npos        ||
 343       Name.find("EH_RETURN") != Name.npos  ||
 344       Name.find("V_SET") != Name.npos      ||
 345       Name.find("LOCK_") != Name.npos      ||
 346       Name.find("WIN") != Name.npos        ||
 347       Name.find("_AVX") != Name.npos       ||
 348       Name.find("2SDL") != Name.npos)
 349     return FILTER_STRONG;
 350
 351   // Filter out instructions with segment override prefixes.
 352   // They're too messy to handle now and we'll special case them if needed.
 353
 354   if (SegOvr)
 355     return FILTER_STRONG;
 356
 357   // Filter out instructions that can't be printed.
 358
 359   if (AsmString.size() == 0)
 360     return FILTER_STRONG;
 361
 362   // Filter out instructions with subreg operands.
 363
 364   if (AsmString.find("subreg") != AsmString.npos)
 365     return FILTER_STRONG;
 366
 367   /////////////////
 368   // FILTER_WEAK
 369   //
 370
 371
 372   // Filter out instructions with a LOCK prefix;
 373   //   prefer forms that do not have the prefix
 374   if (HasLockPrefix)
 375     return FILTER_WEAK;
 376
 377   // Filter out alternate forms of AVX instructions
 378   if (Name.find("_alt") != Name.npos ||
 379       Name.find("XrYr") != Name.npos ||
 380       Name.find("r64r") != Name.npos ||
 381       Name.find("_64mr") != Name.npos ||
 382       Name.find("Xrr") != Name.npos ||
 383       Name.find("rr64") != Name.npos)
 384     return FILTER_WEAK;
 385
 386   if (Name == "VMASKMOVDQU64"  ||
 387       Name == "VEXTRACTPSrr64" ||
 388       Name == "VMOVQd64rr"     ||
 389       Name == "VMOVQs64rr")
 390     return FILTER_WEAK;
 391
 392   // Special cases.
 393
 394   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
 395     return FILTER_WEAK;
 396   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
 397     return FILTER_WEAK;
 398
 399   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
 400     return FILTER_WEAK;
 401   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
 402     return FILTER_WEAK;
 403   if (Name.find("Fs") != Name.npos)
 404     return FILTER_WEAK;
 405   if (Name == "MOVLPDrr"          ||
 406       Name == "MOVLPSrr"          ||
 407       Name == "PUSHFQ"            ||
 408       Name == "BSF16rr"           ||
 409       Name == "BSF16rm"           ||
 410       Name == "BSR16rr"           ||
 411       Name == "BSR16rm"           ||
 412       Name == "MOVSX16rm8"        ||
 413       Name == "MOVSX16rr8"        ||
 414       Name == "MOVZX16rm8"        ||
 415       Name == "MOVZX16rr8"        ||
 416       Name == "PUSH32i16"         ||
 417       Name == "PUSH64i16"         ||
 418       Name == "MOVPQI2QImr"       ||
 419       Name == "VMOVPQI2QImr"      ||
 420       Name == "MOVSDmr"           ||
 421       Name == "MOVSDrm"           ||
 422       Name == "MOVSSmr"           ||
 423       Name == "MOVSSrm"           ||
 424       Name == "MMX_MOVD64rrv164"  ||
 425       Name == "CRC32m16"          ||
 426       Name == "MOV64ri64i32"      ||
 427       Name == "CRC32r16")
 428     return FILTER_WEAK;
 429
 430   if (HasFROperands && Name.find("MOV") != Name.npos &&
 431      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
 432       (Name.find("to") != Name.npos)))
 433     return FILTER_WEAK;
 434
 435   return FILTER_NORMAL;
 436 }
 437
 438 bool RecognizableInstr::hasFROperands() const {
 439   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
 440   unsigned numOperands = OperandList.size();
 441
 442   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
 443     const std::string &recName = OperandList[operandIndex].Rec->getName();
 444
 445     if (recName.find("FR") != recName.npos)
 446       return true;
 447   }
 448   return false;
 449 }
 450
 451 bool RecognizableInstr::has256BitOperands() const {
 452   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
 453   unsigned numOperands = OperandList.size();
 454
 455   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
 456     const std::string &recName = OperandList[operandIndex].Rec->getName();
 457
 458     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
 459       return true;
 460     }
 461   }
 462   return false;
 463 }
 464
 465 void RecognizableInstr::handleOperand(
 466   bool optional,
 467   unsigned &operandIndex,
 468   unsigned &physicalOperandIndex,
 469   unsigned &numPhysicalOperands,
 470   unsigned *operandMapping,
 471   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
 472   if (optional) {
 473     if (physicalOperandIndex >= numPhysicalOperands)
 474       return;
 475   } else {
 476     assert(physicalOperandIndex < numPhysicalOperands);
 477   }
 478
 479   while (operandMapping[operandIndex] != operandIndex) {
 480     Spec->operands[operandIndex].encoding = ENCODING_DUP;
 481     Spec->operands[operandIndex].type =
 482       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
 483     ++operandIndex;
 484   }
 485
 486   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
 487
 488   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
 489                                                               HasOpSizePrefix);
 490   Spec->operands[operandIndex].type = typeFromString(typeName,
 491                                                      IsSSE,
 492                                                      HasREX_WPrefix,
 493                                                      HasOpSizePrefix);
 494
 495   ++operandIndex;
 496   ++physicalOperandIndex;
 497 }
 498
 499 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
 500   Spec->name       = Name;
 501
 502   if (!Rec->isSubClassOf("X86Inst"))
 503     return;
 504
 505   switch (filter()) {
 506   case FILTER_WEAK:
 507     Spec->filtered = true;
 508     break;
 509   case FILTER_STRONG:
 510     ShouldBeEmitted = false;
 511     return;
 512   case FILTER_NORMAL:
 513     break;
 514   }
 515
 516   Spec->insnContext = insnContext();
 517
 518   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
 519
 520   unsigned operandIndex;
 521   unsigned numOperands = OperandList.size();
 522   unsigned numPhysicalOperands = 0;
 523
 524   // operandMapping maps from operands in OperandList to their originals.
 525   // If operandMapping[i] != i, then the entry is a duplicate.
 526   unsigned operandMapping[X86_MAX_OPERANDS];
 527
 528   bool hasFROperands = false;
 529
 530   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
 531
 532   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
 533     if (OperandList[operandIndex].Constraints.size()) {
 534       const CGIOperandList::ConstraintInfo &Constraint =
 535         OperandList[operandIndex].Constraints[0];
 536       if (Constraint.isTied()) {
 537         operandMapping[operandIndex] = Constraint.getTiedOperand();
 538       } else {
 539         ++numPhysicalOperands;
 540         operandMapping[operandIndex] = operandIndex;
 541       }
 542     } else {
 543       ++numPhysicalOperands;
 544       operandMapping[operandIndex] = operandIndex;
 545     }
 546
 547     const std::string &recName = OperandList[operandIndex].Rec->getName();
 548
 549     if (recName.find("FR") != recName.npos)
 550       hasFROperands = true;
 551   }
 552
 553   if (hasFROperands && Name.find("MOV") != Name.npos &&
 554      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
 555       (Name.find("to") != Name.npos)))
 556     ShouldBeEmitted = false;
 557
 558   if (!ShouldBeEmitted)
 559     return;
 560
 561 #define HANDLE_OPERAND(class)               \
 562   handleOperand(false,                      \
 563                 operandIndex,               \
 564                 physicalOperandIndex,       \
 565                 numPhysicalOperands,        \
 566                 operandMapping,             \
 567                 class##EncodingFromString);
 568
 569 #define HANDLE_OPTIONAL(class)              \
 570   handleOperand(true,                       \
 571                 operandIndex,               \
 572                 physicalOperandIndex,       \
 573                 numPhysicalOperands,        \
 574                 operandMapping,             \
 575                 class##EncodingFromString);
 576
 577   // operandIndex should always be < numOperands
 578   operandIndex = 0;
 579   // physicalOperandIndex should always be < numPhysicalOperands
 580   unsigned physicalOperandIndex = 0;
 581
 582   switch (Form) {
 583   case X86Local::RawFrm:
 584     // Operand 1 (optional) is an address or immediate.
 585     // Operand 2 (optional) is an immediate.
 586     assert(numPhysicalOperands <= 2 &&
 587            "Unexpected number of operands for RawFrm");
 588     HANDLE_OPTIONAL(relocation)
 589     HANDLE_OPTIONAL(immediate)
 590     break;
 591   case X86Local::AddRegFrm:
 592     // Operand 1 is added to the opcode.
 593     // Operand 2 (optional) is an address.
 594     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
 595            "Unexpected number of operands for AddRegFrm");
 596     HANDLE_OPERAND(opcodeModifier)
 597     HANDLE_OPTIONAL(relocation)
 598     break;
 599   case X86Local::MRMDestReg:
 600     // Operand 1 is a register operand in the R/M field.
 601     // Operand 2 is a register operand in the Reg/Opcode field.
 602     // Operand 3 (optional) is an immediate.
 603     assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
 604            "Unexpected number of operands for MRMDestRegFrm");
 605     HANDLE_OPERAND(rmRegister)
 606     HANDLE_OPERAND(roRegister)
 607     HANDLE_OPTIONAL(immediate)
 608     break;
 609   case X86Local::MRMDestMem:
 610     // Operand 1 is a memory operand (possibly SIB-extended)
 611     // Operand 2 is a register operand in the Reg/Opcode field.
 612     // Operand 3 (optional) is an immediate.
 613     assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
 614            "Unexpected number of operands for MRMDestMemFrm");
 615     HANDLE_OPERAND(memory)
 616     HANDLE_OPERAND(roRegister)
 617     HANDLE_OPTIONAL(immediate)
 618     break;
 619   case X86Local::MRMSrcReg:
 620     // Operand 1 is a register operand in the Reg/Opcode field.
 621     // Operand 2 is a register operand in the R/M field.
 622     // - In AVX, there is a register operand in the VEX.vvvv field here -
 623     // Operand 3 (optional) is an immediate.
 624
 625     if (HasVEX_4VPrefix)
 626       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
 627              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
 628     else
 629       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
 630              "Unexpected number of operands for MRMSrcRegFrm");
 631
 632     HANDLE_OPERAND(roRegister)
 633
 634     if (HasVEX_4VPrefix)
 635       // FIXME: In AVX, the register below becomes the one encoded
 636       // in ModRMVEX and the one above the one in the VEX.VVVV field
 637       HANDLE_OPERAND(vvvvRegister)
 638
 639     HANDLE_OPERAND(rmRegister)
 640     HANDLE_OPTIONAL(immediate)
 641     break;
 642   case X86Local::MRMSrcMem:
 643     // Operand 1 is a register operand in the Reg/Opcode field.
 644     // Operand 2 is a memory operand (possibly SIB-extended)
 645     // - In AVX, there is a register operand in the VEX.vvvv field here -
 646     // Operand 3 (optional) is an immediate.
 647
 648     if (HasVEX_4VPrefix)
 649       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
 650              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
 651     else
 652       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
 653              "Unexpected number of operands for MRMSrcMemFrm");
 654
 655     HANDLE_OPERAND(roRegister)
 656
 657     if (HasVEX_4VPrefix)
 658       // FIXME: In AVX, the register below becomes the one encoded
 659       // in ModRMVEX and the one above the one in the VEX.VVVV field
 660       HANDLE_OPERAND(vvvvRegister)
 661
 662     HANDLE_OPERAND(memory)
 663     HANDLE_OPTIONAL(immediate)
 664     break;
 665   case X86Local::MRM0r:
 666   case X86Local::MRM1r:
 667   case X86Local::MRM2r:
 668   case X86Local::MRM3r:
 669   case X86Local::MRM4r:
 670   case X86Local::MRM5r:
 671   case X86Local::MRM6r:
 672   case X86Local::MRM7r:
 673     // Operand 1 is a register operand in the R/M field.
 674     // Operand 2 (optional) is an immediate or relocation.
 675     if (HasVEX_4VPrefix)
 676       assert(numPhysicalOperands <= 3 &&
 677              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
 678     else
 679       assert(numPhysicalOperands <= 2 &&
 680              "Unexpected number of operands for MRMnRFrm");
 681     if (HasVEX_4VPrefix)
 682       HANDLE_OPERAND(vvvvRegister);
 683     HANDLE_OPTIONAL(rmRegister)
 684     HANDLE_OPTIONAL(relocation)
 685     break;
 686   case X86Local::MRM0m:
 687   case X86Local::MRM1m:
 688   case X86Local::MRM2m:
 689   case X86Local::MRM3m:
 690   case X86Local::MRM4m:
 691   case X86Local::MRM5m:
 692   case X86Local::MRM6m:
 693   case X86Local::MRM7m:
 694     // Operand 1 is a memory operand (possibly SIB-extended)
 695     // Operand 2 (optional) is an immediate or relocation.
 696     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
 697            "Unexpected number of operands for MRMnMFrm");
 698     HANDLE_OPERAND(memory)
 699     HANDLE_OPTIONAL(relocation)
 700     break;
 701   case X86Local::RawFrmImm8:
 702     // operand 1 is a 16-bit immediate
 703     // operand 2 is an 8-bit immediate
 704     assert(numPhysicalOperands == 2 &&
 705            "Unexpected number of operands for X86Local::RawFrmImm8");
 706     HANDLE_OPERAND(immediate)
 707     HANDLE_OPERAND(immediate)
 708     break;
 709   case X86Local::RawFrmImm16:
 710     // operand 1 is a 16-bit immediate
 711     // operand 2 is a 16-bit immediate
 712     HANDLE_OPERAND(immediate)
 713     HANDLE_OPERAND(immediate)
 714     break;
 715   case X86Local::MRMInitReg:
 716     // Ignored.
 717     break;
 718   }
 719
 720   #undef HANDLE_OPERAND
 721   #undef HANDLE_OPTIONAL
 722 }
 723
 724 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
 725   // Special cases where the LLVM tables are not complete
 726
 727 #define MAP(from, to)                     \
 728   case X86Local::MRM_##from:              \
 729     filter = new ExactFilter(0x##from);   \
 730     break;
 731
 732   OpcodeType    opcodeType  = (OpcodeType)-1;
 733
 734   ModRMFilter*  filter      = NULL;
 735   uint8_t       opcodeToSet = 0;
 736
 737   switch (Prefix) {
 738   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
 739   case X86Local::XD:
 740   case X86Local::XS:
 741   case X86Local::TB:
 742     opcodeType = TWOBYTE;
 743
 744     switch (Opcode) {
 745     default:
 746       if (needsModRMForDecode(Form))
 747         filter = new ModFilter(isRegFormat(Form));
 748       else
 749         filter = new DumbFilter();
 750       break;
 751 #define EXTENSION_TABLE(n) case 0x##n:
 752     TWO_BYTE_EXTENSION_TABLES
 753 #undef EXTENSION_TABLE
 754       switch (Form) {
 755       default:
 756         llvm_unreachable("Unhandled two-byte extended opcode");
 757       case X86Local::MRM0r:
 758       case X86Local::MRM1r:
 759       case X86Local::MRM2r:
 760       case X86Local::MRM3r:
 761       case X86Local::MRM4r:
 762       case X86Local::MRM5r:
 763       case X86Local::MRM6r:
 764       case X86Local::MRM7r:
 765         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
 766         break;
 767       case X86Local::MRM0m:
 768       case X86Local::MRM1m:
 769       case X86Local::MRM2m:
 770       case X86Local::MRM3m:
 771       case X86Local::MRM4m:
 772       case X86Local::MRM5m:
 773       case X86Local::MRM6m:
 774       case X86Local::MRM7m:
 775         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
 776         break;
 777       MRM_MAPPING
 778       } // switch (Form)
 779       break;
 780     } // switch (Opcode)
 781     opcodeToSet = Opcode;
 782     break;
 783   case X86Local::T8:
 784     opcodeType = THREEBYTE_38;
 785     if (needsModRMForDecode(Form))
 786       filter = new ModFilter(isRegFormat(Form));
 787     else
 788       filter = new DumbFilter();
 789     opcodeToSet = Opcode;
 790     break;
 791   case X86Local::P_TA:
 792     opcodeType = THREEBYTE_3A;
 793     if (needsModRMForDecode(Form))
 794       filter = new ModFilter(isRegFormat(Form));
 795     else
 796       filter = new DumbFilter();
 797     opcodeToSet = Opcode;
 798     break;
 799   case X86Local::A6:
 800     opcodeType = THREEBYTE_A6;
 801     if (needsModRMForDecode(Form))
 802       filter = new ModFilter(isRegFormat(Form));
 803     else
 804       filter = new DumbFilter();
 805     opcodeToSet = Opcode;
 806     break;
 807   case X86Local::A7:
 808     opcodeType = THREEBYTE_A7;
 809     if (needsModRMForDecode(Form))
 810       filter = new ModFilter(isRegFormat(Form));
 811     else
 812       filter = new DumbFilter();
 813     opcodeToSet = Opcode;
 814     break;
 815   case X86Local::D8:
 816   case X86Local::D9:
 817   case X86Local::DA:
 818   case X86Local::DB:
 819   case X86Local::DC:
 820   case X86Local::DD:
 821   case X86Local::DE:
 822   case X86Local::DF:
 823     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
 824     opcodeType = ONEBYTE;
 825     if (Form == X86Local::AddRegFrm) {
 826       Spec->modifierType = MODIFIER_MODRM;
 827       Spec->modifierBase = Opcode;
 828       filter = new AddRegEscapeFilter(Opcode);
 829     } else {
 830       filter = new EscapeFilter(true, Opcode);
 831     }
 832     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
 833     break;
 834   default:
 835     opcodeType = ONEBYTE;
 836     switch (Opcode) {
 837 #define EXTENSION_TABLE(n) case 0x##n:
 838     ONE_BYTE_EXTENSION_TABLES
 839 #undef EXTENSION_TABLE
 840       switch (Form) {
 841       default:
 842         llvm_unreachable("Fell through the cracks of a single-byte "
 843                          "extended opcode");
 844       case X86Local::MRM0r:
 845       case X86Local::MRM1r:
 846       case X86Local::MRM2r:
 847       case X86Local::MRM3r:
 848       case X86Local::MRM4r:
 849       case X86Local::MRM5r:
 850       case X86Local::MRM6r:
 851       case X86Local::MRM7r:
 852         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
 853         break;
 854       case X86Local::MRM0m:
 855       case X86Local::MRM1m:
 856       case X86Local::MRM2m:
 857       case X86Local::MRM3m:
 858       case X86Local::MRM4m:
 859       case X86Local::MRM5m:
 860       case X86Local::MRM6m:
 861       case X86Local::MRM7m:
 862         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
 863         break;
 864       MRM_MAPPING
 865       } // switch (Form)
 866       break;
 867     case 0xd8:
 868     case 0xd9:
 869     case 0xda:
 870     case 0xdb:
 871     case 0xdc:
 872     case 0xdd:
 873     case 0xde:
 874     case 0xdf:
 875       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
 876       break;
 877     default:
 878       if (needsModRMForDecode(Form))
 879         filter = new ModFilter(isRegFormat(Form));
 880       else
 881         filter = new DumbFilter();
 882       break;
 883     } // switch (Opcode)
 884     opcodeToSet = Opcode;
 885   } // switch (Prefix)
 886
 887   assert(opcodeType != (OpcodeType)-1 &&
 888          "Opcode type not set");
 889   assert(filter && "Filter not set");
 890
 891   if (Form == X86Local::AddRegFrm) {
 892     if(Spec->modifierType != MODIFIER_MODRM) {
 893       assert(opcodeToSet < 0xf9 &&
 894              "Not enough room for all ADDREG_FRM operands");
 895
 896       uint8_t currentOpcode;
 897
 898       for (currentOpcode = opcodeToSet;
 899            currentOpcode < opcodeToSet + 8;
 900            ++currentOpcode)
 901         tables.setTableFields(opcodeType,
 902                               insnContext(),
 903                               currentOpcode,
 904                               *filter,
 905                               UID);
 906
 907       Spec->modifierType = MODIFIER_OPCODE;
 908       Spec->modifierBase = opcodeToSet;
 909     } else {
 910       // modifierBase was set where MODIFIER_MODRM was set
 911       tables.setTableFields(opcodeType,
 912                             insnContext(),
 913                             opcodeToSet,
 914                             *filter,
 915                             UID);
 916     }
 917   } else {
 918     tables.setTableFields(opcodeType,
 919                           insnContext(),
 920                           opcodeToSet,
 921                           *filter,
 922                           UID);
 923
 924     Spec->modifierType = MODIFIER_NONE;
 925     Spec->modifierBase = opcodeToSet;
 926   }
 927
 928   delete filter;
 929
 930 #undef MAP
 931 }
 932
 933 #define TYPE(str, type) if (s == str) return type;
 934 OperandType RecognizableInstr::typeFromString(const std::string &s,
 935                                               bool isSSE,
 936                                               bool hasREX_WPrefix,
 937                                               bool hasOpSizePrefix) {
 938   if (isSSE) {
 939     // For SSE instructions, we ignore the OpSize prefix and force operand
 940     // sizes.
 941     TYPE("GR16",              TYPE_R16)
 942     TYPE("GR32",              TYPE_R32)
 943     TYPE("GR64",              TYPE_R64)
 944   }
 945   if(hasREX_WPrefix) {
 946     // For instructions with a REX_W prefix, a declared 32-bit register encoding
 947     // is special.
 948     TYPE("GR32",              TYPE_R32)
 949   }
 950   if(!hasOpSizePrefix) {
 951     // For instructions without an OpSize prefix, a declared 16-bit register or
 952     // immediate encoding is special.
 953     TYPE("GR16",              TYPE_R16)
 954     TYPE("i16imm",            TYPE_IMM16)
 955   }
 956   TYPE("i16mem",              TYPE_Mv)
 957   TYPE("i16imm",              TYPE_IMMv)
 958   TYPE("i16i8imm",            TYPE_IMMv)
 959   TYPE("GR16",                TYPE_Rv)
 960   TYPE("i32mem",              TYPE_Mv)
 961   TYPE("i32imm",              TYPE_IMMv)
 962   TYPE("i32i8imm",            TYPE_IMM32)
 963   TYPE("GR32",                TYPE_Rv)
 964   TYPE("i64mem",              TYPE_Mv)
 965   TYPE("i64i32imm",           TYPE_IMM64)
 966   TYPE("i64i8imm",            TYPE_IMM64)
 967   TYPE("GR64",                TYPE_R64)
 968   TYPE("i8mem",               TYPE_M8)
 969   TYPE("i8imm",               TYPE_IMM8)
 970   TYPE("GR8",                 TYPE_R8)
 971   TYPE("VR128",               TYPE_XMM128)
 972   TYPE("f128mem",             TYPE_M128)
 973   TYPE("f256mem",             TYPE_M256)
 974   TYPE("FR64",                TYPE_XMM64)
 975   TYPE("f64mem",              TYPE_M64FP)
 976   TYPE("sdmem",               TYPE_M64FP)
 977   TYPE("FR32",                TYPE_XMM32)
 978   TYPE("f32mem",              TYPE_M32FP)
 979   TYPE("ssmem",               TYPE_M32FP)
 980   TYPE("RST",                 TYPE_ST)
 981   TYPE("i128mem",             TYPE_M128)
 982   TYPE("i256mem",             TYPE_M256)
 983   TYPE("i64i32imm_pcrel",     TYPE_REL64)
 984   TYPE("i16imm_pcrel",        TYPE_REL16)
 985   TYPE("i32imm_pcrel",        TYPE_REL32)
 986   TYPE("SSECC",               TYPE_IMM3)
 987   TYPE("brtarget",            TYPE_RELv)
 988   TYPE("uncondbrtarget",      TYPE_RELv)
 989   TYPE("brtarget8",           TYPE_REL8)
 990   TYPE("f80mem",              TYPE_M80FP)
 991   TYPE("lea32mem",            TYPE_LEA)
 992   TYPE("lea64_32mem",         TYPE_LEA)
 993   TYPE("lea64mem",            TYPE_LEA)
 994   TYPE("VR64",                TYPE_MM64)
 995   TYPE("i64imm",              TYPE_IMMv)
 996   TYPE("opaque32mem",         TYPE_M1616)
 997   TYPE("opaque48mem",         TYPE_M1632)
 998   TYPE("opaque80mem",         TYPE_M1664)
 999   TYPE("opaque512mem",        TYPE_M512)
1000   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1001   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1002   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1003   TYPE("offset8",             TYPE_MOFFS8)
1004   TYPE("offset16",            TYPE_MOFFS16)
1005   TYPE("offset32",            TYPE_MOFFS32)
1006   TYPE("offset64",            TYPE_MOFFS64)
1007   TYPE("VR256",               TYPE_XMM256)
1008   errs() << "Unhandled type string " << s << "\n";
1009   llvm_unreachable("Unhandled type string");
1010 }
1011 #undef TYPE
1012
1013 #define ENCODING(str, encoding) if (s == str) return encoding;
1014 OperandEncoding RecognizableInstr::immediateEncodingFromString
1015   (const std::string &s,
1016    bool hasOpSizePrefix) {
1017   if(!hasOpSizePrefix) {
1018     // For instructions without an OpSize prefix, a declared 16-bit register or
1019     // immediate encoding is special.
1020     ENCODING("i16imm",        ENCODING_IW)
1021   }
1022   ENCODING("i32i8imm",        ENCODING_IB)
1023   ENCODING("SSECC",           ENCODING_IB)
1024   ENCODING("i16imm",          ENCODING_Iv)
1025   ENCODING("i16i8imm",        ENCODING_IB)
1026   ENCODING("i32imm",          ENCODING_Iv)
1027   ENCODING("i64i32imm",       ENCODING_ID)
1028   ENCODING("i64i8imm",        ENCODING_IB)
1029   ENCODING("i8imm",           ENCODING_IB)
1030   // This is not a typo.  Instructions like BLENDVPD put
1031   // register IDs in 8-bit immediates nowadays.
1032   ENCODING("VR256",           ENCODING_IB)
1033   ENCODING("VR128",           ENCODING_IB)
1034   errs() << "Unhandled immediate encoding " << s << "\n";
1035   llvm_unreachable("Unhandled immediate encoding");
1036 }
1037
1038 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1039   (const std::string &s,
1040    bool hasOpSizePrefix) {
1041   ENCODING("GR16",            ENCODING_RM)
1042   ENCODING("GR32",            ENCODING_RM)
1043   ENCODING("GR64",            ENCODING_RM)
1044   ENCODING("GR8",             ENCODING_RM)
1045   ENCODING("VR128",           ENCODING_RM)
1046   ENCODING("FR64",            ENCODING_RM)
1047   ENCODING("FR32",            ENCODING_RM)
1048   ENCODING("VR64",            ENCODING_RM)
1049   ENCODING("VR256",           ENCODING_RM)
1050   errs() << "Unhandled R/M register encoding " << s << "\n";
1051   llvm_unreachable("Unhandled R/M register encoding");
1052 }
1053
1054 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1055   (const std::string &s,
1056    bool hasOpSizePrefix) {
1057   ENCODING("GR16",            ENCODING_REG)
1058   ENCODING("GR32",            ENCODING_REG)
1059   ENCODING("GR64",            ENCODING_REG)
1060   ENCODING("GR8",             ENCODING_REG)
1061   ENCODING("VR128",           ENCODING_REG)
1062   ENCODING("FR64",            ENCODING_REG)
1063   ENCODING("FR32",            ENCODING_REG)
1064   ENCODING("VR64",            ENCODING_REG)
1065   ENCODING("SEGMENT_REG",     ENCODING_REG)
1066   ENCODING("DEBUG_REG",       ENCODING_REG)
1067   ENCODING("CONTROL_REG",     ENCODING_REG)
1068   ENCODING("VR256",           ENCODING_REG)
1069   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1070   llvm_unreachable("Unhandled reg/opcode register encoding");
1071 }
1072
1073 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1074   (const std::string &s,
1075    bool hasOpSizePrefix) {
1076   ENCODING("FR32",            ENCODING_VVVV)
1077   ENCODING("FR64",            ENCODING_VVVV)
1078   ENCODING("VR128",           ENCODING_VVVV)
1079   ENCODING("VR256",           ENCODING_VVVV)
1080   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1081   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1082 }
1083
1084 OperandEncoding RecognizableInstr::memoryEncodingFromString
1085   (const std::string &s,
1086    bool hasOpSizePrefix) {
1087   ENCODING("i16mem",          ENCODING_RM)
1088   ENCODING("i32mem",          ENCODING_RM)
1089   ENCODING("i64mem",          ENCODING_RM)
1090   ENCODING("i8mem",           ENCODING_RM)
1091   ENCODING("ssmem",           ENCODING_RM)
1092   ENCODING("sdmem",           ENCODING_RM)
1093   ENCODING("f128mem",         ENCODING_RM)
1094   ENCODING("f256mem",         ENCODING_RM)
1095   ENCODING("f64mem",          ENCODING_RM)
1096   ENCODING("f32mem",          ENCODING_RM)
1097   ENCODING("i128mem",         ENCODING_RM)
1098   ENCODING("i256mem",         ENCODING_RM)
1099   ENCODING("f80mem",          ENCODING_RM)
1100   ENCODING("lea32mem",        ENCODING_RM)
1101   ENCODING("lea64_32mem",     ENCODING_RM)
1102   ENCODING("lea64mem",        ENCODING_RM)
1103   ENCODING("opaque32mem",     ENCODING_RM)
1104   ENCODING("opaque48mem",     ENCODING_RM)
1105   ENCODING("opaque80mem",     ENCODING_RM)
1106   ENCODING("opaque512mem",    ENCODING_RM)
1107   errs() << "Unhandled memory encoding " << s << "\n";
1108   llvm_unreachable("Unhandled memory encoding");
1109 }
1110
1111 OperandEncoding RecognizableInstr::relocationEncodingFromString
1112   (const std::string &s,
1113    bool hasOpSizePrefix) {
1114   if(!hasOpSizePrefix) {
1115     // For instructions without an OpSize prefix, a declared 16-bit register or
1116     // immediate encoding is special.
1117     ENCODING("i16imm",        ENCODING_IW)
1118   }
1119   ENCODING("i16imm",          ENCODING_Iv)
1120   ENCODING("i16i8imm",        ENCODING_IB)
1121   ENCODING("i32imm",          ENCODING_Iv)
1122   ENCODING("i32i8imm",        ENCODING_IB)
1123   ENCODING("i64i32imm",       ENCODING_ID)
1124   ENCODING("i64i8imm",        ENCODING_IB)
1125   ENCODING("i8imm",           ENCODING_IB)
1126   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1127   ENCODING("i16imm_pcrel",    ENCODING_IW)
1128   ENCODING("i32imm_pcrel",    ENCODING_ID)
1129   ENCODING("brtarget",        ENCODING_Iv)
1130   ENCODING("brtarget8",       ENCODING_IB)
1131   ENCODING("i64imm",          ENCODING_IO)
1132   ENCODING("offset8",         ENCODING_Ia)
1133   ENCODING("offset16",        ENCODING_Ia)
1134   ENCODING("offset32",        ENCODING_Ia)
1135   ENCODING("offset64",        ENCODING_Ia)
1136   errs() << "Unhandled relocation encoding " << s << "\n";
1137   llvm_unreachable("Unhandled relocation encoding");
1138 }
1139
1140 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1141   (const std::string &s,
1142    bool hasOpSizePrefix) {
1143   ENCODING("RST",             ENCODING_I)
1144   ENCODING("GR32",            ENCODING_Rv)
1145   ENCODING("GR64",            ENCODING_RO)
1146   ENCODING("GR16",            ENCODING_Rv)
1147   ENCODING("GR8",             ENCODING_RB)
1148   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1149   llvm_unreachable("Unhandled opcode modifier encoding");
1150 }
1151 #undef ENCODING