utils/TableGen/X86RecognizableInstr.h

   1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the X86 Disassembler Emitter.
  11 // It contains the interface of a single recognizable instruction.
  12 // Documentation for the disassembler emitter in general can be found in
  13 //  X86DisasemblerEmitter.h.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef X86RECOGNIZABLEINSTR_H
  18 #define X86RECOGNIZABLEINSTR_H
  19
  20 #include "X86DisassemblerTables.h"
  21
  22 #include "CodeGenTarget.h"
  23 #include "Record.h"
  24
  25 #include "llvm/Support/DataTypes.h"
  26 #include "llvm/ADT/SmallVector.h"
  27
  28 namespace llvm {
  29
  30 namespace X86Disassembler {
  31
  32 /// RecognizableInstr - Encapsulates all information required to decode a single
  33 ///   instruction, as extracted from the LLVM instruction tables.  Has methods
  34 ///   to interpret the information available in the LLVM tables, and to emit the
  35 ///   instruction into DisassemblerTables.
  36 class RecognizableInstr {
  37 private:
  38   /// The opcode of the instruction, as used in an MCInst
  39   InstrUID UID;
  40   /// The record from the .td files corresponding to this instruction
  41   const Record* Rec;
  42   /// The prefix field from the record
  43   uint8_t Prefix;
  44   /// The opcode field from the record; this is the opcode used in the Intel
  45   /// encoding and therefore distinct from the UID
  46   uint8_t Opcode;
  47   /// The form field from the record
  48   uint8_t Form;
  49   /// The segment override field from the record
  50   uint8_t SegOvr;
  51   /// The hasOpSizePrefix field from the record
  52   bool HasOpSizePrefix;
  53   /// The hasREX_WPrefix field from the record
  54   bool HasREX_WPrefix;
  55   /// The hasVEXPrefix field from the record
  56   bool HasVEXPrefix;
  57   /// The hasVEX_4VPrefix field from the record
  58   bool HasVEX_4VPrefix;
  59   /// The hasVEX_WPrefix field from the record
  60   bool HasVEX_WPrefix;
  61   /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
  62   bool HasVEX_LPrefix;
  63   /// The hasLockPrefix field from the record
  64   bool HasLockPrefix;
  65   /// The isCodeGenOnly filed from the record
  66   bool IsCodeGenOnly;
  67
  68   /// The instruction name as listed in the tables
  69   std::string Name;
  70   /// The AT&T AsmString for the instruction
  71   std::string AsmString;
  72
  73   /// Indicates whether the instruction is SSE
  74   bool IsSSE;
  75   /// Indicates whether the instruction has FR operands - MOVs with FR operands
  76   /// are typically ignored
  77   bool HasFROperands;
  78   /// Indicates whether the instruction should be emitted into the decode
  79   /// tables; regardless, it will be emitted into the instruction info table
  80   bool ShouldBeEmitted;
  81
  82   /// The operands of the instruction, as listed in the CodeGenInstruction.
  83   /// They are not one-to-one with operands listed in the MCInst; for example,
  84   /// memory operands expand to 5 operands in the MCInst
  85   const std::vector<CGIOperandList::OperandInfo>* Operands;
  86
  87   /// The description of the instruction that is emitted into the instruction
  88   /// info table
  89   InstructionSpecifier* Spec;
  90
  91   /// insnContext - Returns the primary context in which the instruction is
  92   ///   valid.
  93   ///
  94   /// @return - The context in which the instruction is valid.
  95   InstructionContext insnContext() const;
  96
  97   enum filter_ret {
  98     FILTER_STRONG,    // instruction has no place in the instruction tables
  99     FILTER_WEAK,      // instruction may conflict, and should be eliminated if
 100                       // it does
 101     FILTER_NORMAL     // instruction should have high priority and generate an
 102                       // error if it conflcits with any other FILTER_NORMAL
 103                       // instruction
 104   };
 105
 106   /// filter - Determines whether the instruction should be decodable.  Some
 107   ///   instructions are pure intrinsics and use unencodable operands; many
 108   ///   synthetic instructions are duplicates of other instructions; other
 109   ///   instructions only differ in the logical way in which they are used, and
 110   ///   have the same decoding.  Because these would cause decode conflicts,
 111   ///   they must be filtered out.
 112   ///
 113   /// @return - The degree of filtering to be applied (see filter_ret).
 114   filter_ret filter() const;
 115
 116   /// hasFROperands - Returns true if any operand is a FR operand.
 117   bool hasFROperands() const;
 118
 119   /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
 120   bool has256BitOperands() const;
 121
 122   /// typeFromString - Translates an operand type from the string provided in
 123   ///   the LLVM tables to an OperandType for use in the operand specifier.
 124   ///
 125   /// @param s              - The string, as extracted by calling Rec->getName()
 126   ///                         on a CodeGenInstruction::OperandInfo.
 127   /// @param isSSE          - Indicates whether the instruction is an SSE
 128   ///                         instruction.  For SSE instructions, immediates are
 129   ///                         fixed-size rather than being affected by the
 130   ///                         mandatory OpSize prefix.
 131   /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
 132   ///                         prefix.  If it does, 32-bit register operands stay
 133   ///                         32-bit regardless of the operand size.
 134   /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
 135   ///                         prefix.  If it does not, then 16-bit register
 136   ///                         operands stay 16-bit.
 137   /// @return               - The operand's type.
 138   static OperandType typeFromString(const std::string& s,
 139                                     bool isSSE,
 140                                     bool hasREX_WPrefix,
 141                                     bool hasOpSizePrefix);
 142
 143   /// immediateEncodingFromString - Translates an immediate encoding from the
 144   ///   string provided in the LLVM tables to an OperandEncoding for use in
 145   ///   the operand specifier.
 146   ///
 147   /// @param s                - See typeFromString().
 148   /// @param hasOpSizePrefix  - Indicates whether the instruction has an OpSize
 149   ///                           prefix.  If it does not, then 16-bit immediate
 150   ///                           operands stay 16-bit.
 151   /// @return                 - The operand's encoding.
 152   static OperandEncoding immediateEncodingFromString(const std::string &s,
 153                                                      bool hasOpSizePrefix);
 154
 155   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 156   ///   handles operands that are in the REG field of the ModR/M byte.
 157   static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
 158                                                       bool hasOpSizePrefix);
 159
 160   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 161   ///   handles operands that are in the REG field of the ModR/M byte.
 162   static OperandEncoding roRegisterEncodingFromString(const std::string &s,
 163                                                       bool hasOpSizePrefix);
 164   static OperandEncoding memoryEncodingFromString(const std::string &s,
 165                                                   bool hasOpSizePrefix);
 166   static OperandEncoding relocationEncodingFromString(const std::string &s,
 167                                                       bool hasOpSizePrefix);
 168   static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
 169                                                           bool hasOpSizePrefix);
 170   static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
 171                                                         bool HasOpSizePrefix);
 172
 173   /// handleOperand - Converts a single operand from the LLVM table format to
 174   ///   the emitted table format, handling any duplicate operands it encounters
 175   ///   and then one non-duplicate.
 176   ///
 177   /// @param optional             - Determines whether to assert that the
 178   ///                               operand exists.
 179   /// @param operandIndex         - The index into the generated operand table.
 180   ///                               Incremented by this function one or more
 181   ///                               times to reflect possible duplicate
 182   ///                               operands).
 183   /// @param physicalOperandIndex - The index of the current operand into the
 184   ///                               set of non-duplicate ('physical') operands.
 185   ///                               Incremented by this function once.
 186   /// @param numPhysicalOperands  - The number of non-duplicate operands in the
 187   ///                               instructions.
 188   /// @param operandMapping       - The operand mapping, which has an entry for
 189   ///                               each operand that indicates whether it is a
 190   ///                               duplicate, and of what.
 191   void handleOperand(bool optional,
 192                      unsigned &operandIndex,
 193                      unsigned &physicalOperandIndex,
 194                      unsigned &numPhysicalOperands,
 195                      unsigned *operandMapping,
 196                      OperandEncoding (*encodingFromString)
 197                        (const std::string&,
 198                         bool hasOpSizePrefix));
 199
 200   /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
 201   ///   filters out many instructions, at various points in decoding we
 202   ///   determine that the instruction should not actually be decodable.  In
 203   ///   particular, MMX MOV instructions aren't emitted, but they're only
 204   ///   identified during operand parsing.
 205   ///
 206   /// @return - true if at this point we believe the instruction should be
 207   ///   emitted; false if not.  This will return false if filter() returns false
 208   ///   once emitInstructionSpecifier() has been called.
 209   bool shouldBeEmitted() const {
 210     return ShouldBeEmitted;
 211   }
 212
 213   /// emitInstructionSpecifier - Loads the instruction specifier for the current
 214   ///   instruction into a DisassemblerTables.
 215   ///
 216   /// @arg tables - The DisassemblerTables to populate with the specifier for
 217   ///               the current instruction.
 218   void emitInstructionSpecifier(DisassemblerTables &tables);
 219
 220   /// emitDecodePath - Populates the proper fields in the decode tables
 221   ///   corresponding to the decode paths for this instruction.
 222   ///
 223   /// @arg tables - The DisassemblerTables to populate with the decode
 224   ///               decode information for the current instruction.
 225   void emitDecodePath(DisassemblerTables &tables) const;
 226
 227   /// Constructor - Initializes a RecognizableInstr with the appropriate fields
 228   ///   from a CodeGenInstruction.
 229   ///
 230   /// @arg tables - The DisassemblerTables that the specifier will be added to.
 231   /// @arg insn   - The CodeGenInstruction to extract information from.
 232   /// @arg uid    - The unique ID of the current instruction.
 233   RecognizableInstr(DisassemblerTables &tables,
 234                     const CodeGenInstruction &insn,
 235                     InstrUID uid);
 236 public:
 237   /// processInstr - Accepts a CodeGenInstruction and loads decode information
 238   ///   for it into a DisassemblerTables if appropriate.
 239   ///
 240   /// @arg tables - The DiassemblerTables to be populated with decode
 241   ///               information.
 242   /// @arg insn   - The CodeGenInstruction to be used as a source for this
 243   ///               information.
 244   /// @uid        - The unique ID of the instruction.
 245   static void processInstr(DisassemblerTables &tables,
 246                            const CodeGenInstruction &insn,
 247                            InstrUID uid);
 248 };
 249
 250 } // namespace X86Disassembler
 251
 252 } // namespace llvm
 253
 254 #endif