lib/CodeGen/ScheduleDAGInstrs.h

   1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the ScheduleDAGInstrs class, which implements
  11 // scheduling for a MachineInstr-based dependency graph.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SCHEDULEDAGINSTRS_H
  16 #define SCHEDULEDAGINSTRS_H
  17
  18 #include "llvm/CodeGen/MachineDominators.h"
  19 #include "llvm/CodeGen/MachineLoopInfo.h"
  20 #include "llvm/CodeGen/ScheduleDAG.h"
  21 #include "llvm/Support/Compiler.h"
  22 #include "llvm/Target/TargetRegisterInfo.h"
  23 #include "llvm/ADT/SmallSet.h"
  24 #include <map>
  25
  26 namespace llvm {
  27   class MachineLoopInfo;
  28   class MachineDominatorTree;
  29
  30   /// LoopDependencies - This class analyzes loop-oriented register
  31   /// dependencies, which are used to guide scheduling decisions.
  32   /// For example, loop induction variable increments should be
  33   /// scheduled as soon as possible after the variable's last use.
  34   ///
  35   class LLVM_LIBRARY_VISIBILITY LoopDependencies {
  36     const MachineLoopInfo &MLI;
  37     const MachineDominatorTree &MDT;
  38
  39   public:
  40     typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
  41       LoopDeps;
  42     LoopDeps Deps;
  43
  44     LoopDependencies(const MachineLoopInfo &mli,
  45                      const MachineDominatorTree &mdt) :
  46       MLI(mli), MDT(mdt) {}
  47
  48     /// VisitLoop - Clear out any previous state and analyze the given loop.
  49     ///
  50     void VisitLoop(const MachineLoop *Loop) {
  51       Deps.clear();
  52       MachineBasicBlock *Header = Loop->getHeader();
  53       SmallSet<unsigned, 8> LoopLiveIns;
  54       for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
  55            LE = Header->livein_end(); LI != LE; ++LI)
  56         LoopLiveIns.insert(*LI);
  57
  58       const MachineDomTreeNode *Node = MDT.getNode(Header);
  59       const MachineBasicBlock *MBB = Node->getBlock();
  60       assert(Loop->contains(MBB) &&
  61              "Loop does not contain header!");
  62       VisitRegion(Node, MBB, Loop, LoopLiveIns);
  63     }
  64
  65   private:
  66     void VisitRegion(const MachineDomTreeNode *Node,
  67                      const MachineBasicBlock *MBB,
  68                      const MachineLoop *Loop,
  69                      const SmallSet<unsigned, 8> &LoopLiveIns) {
  70       unsigned Count = 0;
  71       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
  72            I != E; ++I) {
  73         const MachineInstr *MI = I;
  74         if (MI->isDebugValue())
  75           continue;
  76         for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
  77           const MachineOperand &MO = MI->getOperand(i);
  78           if (!MO.isReg() || !MO.isUse())
  79             continue;
  80           unsigned MOReg = MO.getReg();
  81           if (LoopLiveIns.count(MOReg))
  82             Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
  83         }
  84         ++Count; // Not every iteration due to dbg_value above.
  85       }
  86
  87       const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
  88       for (std::vector<MachineDomTreeNode*>::const_iterator I =
  89            Children.begin(), E = Children.end(); I != E; ++I) {
  90         const MachineDomTreeNode *ChildNode = *I;
  91         MachineBasicBlock *ChildBlock = ChildNode->getBlock();
  92         if (Loop->contains(ChildBlock))
  93           VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
  94       }
  95     }
  96   };
  97
  98   /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
  99   /// MachineInstrs.
 100   class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
 101     const MachineLoopInfo &MLI;
 102     const MachineDominatorTree &MDT;
 103     const MachineFrameInfo *MFI;
 104     const InstrItineraryData *InstrItins;
 105
 106     /// Defs, Uses - Remember where defs and uses of each physical register
 107     /// are as we iterate upward through the instructions. This is allocated
 108     /// here instead of inside BuildSchedGraph to avoid the need for it to be
 109     /// initialized and destructed for each block.
 110     std::vector<std::vector<SUnit *> > Defs;
 111     std::vector<std::vector<SUnit *> > Uses;
 112
 113     /// DbgValueVec - Remember DBG_VALUEs that refer to a particular
 114     /// register.
 115     std::vector<MachineInstr *>DbgValueVec;
 116
 117     /// PendingLoads - Remember where unknown loads are after the most recent
 118     /// unknown store, as we iterate. As with Defs and Uses, this is here
 119     /// to minimize construction/destruction.
 120     std::vector<SUnit *> PendingLoads;
 121
 122     /// LoopRegs - Track which registers are used for loop-carried dependencies.
 123     ///
 124     LoopDependencies LoopRegs;
 125
 126     /// LoopLiveInRegs - Track which regs are live into a loop, to help guide
 127     /// back-edge-aware scheduling.
 128     ///
 129     SmallSet<unsigned, 8> LoopLiveInRegs;
 130
 131   public:
 132     MachineBasicBlock::iterator Begin;    // The beginning of the range to
 133                                           // be scheduled. The range extends
 134                                           // to InsertPos.
 135     unsigned InsertPosIndex;              // The index in BB of InsertPos.
 136
 137     explicit ScheduleDAGInstrs(MachineFunction &mf,
 138                                const MachineLoopInfo &mli,
 139                                const MachineDominatorTree &mdt);
 140
 141     virtual ~ScheduleDAGInstrs() {}
 142
 143     /// NewSUnit - Creates a new SUnit and return a ptr to it.
 144     ///
 145     SUnit *NewSUnit(MachineInstr *MI) {
 146 #ifndef NDEBUG
 147       const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
 148 #endif
 149       SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
 150       assert((Addr == 0 || Addr == &SUnits[0]) &&
 151              "SUnits std::vector reallocated on the fly!");
 152       SUnits.back().OrigNode = &SUnits.back();
 153       return &SUnits.back();
 154     }
 155
 156     /// Run - perform scheduling.
 157     ///
 158     void Run(MachineBasicBlock *bb,
 159              MachineBasicBlock::iterator begin,
 160              MachineBasicBlock::iterator end,
 161              unsigned endindex);
 162
 163     /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
 164     /// input.
 165     virtual void BuildSchedGraph(AliasAnalysis *AA);
 166
 167     /// AddSchedBarrierDeps - Add dependencies from instructions in the current
 168     /// list of instructions being scheduled to scheduling barrier. We want to
 169     /// make sure instructions which define registers that are either used by
 170     /// the terminator or are live-out are properly scheduled. This is
 171     /// especially important when the definition latency of the return value(s)
 172     /// are too high to be hidden by the branch or when the liveout registers
 173     /// used by instructions in the fallthrough block.
 174     void AddSchedBarrierDeps();
 175
 176     /// ComputeLatency - Compute node latency.
 177     ///
 178     virtual void ComputeLatency(SUnit *SU);
 179
 180     /// ComputeOperandLatency - Override dependence edge latency using
 181     /// operand use/def information
 182     ///
 183     virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
 184                                        SDep& dep) const;
 185
 186     virtual MachineBasicBlock *EmitSchedule();
 187
 188     /// StartBlock - Prepare to perform scheduling in the given block.
 189     ///
 190     virtual void StartBlock(MachineBasicBlock *BB);
 191
 192     /// Schedule - Order nodes according to selected style, filling
 193     /// in the Sequence member.
 194     ///
 195     virtual void Schedule() = 0;
 196
 197     /// FinishBlock - Clean up after scheduling in the given block.
 198     ///
 199     virtual void FinishBlock();
 200
 201     virtual void dumpNode(const SUnit *SU) const;
 202
 203     virtual std::string getGraphNodeLabel(const SUnit *SU) const;
 204   };
 205 }
 206
 207 #endif