lib/CodeGen/Spiller.cpp

   1 //===-- llvm/CodeGen/Spiller.cpp -  Spiller -------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "spiller"
  11
  12 #include "Spiller.h"
  13 #include "VirtRegMap.h"
  14 #include "LiveRangeEdit.h"
  15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  16 #include "llvm/CodeGen/LiveStackAnalysis.h"
  17 #include "llvm/CodeGen/MachineFrameInfo.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineLoopInfo.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/Target/TargetInstrInfo.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/Debug.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/raw_ostream.h"
  28 #include <set>
  29
  30 using namespace llvm;
  31
  32 namespace {
  33   enum SpillerName { trivial, standard, inline_ };
  34 }
  35
  36 static cl::opt<SpillerName>
  37 spillerOpt("spiller",
  38            cl::desc("Spiller to use: (default: standard)"),
  39            cl::Prefix,
  40            cl::values(clEnumVal(trivial,   "trivial spiller"),
  41                       clEnumVal(standard,  "default spiller"),
  42                       clEnumValN(inline_,  "inline", "inline spiller"),
  43                       clEnumValEnd),
  44            cl::init(standard));
  45
  46 // Spiller virtual destructor implementation.
  47 Spiller::~Spiller() {}
  48
  49 namespace {
  50
  51 /// Utility class for spillers.
  52 class SpillerBase : public Spiller {
  53 protected:
  54   MachineFunctionPass *pass;
  55   MachineFunction *mf;
  56   VirtRegMap *vrm;
  57   LiveIntervals *lis;
  58   MachineFrameInfo *mfi;
  59   MachineRegisterInfo *mri;
  60   const TargetInstrInfo *tii;
  61   const TargetRegisterInfo *tri;
  62
  63   /// Construct a spiller base.
  64   SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
  65     : pass(&pass), mf(&mf), vrm(&vrm)
  66   {
  67     lis = &pass.getAnalysis<LiveIntervals>();
  68     mfi = mf.getFrameInfo();
  69     mri = &mf.getRegInfo();
  70     tii = mf.getTarget().getInstrInfo();
  71     tri = mf.getTarget().getRegisterInfo();
  72   }
  73
  74   /// Add spill ranges for every use/def of the live interval, inserting loads
  75   /// immediately before each use, and stores after each def. No folding or
  76   /// remat is attempted.
  77   void trivialSpillEverywhere(LiveInterval *li,
  78                               SmallVectorImpl<LiveInterval*> &newIntervals) {
  79     DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
  80
  81     assert(li->weight != HUGE_VALF &&
  82            "Attempting to spill already spilled value.");
  83
  84     assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
  85            "Trying to spill a stack slot.");
  86
  87     DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
  88
  89     const TargetRegisterClass *trc = mri->getRegClass(li->reg);
  90     unsigned ss = vrm->assignVirt2StackSlot(li->reg);
  91
  92     // Iterate over reg uses/defs.
  93     for (MachineRegisterInfo::reg_iterator
  94          regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
  95
  96       // Grab the use/def instr.
  97       MachineInstr *mi = &*regItr;
  98
  99       DEBUG(dbgs() << "  Processing " << *mi);
 100
 101       // Step regItr to the next use/def instr.
 102       do {
 103         ++regItr;
 104       } while (regItr != mri->reg_end() && (&*regItr == mi));
 105
 106       // Collect uses & defs for this instr.
 107       SmallVector<unsigned, 2> indices;
 108       bool hasUse = false;
 109       bool hasDef = false;
 110       for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
 111         MachineOperand &op = mi->getOperand(i);
 112         if (!op.isReg() || op.getReg() != li->reg)
 113           continue;
 114         hasUse |= mi->getOperand(i).isUse();
 115         hasDef |= mi->getOperand(i).isDef();
 116         indices.push_back(i);
 117       }
 118
 119       // Create a new vreg & interval for this instr.
 120       unsigned newVReg = mri->createVirtualRegister(trc);
 121       vrm->grow();
 122       vrm->assignVirt2StackSlot(newVReg, ss);
 123       LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
 124       newLI->weight = HUGE_VALF;
 125
 126       // Update the reg operands & kill flags.
 127       for (unsigned i = 0; i < indices.size(); ++i) {
 128         unsigned mopIdx = indices[i];
 129         MachineOperand &mop = mi->getOperand(mopIdx);
 130         mop.setReg(newVReg);
 131         if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
 132           mop.setIsKill(true);
 133         }
 134       }
 135       assert(hasUse || hasDef);
 136
 137       // Insert reload if necessary.
 138       MachineBasicBlock::iterator miItr(mi);
 139       if (hasUse) {
 140         tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
 141                                   tri);
 142         MachineInstr *loadInstr(prior(miItr));
 143         SlotIndex loadIndex =
 144           lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
 145         vrm->addSpillSlotUse(ss, loadInstr);
 146         SlotIndex endIndex = loadIndex.getNextIndex();
 147         VNInfo *loadVNI =
 148           newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
 149         newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
 150       }
 151
 152       // Insert store if necessary.
 153       if (hasDef) {
 154         tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
 155                                  true, ss, trc, tri);
 156         MachineInstr *storeInstr(llvm::next(miItr));
 157         SlotIndex storeIndex =
 158           lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
 159         vrm->addSpillSlotUse(ss, storeInstr);
 160         SlotIndex beginIndex = storeIndex.getPrevIndex();
 161         VNInfo *storeVNI =
 162           newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
 163         newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
 164       }
 165
 166       newIntervals.push_back(newLI);
 167     }
 168   }
 169 };
 170
 171 } // end anonymous namespace
 172
 173 namespace {
 174
 175 /// Spills any live range using the spill-everywhere method with no attempt at
 176 /// folding.
 177 class TrivialSpiller : public SpillerBase {
 178 public:
 179
 180   TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
 181                  VirtRegMap &vrm)
 182     : SpillerBase(pass, mf, vrm) {}
 183
 184   void spill(LiveRangeEdit &LRE) {
 185     // Ignore spillIs - we don't use it.
 186     trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs());
 187   }
 188 };
 189
 190 } // end anonymous namespace
 191
 192 namespace {
 193
 194 /// Falls back on LiveIntervals::addIntervalsForSpills.
 195 class StandardSpiller : public Spiller {
 196 protected:
 197   MachineFunction *mf;
 198   LiveIntervals *lis;
 199   LiveStacks *lss;
 200   MachineLoopInfo *loopInfo;
 201   VirtRegMap *vrm;
 202 public:
 203   StandardSpiller(MachineFunctionPass &pass, MachineFunction &mf,
 204                   VirtRegMap &vrm)
 205     : mf(&mf),
 206       lis(&pass.getAnalysis<LiveIntervals>()),
 207       lss(&pass.getAnalysis<LiveStacks>()),
 208       loopInfo(pass.getAnalysisIfAvailable<MachineLoopInfo>()),
 209       vrm(&vrm) {}
 210
 211   /// Falls back on LiveIntervals::addIntervalsForSpills.
 212   void spill(LiveRangeEdit &LRE) {
 213     std::vector<LiveInterval*> added =
 214       lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(),
 215                                  loopInfo, *vrm);
 216     LRE.getNewVRegs()->insert(LRE.getNewVRegs()->end(),
 217                               added.begin(), added.end());
 218
 219     // Update LiveStacks.
 220     int SS = vrm->getStackSlot(LRE.getReg());
 221     if (SS == VirtRegMap::NO_STACK_SLOT)
 222       return;
 223     const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
 224     LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
 225     if (!SI.hasAtLeastOneValue())
 226       SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator());
 227     SI.MergeRangesInAsValue(LRE.getParent(), SI.getValNumInfo(0));
 228   }
 229 };
 230
 231 } // end anonymous namespace
 232
 233 llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
 234                                    MachineFunction &mf,
 235                                    VirtRegMap &vrm) {
 236   switch (spillerOpt) {
 237   default: assert(0 && "unknown spiller");
 238   case trivial: return new TrivialSpiller(pass, mf, vrm);
 239   case standard: return new StandardSpiller(pass, mf, vrm);
 240   case inline_: return createInlineSpiller(pass, mf, vrm);
 241   }
 242 }