lib/CodeGen/LiveIntervalUnion.h

   1 //===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // LiveIntervalUnion is a union of live segments across multiple live virtual
  11 // registers. This may be used during coalescing to represent a congruence
  12 // class, or during register allocation to model liveness of a physical
  13 // register.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION
  18 #define LLVM_CODEGEN_LIVEINTERVALUNION
  19
  20 #include "llvm/ADT/IntervalMap.h"
  21 #include "llvm/CodeGen/LiveInterval.h"
  22
  23 #include <algorithm>
  24
  25 namespace llvm {
  26
  27 class MachineLoopRange;
  28 class TargetRegisterInfo;
  29
  30 #ifndef NDEBUG
  31 // forward declaration
  32 template <unsigned Element> class SparseBitVector;
  33 typedef SparseBitVector<128> LiveVirtRegBitSet;
  34 #endif
  35
  36 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
  37 inline bool
  38 overlap(const LiveRange &VRSeg,
  39         const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
  40   return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
  41 }
  42
  43 /// Union of live intervals that are strong candidates for coalescing into a
  44 /// single register (either physical or virtual depending on the context).  We
  45 /// expect the constituent live intervals to be disjoint, although we may
  46 /// eventually make exceptions to handle value-based interference.
  47 class LiveIntervalUnion {
  48   // A set of live virtual register segments that supports fast insertion,
  49   // intersection, and removal.
  50   // Mapping SlotIndex intervals to virtual register numbers.
  51   typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
  52
  53 public:
  54   // SegmentIter can advance to the next segment ordered by starting position
  55   // which may belong to a different live virtual register. We also must be able
  56   // to reach the current segment's containing virtual register.
  57   typedef LiveSegments::iterator SegmentIter;
  58
  59   // LiveIntervalUnions share an external allocator.
  60   typedef LiveSegments::Allocator Allocator;
  61
  62   class InterferenceResult;
  63   class Query;
  64
  65 private:
  66   const unsigned RepReg;  // representative register number
  67   unsigned Tag;           // unique tag for current contents.
  68   LiveSegments Segments;  // union of virtual reg segments
  69
  70 public:
  71   LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Tag(0), Segments(a)
  72     {}
  73
  74   // Iterate over all segments in the union of live virtual registers ordered
  75   // by their starting position.
  76   SegmentIter begin() { return Segments.begin(); }
  77   SegmentIter end() { return Segments.end(); }
  78   SegmentIter find(SlotIndex x) { return Segments.find(x); }
  79   bool empty() const { return Segments.empty(); }
  80   SlotIndex startIndex() const { return Segments.start(); }
  81
  82   // Provide public access to the underlying map to allow overlap iteration.
  83   typedef LiveSegments Map;
  84   const Map &getMap() { return Segments; }
  85
  86   /// getTag - Return an opaque tag representing the current state of the union.
  87   unsigned getTag() const { return Tag; }
  88
  89   /// changedSince - Return true if the union change since getTag returned tag.
  90   bool changedSince(unsigned tag) const { return tag != Tag; }
  91
  92   // Add a live virtual register to this union and merge its segments.
  93   void unify(LiveInterval &VirtReg);
  94
  95   // Remove a live virtual register's segments from this union.
  96   void extract(LiveInterval &VirtReg);
  97
  98   // Remove all inserted virtual registers.
  99   void clear() { Segments.clear(); ++Tag; }
 100
 101   // Print union, using TRI to translate register names
 102   void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
 103
 104 #ifndef NDEBUG
 105   // Verify the live intervals in this union and add them to the visited set.
 106   void verify(LiveVirtRegBitSet& VisitedVRegs);
 107 #endif
 108
 109   /// Cache a single interference test result in the form of two intersecting
 110   /// segments. This allows efficiently iterating over the interferences. The
 111   /// iteration logic is handled by LiveIntervalUnion::Query which may
 112   /// filter interferences depending on the type of query.
 113   class InterferenceResult {
 114     friend class Query;
 115
 116     LiveInterval::iterator VirtRegI; // current position in VirtReg
 117     SegmentIter LiveUnionI;          // current position in LiveUnion
 118
 119     // Internal ctor.
 120     InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
 121       : VirtRegI(VRegI), LiveUnionI(UnionI) {}
 122
 123   public:
 124     // Public default ctor.
 125     InterferenceResult(): VirtRegI(), LiveUnionI() {}
 126
 127     /// start - Return the start of the current overlap.
 128     SlotIndex start() const {
 129       return std::max(VirtRegI->start, LiveUnionI.start());
 130     }
 131
 132     /// stop - Return the end of the current overlap.
 133     SlotIndex stop() const {
 134       return std::min(VirtRegI->end, LiveUnionI.stop());
 135     }
 136
 137     /// interference - Return the register that is interfering here.
 138     LiveInterval *interference() const { return LiveUnionI.value(); }
 139
 140     // Note: this interface provides raw access to the iterators because the
 141     // result has no way to tell if it's valid to dereference them.
 142
 143     // Access the VirtReg segment.
 144     LiveInterval::iterator virtRegPos() const { return VirtRegI; }
 145
 146     // Access the LiveUnion segment.
 147     const SegmentIter &liveUnionPos() const { return LiveUnionI; }
 148
 149     bool operator==(const InterferenceResult &IR) const {
 150       return VirtRegI == IR.VirtRegI && LiveUnionI == IR.LiveUnionI;
 151     }
 152     bool operator!=(const InterferenceResult &IR) const {
 153       return !operator==(IR);
 154     }
 155
 156     void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
 157   };
 158
 159   /// Query interferences between a single live virtual register and a live
 160   /// interval union.
 161   class Query {
 162     LiveIntervalUnion *LiveUnion;
 163     LiveInterval *VirtReg;
 164     InterferenceResult FirstInterference;
 165     SmallVector<LiveInterval*,4> InterferingVRegs;
 166     bool CheckedFirstInterference;
 167     bool SeenAllInterferences;
 168     bool SeenUnspillableVReg;
 169     unsigned Tag, UserTag;
 170
 171   public:
 172     Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
 173
 174     Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
 175       LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
 176       SeenAllInterferences(false), SeenUnspillableVReg(false)
 177     {}
 178
 179     void clear() {
 180       LiveUnion = NULL;
 181       VirtReg = NULL;
 182       InterferingVRegs.clear();
 183       CheckedFirstInterference = false;
 184       SeenAllInterferences = false;
 185       SeenUnspillableVReg = false;
 186       Tag = 0;
 187       UserTag = 0;
 188     }
 189
 190     void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
 191       assert(VReg && LIU && "Invalid arguments");
 192       if (UserTag == UTag && VirtReg == VReg &&
 193           LiveUnion == LIU && !LIU->changedSince(Tag)) {
 194         // Retain cached results, e.g. firstInterference.
 195         return;
 196       }
 197       clear();
 198       LiveUnion = LIU;
 199       VirtReg = VReg;
 200       Tag = LIU->getTag();
 201       UserTag = UTag;
 202     }
 203
 204     LiveInterval &virtReg() const {
 205       assert(VirtReg && "uninitialized");
 206       return *VirtReg;
 207     }
 208
 209     bool isInterference(const InterferenceResult &IR) const {
 210       if (IR.VirtRegI != VirtReg->end()) {
 211         assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
 212                "invalid segment iterators");
 213         return true;
 214       }
 215       return false;
 216     }
 217
 218     // Does this live virtual register interfere with the union?
 219     bool checkInterference() { return isInterference(firstInterference()); }
 220
 221     // Get the first pair of interfering segments, or a noninterfering result.
 222     // This initializes the firstInterference_ cache.
 223     const InterferenceResult &firstInterference();
 224
 225     // Treat the result as an iterator and advance to the next interfering pair
 226     // of segments. Visiting each unique interfering pairs means that the same
 227     // VirtReg or LiveUnion segment may be visited multiple times.
 228     bool nextInterference(InterferenceResult &IR) const;
 229
 230     // Count the virtual registers in this union that interfere with this
 231     // query's live virtual register, up to maxInterferingRegs.
 232     unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
 233
 234     // Was this virtual register visited during collectInterferingVRegs?
 235     bool isSeenInterference(LiveInterval *VReg) const;
 236
 237     // Did collectInterferingVRegs collect all interferences?
 238     bool seenAllInterferences() const { return SeenAllInterferences; }
 239
 240     // Did collectInterferingVRegs encounter an unspillable vreg?
 241     bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
 242
 243     // Vector generated by collectInterferingVRegs.
 244     const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
 245       return InterferingVRegs;
 246     }
 247
 248     /// checkLoopInterference - Return true if there is interference overlapping
 249     /// Loop.
 250     bool checkLoopInterference(MachineLoopRange*);
 251
 252     void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
 253   private:
 254     Query(const Query&);          // DO NOT IMPLEMENT
 255     void operator=(const Query&); // DO NOT IMPLEMENT
 256
 257     // Private interface for queries
 258     void findIntersection(InterferenceResult &IR) const;
 259   };
 260 };
 261
 262 } // end namespace llvm
 263
 264 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)