lib/CodeGen/RegisterClassInfo.h

   1 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the RegisterClassInfo class which provides dynamic
  11 // information about target register classes. Callee saved and reserved
  12 // registers depends on calling conventions and other dynamic information, so
  13 // some things cannot be determined statically.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
  18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
  19
  20 #include "llvm/ADT/ArrayRef.h"
  21 #include "llvm/ADT/BitVector.h"
  22 #include "llvm/ADT/OwningPtr.h"
  23 #include "llvm/Target/TargetRegisterInfo.h"
  24
  25 namespace llvm {
  26
  27 class RegisterClassInfo {
  28   struct RCInfo {
  29     unsigned Tag;
  30     unsigned NumRegs;
  31     OwningArrayPtr<unsigned> Order;
  32
  33     RCInfo() : Tag(0), NumRegs(0) {}
  34     operator ArrayRef<unsigned>() const {
  35       return ArrayRef<unsigned>(Order.get(), NumRegs);
  36     }
  37   };
  38
  39   // Brief cached information for each register class.
  40   OwningArrayPtr<RCInfo> RegClass;
  41
  42   // Tag changes whenever cached information needs to be recomputed. An RCInfo
  43   // entry is valid when its tag matches.
  44   unsigned Tag;
  45
  46   const MachineFunction *MF;
  47   const TargetRegisterInfo *TRI;
  48
  49   // Callee saved registers of last MF. Assumed to be valid until the next
  50   // runOnFunction() call.
  51   const unsigned *CalleeSaved;
  52
  53   // Map register number to CalleeSaved index + 1;
  54   SmallVector<uint8_t, 4> CSRNum;
  55
  56   // Reserved registers in the current MF.
  57   BitVector Reserved;
  58
  59   // Compute all information about RC.
  60   void compute(const TargetRegisterClass *RC) const;
  61
  62   // Return an up-to-date RCInfo for RC.
  63   const RCInfo &get(const TargetRegisterClass *RC) const {
  64     const RCInfo &RCI = RegClass[RC->getID()];
  65     if (Tag != RCI.Tag)
  66       compute(RC);
  67     return RCI;
  68   }
  69
  70 public:
  71   RegisterClassInfo();
  72
  73   /// runOnFunction - Prepare to answer questions about MF. This must be called
  74   /// before any other methods are used.
  75   void runOnMachineFunction(const MachineFunction &MF);
  76
  77   /// getNumAllocatableRegs - Returns the number of actually allocatable
  78   /// registers in RC in the current function.
  79   unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
  80     return get(RC).NumRegs;
  81   }
  82
  83   /// getOrder - Returns the preferred allocation order for RC. The order
  84   /// contains no reserved registers, and registers that alias callee saved
  85   /// registers come last.
  86   ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
  87     return get(RC);
  88   }
  89
  90   /// getLastCalleeSavedAlias - Returns the last callee saved register that
  91   /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
  92   unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
  93     assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
  94     if (unsigned N = CSRNum[PhysReg])
  95       return CalleeSaved[N-1];
  96     return 0;
  97   }
  98
  99   /// isReserved - Returns true when PhysReg is a reserved register.
 100   ///
 101   /// Reserved registers may belong to an allocatable register class, but the
 102   /// target has explicitly requested that they are not used.
 103   ///
 104   bool isReserved(unsigned PhysReg) const {
 105     return Reserved.test(PhysReg);
 106   }
 107
 108   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
 109   /// register class and it hasn't been reserved.
 110   ///
 111   /// Allocatable registers may show up in the allocation order of some virtual
 112   /// register, so a register allocator needs to track its liveness and
 113   /// availability.
 114   bool isAllocatable(unsigned PhysReg) const {
 115     return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
 116   }
 117 };
 118 } // end namespace llvm
 119
 120 #endif
 121