lib/Target/Alpha/AlphaRegisterInfo.cpp

   1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "reginfo"
  15 #include "Alpha.h"
  16 #include "AlphaRegisterInfo.h"
  17 #include "llvm/Constants.h"
  18 #include "llvm/Type.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/ValueTypes.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/MachineFrameInfo.h"
  24 #include "llvm/CodeGen/MachineLocation.h"
  25 #include "llvm/Target/TargetFrameLowering.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Target/TargetOptions.h"
  28 #include "llvm/Target/TargetInstrInfo.h"
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Support/Debug.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Support/raw_ostream.h"
  33 #include "llvm/ADT/BitVector.h"
  34 #include "llvm/ADT/STLExtras.h"
  35 #include <cstdlib>
  36
  37 #define GET_REGINFO_MC_DESC
  38 #define GET_REGINFO_TARGET_DESC
  39 #include "AlphaGenRegisterInfo.inc"
  40
  41 using namespace llvm;
  42
  43 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
  44   : AlphaGenRegisterInfo(),
  45     TII(tii) {
  46 }
  47
  48 static long getUpper16(long l) {
  49   long y = l / Alpha::IMM_MULT;
  50   if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
  51     ++y;
  52   return y;
  53 }
  54
  55 static long getLower16(long l) {
  56   long h = getUpper16(l);
  57   return l - h * Alpha::IMM_MULT;
  58 }
  59
  60 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  61                                                                          const {
  62   static const unsigned CalleeSavedRegs[] = {
  63     Alpha::R9, Alpha::R10,
  64     Alpha::R11, Alpha::R12,
  65     Alpha::R13, Alpha::R14,
  66     Alpha::F2, Alpha::F3,
  67     Alpha::F4, Alpha::F5,
  68     Alpha::F6, Alpha::F7,
  69     Alpha::F8, Alpha::F9,  0
  70   };
  71   return CalleeSavedRegs;
  72 }
  73
  74 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  75   BitVector Reserved(getNumRegs());
  76   Reserved.set(Alpha::R15);
  77   Reserved.set(Alpha::R29);
  78   Reserved.set(Alpha::R30);
  79   Reserved.set(Alpha::R31);
  80   return Reserved;
  81 }
  82
  83 //===----------------------------------------------------------------------===//
  84 // Stack Frame Processing methods
  85 //===----------------------------------------------------------------------===//
  86
  87 void AlphaRegisterInfo::
  88 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  89                               MachineBasicBlock::iterator I) const {
  90   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
  91
  92   if (TFI->hasFP(MF)) {
  93     // If we have a frame pointer, turn the adjcallstackup instruction into a
  94     // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
  95     // <amt>'
  96     MachineInstr *Old = I;
  97     uint64_t Amount = Old->getOperand(0).getImm();
  98     if (Amount != 0) {
  99       // We need to keep the stack aligned properly.  To do this, we round the
 100       // amount of space needed for the outgoing arguments up to the next
 101       // alignment boundary.
 102       unsigned Align = TFI->getStackAlignment();
 103       Amount = (Amount+Align-1)/Align*Align;
 104
 105       MachineInstr *New;
 106       if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
 107         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
 108           .addImm(-Amount).addReg(Alpha::R30);
 109       } else {
 110          assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
 111          New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
 112           .addImm(Amount).addReg(Alpha::R30);
 113       }
 114
 115       // Replace the pseudo instruction with a new instruction...
 116       MBB.insert(I, New);
 117     }
 118   }
 119
 120   MBB.erase(I);
 121 }
 122
 123 //Alpha has a slightly funny stack:
 124 //Args
 125 //<- incoming SP
 126 //fixed locals (and spills, callee saved, etc)
 127 //<- FP
 128 //variable locals
 129 //<- SP
 130
 131 void
 132 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 133                                        int SPAdj, RegScavenger *RS) const {
 134   assert(SPAdj == 0 && "Unexpected");
 135
 136   unsigned i = 0;
 137   MachineInstr &MI = *II;
 138   MachineBasicBlock &MBB = *MI.getParent();
 139   MachineFunction &MF = *MBB.getParent();
 140   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 141
 142   bool FP = TFI->hasFP(MF);
 143
 144   while (!MI.getOperand(i).isFI()) {
 145     ++i;
 146     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 147   }
 148
 149   int FrameIndex = MI.getOperand(i).getIndex();
 150
 151   // Add the base register of R30 (SP) or R15 (FP).
 152   MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
 153
 154   // Now add the frame object offset to the offset from the virtual frame index.
 155   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 156
 157   DEBUG(errs() << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
 158
 159   Offset += MF.getFrameInfo()->getStackSize();
 160
 161   DEBUG(errs() << "Corrected Offset " << Offset
 162        << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
 163
 164   if (Offset > Alpha::IMM_HIGH || Offset < Alpha::IMM_LOW) {
 165     DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
 166           << Offset << "\n");
 167     //so in this case, we need to use a temporary register, and move the
 168     //original inst off the SP/FP
 169     //fix up the old:
 170     MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
 171     MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
 172     //insert the new
 173     MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(),
 174                               TII.get(Alpha::LDAH), Alpha::R28)
 175       .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
 176     MBB.insert(II, nMI);
 177   } else {
 178     MI.getOperand(i).ChangeToImmediate(Offset);
 179   }
 180 }
 181
 182 unsigned AlphaRegisterInfo::getRARegister() const {
 183   return Alpha::R26;
 184 }
 185
 186 unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 187   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
 188
 189   return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
 190 }
 191
 192 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
 193   llvm_unreachable("What is the exception register");
 194   return 0;
 195 }
 196
 197 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
 198   llvm_unreachable("What is the exception handler register");
 199   return 0;
 200 }
 201
 202 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 203   llvm_unreachable("What is the dwarf register number");
 204   return -1;
 205 }
 206
 207 int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
 208   llvm_unreachable("What is the dwarf register number");
 209   return -1;
 210 }
 211
 212 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 213 {
 214   std::string s(AlphaRegDesc[reg].Name);
 215   return s;
 216 }