lib/Target/CellSPU/SPUFrameLowering.h

   1 //=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains CellSPU frame information that doesn't fit anywhere else
  11 // cleanly...
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPU_FRAMEINFO_H
  16 #define SPU_FRAMEINFO_H
  17
  18 #include "SPURegisterInfo.h"
  19 #include "llvm/Target/TargetFrameLowering.h"
  20 #include "llvm/Target/TargetMachine.h"
  21
  22 namespace llvm {
  23   class SPUSubtarget;
  24
  25   class SPUFrameLowering: public TargetFrameLowering {
  26     const SPUSubtarget &Subtarget;
  27     std::pair<unsigned, int> LR[1];
  28
  29   public:
  30     SPUFrameLowering(const SPUSubtarget &sti);
  31
  32     //! Determine the frame's layour
  33     void determineFrameLayout(MachineFunction &MF) const;
  34
  35     /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
  36     /// the function.
  37     void emitPrologue(MachineFunction &MF) const;
  38     void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
  39
  40     //! Prediate: Target has dedicated frame pointer
  41     bool hasFP(const MachineFunction &MF) const;
  42
  43     void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
  44                                               RegScavenger *RS = NULL) const;
  45
  46     //! Perform target-specific stack frame setup.
  47     void getInitialFrameState(std::vector<MachineMove> &Moves) const;
  48
  49     //! Return a function's saved spill slots
  50     /*!
  51       For CellSPU, a function's saved spill slots is just the link register.
  52      */
  53     const std::pair<unsigned, int> *
  54     getCalleeSaveSpillSlots(unsigned &NumEntries) const;
  55
  56     //! Stack slot size (16 bytes)
  57     static int stackSlotSize() {
  58       return 16;
  59     }
  60     //! Maximum frame offset representable by a signed 10-bit integer
  61     /*!
  62       This is the maximum frame offset that can be expressed as a 10-bit
  63       integer, used in D-form addresses.
  64      */
  65     static int maxFrameOffset() {
  66       return ((1 << 9) - 1) * stackSlotSize();
  67     }
  68     //! Minimum frame offset representable by a signed 10-bit integer
  69     static int minFrameOffset() {
  70       return -(1 << 9) * stackSlotSize();
  71     }
  72     //! Minimum frame size (enough to spill LR + SP)
  73     static int minStackSize() {
  74       return (2 * stackSlotSize());
  75     }
  76     //! Convert frame index to stack offset
  77     static int FItoStackOffset(int frame_index) {
  78       return frame_index * stackSlotSize();
  79     }
  80     //! Number of instructions required to overcome hint-for-branch latency
  81     /*!
  82       HBR (hint-for-branch) instructions can be inserted when, for example,
  83       we know that a given function is going to be called, such as printf(),
  84       in the control flow graph. HBRs are only inserted if a sufficient number
  85       of instructions occurs between the HBR and the target. Currently, HBRs
  86       take 6 cycles, ergo, the magic number 6.
  87      */
  88     static int branchHintPenalty() {
  89       return 6;
  90     }
  91   };
  92 }
  93
  94 #endif