lib/Target/CellSPU/SPUISelDAGToDAG.cpp

   1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for the Cell SPU,
  11 // converting from a legalized dag to a SPU-target dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SPU.h"
  16 #include "SPUTargetMachine.h"
  17 #include "SPUHazardRecognizers.h"
  18 #include "SPUFrameLowering.h"
  19 #include "SPURegisterNames.h"
  20 #include "SPUTargetMachine.h"
  21 #include "llvm/CodeGen/MachineConstantPool.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineFunction.h"
  24 #include "llvm/CodeGen/SelectionDAG.h"
  25 #include "llvm/CodeGen/SelectionDAGISel.h"
  26 #include "llvm/CodeGen/PseudoSourceValue.h"
  27 #include "llvm/Target/TargetOptions.h"
  28 #include "llvm/ADT/Statistic.h"
  29 #include "llvm/Constants.h"
  30 #include "llvm/GlobalValue.h"
  31 #include "llvm/Intrinsics.h"
  32 #include "llvm/LLVMContext.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/MathExtras.h"
  36 #include "llvm/Support/Compiler.h"
  37 #include "llvm/Support/raw_ostream.h"
  38
  39 using namespace llvm;
  40
  41 namespace {
  42   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
  43   bool
  44   isI32IntS10Immediate(ConstantSDNode *CN)
  45   {
  46     return isInt<10>(CN->getSExtValue());
  47   }
  48
  49   //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
  50   bool
  51   isI32IntU10Immediate(ConstantSDNode *CN)
  52   {
  53     return isUInt<10>(CN->getSExtValue());
  54   }
  55
  56   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
  57   bool
  58   isI16IntS10Immediate(ConstantSDNode *CN)
  59   {
  60     return isInt<10>(CN->getSExtValue());
  61   }
  62
  63   //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
  64   bool
  65   isI16IntU10Immediate(ConstantSDNode *CN)
  66   {
  67     return isUInt<10>((short) CN->getZExtValue());
  68   }
  69
  70   //! ConstantSDNode predicate for signed 16-bit values
  71   /*!
  72     \arg CN The constant SelectionDAG node holding the value
  73     \arg Imm The returned 16-bit value, if returning true
  74
  75     This predicate tests the value in \a CN to see whether it can be
  76     represented as a 16-bit, sign-extended quantity. Returns true if
  77     this is the case.
  78    */
  79   bool
  80   isIntS16Immediate(ConstantSDNode *CN, short &Imm)
  81   {
  82     EVT vt = CN->getValueType(0);
  83     Imm = (short) CN->getZExtValue();
  84     if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
  85       return true;
  86     } else if (vt == MVT::i32) {
  87       int32_t i_val = (int32_t) CN->getZExtValue();
  88       short s_val = (short) i_val;
  89       return i_val == s_val;
  90     } else {
  91       int64_t i_val = (int64_t) CN->getZExtValue();
  92       short s_val = (short) i_val;
  93       return i_val == s_val;
  94     }
  95
  96     return false;
  97   }
  98
  99   //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
 100   static bool
 101   isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
 102   {
 103     EVT vt = FPN->getValueType(0);
 104     if (vt == MVT::f32) {
 105       int val = FloatToBits(FPN->getValueAPF().convertToFloat());
 106       int sval = (int) ((val << 16) >> 16);
 107       Imm = (short) val;
 108       return val == sval;
 109     }
 110
 111     return false;
 112   }
 113
 114   //! Generate the carry-generate shuffle mask.
 115   SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 116     SmallVector<SDValue, 16 > ShufBytes;
 117
 118     // Create the shuffle mask for "rotating" the borrow up one register slot
 119     // once the borrow is generated.
 120     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 121     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 122     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 123     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 124
 125     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 126                        &ShufBytes[0], ShufBytes.size());
 127   }
 128
 129   //! Generate the borrow-generate shuffle mask
 130   SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 131     SmallVector<SDValue, 16 > ShufBytes;
 132
 133     // Create the shuffle mask for "rotating" the borrow up one register slot
 134     // once the borrow is generated.
 135     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 136     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 137     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 138     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 139
 140     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 141                        &ShufBytes[0], ShufBytes.size());
 142   }
 143
 144   //===------------------------------------------------------------------===//
 145   /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
 146   /// instructions for SelectionDAG operations.
 147   ///
 148   class SPUDAGToDAGISel :
 149     public SelectionDAGISel
 150   {
 151     const SPUTargetMachine &TM;
 152     const SPUTargetLowering &SPUtli;
 153     unsigned GlobalBaseReg;
 154
 155   public:
 156     explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
 157       SelectionDAGISel(tm),
 158       TM(tm),
 159       SPUtli(*tm.getTargetLowering())
 160     { }
 161
 162     virtual bool runOnMachineFunction(MachineFunction &MF) {
 163       // Make sure we re-emit a set of the global base reg if necessary
 164       GlobalBaseReg = 0;
 165       SelectionDAGISel::runOnMachineFunction(MF);
 166       return true;
 167     }
 168
 169     /// getI32Imm - Return a target constant with the specified value, of type
 170     /// i32.
 171     inline SDValue getI32Imm(uint32_t Imm) {
 172       return CurDAG->getTargetConstant(Imm, MVT::i32);
 173     }
 174
 175     /// getSmallIPtrImm - Return a target constant of pointer type.
 176     inline SDValue getSmallIPtrImm(unsigned Imm) {
 177       return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
 178     }
 179
 180     SDNode *emitBuildVector(SDNode *bvNode) {
 181       EVT vecVT = bvNode->getValueType(0);
 182       DebugLoc dl = bvNode->getDebugLoc();
 183
 184       // Check to see if this vector can be represented as a CellSPU immediate
 185       // constant by invoking all of the instruction selection predicates:
 186       if (((vecVT == MVT::v8i16) &&
 187            (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
 188           ((vecVT == MVT::v4i32) &&
 189            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 190             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 191             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 192             (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
 193           ((vecVT == MVT::v2i64) &&
 194            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 195             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 196             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
 197         HandleSDNode Dummy(SDValue(bvNode, 0));
 198         if (SDNode *N = Select(bvNode))
 199           return N;
 200         return Dummy.getValue().getNode();
 201       }
 202
 203       // No, need to emit a constant pool spill:
 204       std::vector<Constant*> CV;
 205
 206       for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
 207         ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
 208         CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
 209       }
 210
 211       const Constant *CP = ConstantVector::get(CV);
 212       SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
 213       unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
 214       SDValue CGPoolOffset =
 215               SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
 216
 217       HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
 218                                          CurDAG->getEntryNode(), CGPoolOffset,
 219                                          MachinePointerInfo::getConstantPool(),
 220                                          false, false, Alignment));
 221       CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
 222       if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
 223         return N;
 224       return Dummy.getValue().getNode();
 225     }
 226
 227     /// Select - Convert the specified operand from a target-independent to a
 228     /// target-specific node if it hasn't already been changed.
 229     SDNode *Select(SDNode *N);
 230
 231     //! Emit the instruction sequence for i64 shl
 232     SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
 233
 234     //! Emit the instruction sequence for i64 srl
 235     SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
 236
 237     //! Emit the instruction sequence for i64 sra
 238     SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
 239
 240     //! Emit the necessary sequence for loading i64 constants:
 241     SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
 242
 243     //! Alternate instruction emit sequence for loading i64 constants
 244     SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
 245
 246     //! Returns true if the address N is an A-form (local store) address
 247     bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 248                          SDValue &Index);
 249
 250     //! D-form address predicate
 251     bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 252                          SDValue &Index);
 253
 254     /// Alternate D-form address using i7 offset predicate
 255     bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
 256                           SDValue &Base);
 257
 258     /// D-form address selection workhorse
 259     bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
 260                                SDValue &Base, int minOffset, int maxOffset);
 261
 262     //! Address predicate if N can be expressed as an indexed [r+r] operation.
 263     bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 264                          SDValue &Index);
 265
 266     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 267     /// inline asm expressions.
 268     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 269                                               char ConstraintCode,
 270                                               std::vector<SDValue> &OutOps) {
 271       SDValue Op0, Op1;
 272       switch (ConstraintCode) {
 273       default: return true;
 274       case 'm':   // memory
 275         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
 276             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
 277           SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
 278         break;
 279       case 'o':   // offsetable
 280         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
 281             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
 282           Op0 = Op;
 283           Op1 = getSmallIPtrImm(0);
 284         }
 285         break;
 286       case 'v':   // not offsetable
 287 #if 1
 288         llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
 289 #else
 290         SelectAddrIdxOnly(Op, Op, Op0, Op1);
 291 #endif
 292         break;
 293       }
 294
 295       OutOps.push_back(Op0);
 296       OutOps.push_back(Op1);
 297       return false;
 298     }
 299
 300     virtual const char *getPassName() const {
 301       return "Cell SPU DAG->DAG Pattern Instruction Selection";
 302     }
 303
 304   private:
 305     SDValue getRC( MVT );
 306
 307     // Include the pieces autogenerated from the target description.
 308 #include "SPUGenDAGISel.inc"
 309   };
 310 }
 311
 312 /*!
 313  \arg Op The ISD instruction operand
 314  \arg N The address to be tested
 315  \arg Base The base address
 316  \arg Index The base address index
 317  */
 318 bool
 319 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 320                     SDValue &Index) {
 321   // These match the addr256k operand type:
 322   EVT OffsVT = MVT::i16;
 323   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
 324   int64_t val;
 325
 326   switch (N.getOpcode()) {
 327   case ISD::Constant:
 328     val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
 329     Base = CurDAG->getTargetConstant( val , MVT::i32);
 330     Index = Zero;
 331     return true; break;
 332   case ISD::ConstantPool:
 333   case ISD::GlobalAddress:
 334     report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
 335     /*NOTREACHED*/
 336
 337   case ISD::TargetConstant:
 338   case ISD::TargetGlobalAddress:
 339   case ISD::TargetJumpTable:
 340     report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
 341                       "not wrapped as A-form address.");
 342     /*NOTREACHED*/
 343
 344   case SPUISD::AFormAddr:
 345     // Just load from memory if there's only a single use of the location,
 346     // otherwise, this will get handled below with D-form offset addresses
 347     if (N.hasOneUse()) {
 348       SDValue Op0 = N.getOperand(0);
 349       switch (Op0.getOpcode()) {
 350       case ISD::TargetConstantPool:
 351       case ISD::TargetJumpTable:
 352         Base = Op0;
 353         Index = Zero;
 354         return true;
 355
 356       case ISD::TargetGlobalAddress: {
 357         GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
 358         const GlobalValue *GV = GSDN->getGlobal();
 359         if (GV->getAlignment() == 16) {
 360           Base = Op0;
 361           Index = Zero;
 362           return true;
 363         }
 364         break;
 365       }
 366       }
 367     }
 368     break;
 369   }
 370   return false;
 371 }
 372
 373 bool
 374 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
 375                                   SDValue &Base) {
 376   const int minDForm2Offset = -(1 << 7);
 377   const int maxDForm2Offset = (1 << 7) - 1;
 378   return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
 379                                maxDForm2Offset);
 380 }
 381
 382 /*!
 383   \arg Op The ISD instruction (ignored)
 384   \arg N The address to be tested
 385   \arg Base Base address register/pointer
 386   \arg Index Base address index
 387
 388   Examine the input address by a base register plus a signed 10-bit
 389   displacement, [r+I10] (D-form address).
 390
 391   \return true if \a N is a D-form address with \a Base and \a Index set
 392   to non-empty SDValue instances.
 393 */
 394 bool
 395 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 396                                  SDValue &Index) {
 397   return DFormAddressPredicate(Op, N, Base, Index,
 398                                SPUFrameLowering::minFrameOffset(),
 399                                SPUFrameLowering::maxFrameOffset());
 400 }
 401
 402 bool
 403 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
 404                                       SDValue &Index, int minOffset,
 405                                       int maxOffset) {
 406   unsigned Opc = N.getOpcode();
 407   EVT PtrTy = SPUtli.getPointerTy();
 408
 409   if (Opc == ISD::FrameIndex) {
 410     // Stack frame index must be less than 512 (divided by 16):
 411     FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
 412     int FI = int(FIN->getIndex());
 413     DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
 414                << FI << "\n");
 415     if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
 416       Base = CurDAG->getTargetConstant(0, PtrTy);
 417       Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 418       return true;
 419     }
 420   } else if (Opc == ISD::ADD) {
 421     // Generated by getelementptr
 422     const SDValue Op0 = N.getOperand(0);
 423     const SDValue Op1 = N.getOperand(1);
 424
 425     if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
 426         || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
 427       Base = CurDAG->getTargetConstant(0, PtrTy);
 428       Index = N;
 429       return true;
 430     } else if (Op1.getOpcode() == ISD::Constant
 431                || Op1.getOpcode() == ISD::TargetConstant) {
 432       ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 433       int32_t offset = int32_t(CN->getSExtValue());
 434
 435       if (Op0.getOpcode() == ISD::FrameIndex) {
 436         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
 437         int FI = int(FIN->getIndex());
 438         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
 439                    << " frame index = " << FI << "\n");
 440
 441         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
 442           Base = CurDAG->getTargetConstant(offset, PtrTy);
 443           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 444           return true;
 445         }
 446       } else if (offset > minOffset && offset < maxOffset) {
 447         Base = CurDAG->getTargetConstant(offset, PtrTy);
 448         Index = Op0;
 449         return true;
 450       }
 451     } else if (Op0.getOpcode() == ISD::Constant
 452                || Op0.getOpcode() == ISD::TargetConstant) {
 453       ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
 454       int32_t offset = int32_t(CN->getSExtValue());
 455
 456       if (Op1.getOpcode() == ISD::FrameIndex) {
 457         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
 458         int FI = int(FIN->getIndex());
 459         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
 460                    << " frame index = " << FI << "\n");
 461
 462         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
 463           Base = CurDAG->getTargetConstant(offset, PtrTy);
 464           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 465           return true;
 466         }
 467       } else if (offset > minOffset && offset < maxOffset) {
 468         Base = CurDAG->getTargetConstant(offset, PtrTy);
 469         Index = Op1;
 470         return true;
 471       }
 472     }
 473   } else if (Opc == SPUISD::IndirectAddr) {
 474     // Indirect with constant offset -> D-Form address
 475     const SDValue Op0 = N.getOperand(0);
 476     const SDValue Op1 = N.getOperand(1);
 477
 478     if (Op0.getOpcode() == SPUISD::Hi
 479         && Op1.getOpcode() == SPUISD::Lo) {
 480       // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
 481       Base = CurDAG->getTargetConstant(0, PtrTy);
 482       Index = N;
 483       return true;
 484     } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
 485       int32_t offset = 0;
 486       SDValue idxOp;
 487
 488       if (isa<ConstantSDNode>(Op1)) {
 489         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 490         offset = int32_t(CN->getSExtValue());
 491         idxOp = Op0;
 492       } else if (isa<ConstantSDNode>(Op0)) {
 493         ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
 494         offset = int32_t(CN->getSExtValue());
 495         idxOp = Op1;
 496       }
 497
 498       if (offset >= minOffset && offset <= maxOffset) {
 499         Base = CurDAG->getTargetConstant(offset, PtrTy);
 500         Index = idxOp;
 501         return true;
 502       }
 503     }
 504   } else if (Opc == SPUISD::AFormAddr) {
 505     Base = CurDAG->getTargetConstant(0, N.getValueType());
 506     Index = N;
 507     return true;
 508   } else if (Opc == SPUISD::LDRESULT) {
 509     Base = CurDAG->getTargetConstant(0, N.getValueType());
 510     Index = N;
 511     return true;
 512   } else if (Opc == ISD::Register
 513            ||Opc == ISD::CopyFromReg
 514            ||Opc == ISD::UNDEF
 515            ||Opc == ISD::Constant) {
 516     unsigned OpOpc = Op->getOpcode();
 517
 518     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
 519       // Direct load/store without getelementptr
 520       SDValue Offs;
 521
 522       Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
 523
 524       if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
 525         if (Offs.getOpcode() == ISD::UNDEF)
 526           Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
 527
 528         Base = Offs;
 529         Index = N;
 530         return true;
 531       }
 532     } else {
 533       /* If otherwise unadorned, default to D-form address with 0 offset: */
 534       if (Opc == ISD::CopyFromReg) {
 535         Index = N.getOperand(1);
 536       } else {
 537         Index = N;
 538       }
 539
 540       Base = CurDAG->getTargetConstant(0, Index.getValueType());
 541       return true;
 542     }
 543   }
 544
 545   return false;
 546 }
 547
 548 /*!
 549   \arg Op The ISD instruction operand
 550   \arg N The address operand
 551   \arg Base The base pointer operand
 552   \arg Index The offset/index operand
 553
 554   If the address \a N can be expressed as an A-form or D-form address, returns
 555   false.  Otherwise, creates two operands, Base and Index that will become the
 556   (r)(r) X-form address.
 557 */
 558 bool
 559 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
 560                                  SDValue &Index) {
 561   if (!SelectAFormAddr(Op, N, Base, Index)
 562       && !SelectDFormAddr(Op, N, Base, Index)) {
 563     // If the address is neither A-form or D-form, punt and use an X-form
 564     // address:
 565     Base = N.getOperand(1);
 566     Index = N.getOperand(0);
 567     return true;
 568   }
 569
 570   return false;
 571 }
 572
 573 /*!
 574  Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue
 575  to be used as the last parameter of a
 576 CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call
 577  \arg VT the value type for which we want a register class
 578 */
 579 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
 580   switch( VT.SimpleTy ) {
 581   case MVT::i8:
 582     return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
 583     break;
 584   case MVT::i16:
 585     return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
 586     break;
 587   case MVT::i32:
 588     return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
 589     break;
 590   case MVT::f32:
 591     return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
 592     break;
 593   case MVT::i64:
 594     return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
 595     break;
 596   case MVT::i128:
 597     return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
 598     break;
 599   case MVT::v16i8:
 600   case MVT::v8i16:
 601   case MVT::v4i32:
 602   case MVT::v4f32:
 603   case MVT::v2i64:
 604   case MVT::v2f64:
 605     return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
 606     break;
 607   default:
 608     assert( false && "add a new case here" );
 609   }
 610   return SDValue();
 611 }
 612
 613 //! Convert the operand from a target-independent to a target-specific node
 614 /*!
 615  */
 616 SDNode *
 617 SPUDAGToDAGISel::Select(SDNode *N) {
 618   unsigned Opc = N->getOpcode();
 619   int n_ops = -1;
 620   unsigned NewOpc = 0;
 621   EVT OpVT = N->getValueType(0);
 622   SDValue Ops[8];
 623   DebugLoc dl = N->getDebugLoc();
 624
 625   if (N->isMachineOpcode())
 626     return NULL;   // Already selected.
 627
 628   if (Opc == ISD::FrameIndex) {
 629     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 630     SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
 631     SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
 632
 633     if (FI < 128) {
 634       NewOpc = SPU::AIr32;
 635       Ops[0] = TFI;
 636       Ops[1] = Imm0;
 637       n_ops = 2;
 638     } else {
 639       NewOpc = SPU::Ar32;
 640       Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
 641       Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
 642                                               N->getValueType(0), TFI),
 643                        0);
 644       n_ops = 2;
 645     }
 646   } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
 647     // Catch the i64 constants that end up here. Note: The backend doesn't
 648     // attempt to legalize the constant (it's useless because DAGCombiner
 649     // will insert 64-bit constants and we can't stop it).
 650     return SelectI64Constant(N, OpVT, N->getDebugLoc());
 651   } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
 652              && OpVT == MVT::i64) {
 653     SDValue Op0 = N->getOperand(0);
 654     EVT Op0VT = Op0.getValueType();
 655     EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
 656                                     Op0VT, (128 / Op0VT.getSizeInBits()));
 657     EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
 658                                    OpVT, (128 / OpVT.getSizeInBits()));
 659     SDValue shufMask;
 660
 661     switch (Op0VT.getSimpleVT().SimpleTy) {
 662     default:
 663       report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
 664       /*NOTREACHED*/
 665     case MVT::i32:
 666       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 667                                  CurDAG->getConstant(0x80808080, MVT::i32),
 668                                  CurDAG->getConstant(0x00010203, MVT::i32),
 669                                  CurDAG->getConstant(0x80808080, MVT::i32),
 670                                  CurDAG->getConstant(0x08090a0b, MVT::i32));
 671       break;
 672
 673     case MVT::i16:
 674       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 675                                  CurDAG->getConstant(0x80808080, MVT::i32),
 676                                  CurDAG->getConstant(0x80800203, MVT::i32),
 677                                  CurDAG->getConstant(0x80808080, MVT::i32),
 678                                  CurDAG->getConstant(0x80800a0b, MVT::i32));
 679       break;
 680
 681     case MVT::i8:
 682       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 683                                  CurDAG->getConstant(0x80808080, MVT::i32),
 684                                  CurDAG->getConstant(0x80808003, MVT::i32),
 685                                  CurDAG->getConstant(0x80808080, MVT::i32),
 686                                  CurDAG->getConstant(0x8080800b, MVT::i32));
 687       break;
 688     }
 689
 690     SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
 691
 692     HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
 693                                                Op0VecVT, Op0));
 694
 695     SDValue PromScalar;
 696     if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
 697       PromScalar = SDValue(N, 0);
 698     else
 699       PromScalar = PromoteScalar.getValue();
 700
 701     SDValue zextShuffle =
 702             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
 703                             PromScalar, PromScalar,
 704                             SDValue(shufMaskLoad, 0));
 705
 706     HandleSDNode Dummy2(zextShuffle);
 707     if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
 708       zextShuffle = SDValue(N, 0);
 709     else
 710       zextShuffle = Dummy2.getValue();
 711     HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
 712                                        zextShuffle));
 713
 714     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
 715     SelectCode(Dummy.getValue().getNode());
 716     return Dummy.getValue().getNode();
 717   } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 718     SDNode *CGLoad =
 719             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
 720
 721     HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
 722                                        N->getOperand(0), N->getOperand(1),
 723                                        SDValue(CGLoad, 0)));
 724
 725     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
 726     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
 727       return N;
 728     return Dummy.getValue().getNode();
 729   } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 730     SDNode *CGLoad =
 731             emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
 732
 733     HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
 734                                        N->getOperand(0), N->getOperand(1),
 735                                        SDValue(CGLoad, 0)));
 736
 737     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
 738     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
 739       return N;
 740     return Dummy.getValue().getNode();
 741   } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 742     SDNode *CGLoad =
 743             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
 744
 745     HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
 746                                        N->getOperand(0), N->getOperand(1),
 747                                        SDValue(CGLoad, 0)));
 748     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
 749     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
 750       return N;
 751     return Dummy.getValue().getNode();
 752   } else if (Opc == ISD::TRUNCATE) {
 753     SDValue Op0 = N->getOperand(0);
 754     if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
 755         && OpVT == MVT::i32
 756         && Op0.getValueType() == MVT::i64) {
 757       // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
 758       //
 759       // Take advantage of the fact that the upper 32 bits are in the
 760       // i32 preferred slot and avoid shuffle gymnastics:
 761       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
 762       if (CN != 0) {
 763         unsigned shift_amt = unsigned(CN->getZExtValue());
 764
 765         if (shift_amt >= 32) {
 766           SDNode *hi32 =
 767                   CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
 768                                          Op0.getOperand(0), getRC(MVT::i32));
 769
 770           shift_amt -= 32;
 771           if (shift_amt > 0) {
 772             // Take care of the additional shift, if present:
 773             SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
 774             unsigned Opc = SPU::ROTMAIr32_i32;
 775
 776             if (Op0.getOpcode() == ISD::SRL)
 777               Opc = SPU::ROTMr32;
 778
 779             hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
 780                                           shift);
 781           }
 782
 783           return hi32;
 784         }
 785       }
 786     }
 787   } else if (Opc == ISD::SHL) {
 788     if (OpVT == MVT::i64)
 789       return SelectSHLi64(N, OpVT);
 790   } else if (Opc == ISD::SRL) {
 791     if (OpVT == MVT::i64)
 792       return SelectSRLi64(N, OpVT);
 793   } else if (Opc == ISD::SRA) {
 794     if (OpVT == MVT::i64)
 795       return SelectSRAi64(N, OpVT);
 796   } else if (Opc == ISD::FNEG
 797              && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
 798     DebugLoc dl = N->getDebugLoc();
 799     // Check if the pattern is a special form of DFNMS:
 800     // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
 801     SDValue Op0 = N->getOperand(0);
 802     if (Op0.getOpcode() == ISD::FSUB) {
 803       SDValue Op00 = Op0.getOperand(0);
 804       if (Op00.getOpcode() == ISD::FMUL) {
 805         unsigned Opc = SPU::DFNMSf64;
 806         if (OpVT == MVT::v2f64)
 807           Opc = SPU::DFNMSv2f64;
 808
 809         return CurDAG->getMachineNode(Opc, dl, OpVT,
 810                                       Op00.getOperand(0),
 811                                       Op00.getOperand(1),
 812                                       Op0.getOperand(1));
 813       }
 814     }
 815
 816     SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
 817     SDNode *signMask = 0;
 818     unsigned Opc = SPU::XORfneg64;
 819
 820     if (OpVT == MVT::f64) {
 821       signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
 822     } else if (OpVT == MVT::v2f64) {
 823       Opc = SPU::XORfnegvec;
 824       signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
 825                                                  MVT::v2i64,
 826                                                  negConst, negConst).getNode());
 827     }
 828
 829     return CurDAG->getMachineNode(Opc, dl, OpVT,
 830                                   N->getOperand(0), SDValue(signMask, 0));
 831   } else if (Opc == ISD::FABS) {
 832     if (OpVT == MVT::f64) {
 833       SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
 834       return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
 835                                     N->getOperand(0), SDValue(signMask, 0));
 836     } else if (OpVT == MVT::v2f64) {
 837       SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
 838       SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
 839                                        absConst, absConst);
 840       SDNode *signMask = emitBuildVector(absVec.getNode());
 841       return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
 842                                     N->getOperand(0), SDValue(signMask, 0));
 843     }
 844   } else if (Opc == SPUISD::LDRESULT) {
 845     // Custom select instructions for LDRESULT
 846     EVT VT = N->getValueType(0);
 847     SDValue Arg = N->getOperand(0);
 848     SDValue Chain = N->getOperand(1);
 849     SDNode *Result;
 850
 851     Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
 852                                     MVT::Other, Arg,
 853                                     getRC( VT.getSimpleVT()), Chain);
 854     return Result;
 855
 856   } else if (Opc == SPUISD::IndirectAddr) {
 857     // Look at the operands: SelectCode() will catch the cases that aren't
 858     // specifically handled here.
 859     //
 860     // SPUInstrInfo catches the following patterns:
 861     // (SPUindirect (SPUhi ...), (SPUlo ...))
 862     // (SPUindirect $sp, imm)
 863     EVT VT = N->getValueType(0);
 864     SDValue Op0 = N->getOperand(0);
 865     SDValue Op1 = N->getOperand(1);
 866     RegisterSDNode *RN;
 867
 868     if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
 869         || (Op0.getOpcode() == ISD::Register
 870             && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
 871                 && RN->getReg() != SPU::R1))) {
 872       NewOpc = SPU::Ar32;
 873       Ops[1] = Op1;
 874       if (Op1.getOpcode() == ISD::Constant) {
 875         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 876         Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
 877         if (isInt<10>(CN->getSExtValue())) {
 878           NewOpc = SPU::AIr32;
 879           Ops[1] = Op1;
 880         } else {
 881           Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
 882                                                   N->getValueType(0),
 883                                                   Op1),
 884                            0);
 885         }
 886       }
 887       Ops[0] = Op0;
 888       n_ops = 2;
 889     }
 890   }
 891
 892   if (n_ops > 0) {
 893     if (N->hasOneUse())
 894       return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
 895     else
 896       return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
 897   } else
 898     return SelectCode(N);
 899 }
 900
 901 /*!
 902  * Emit the instruction sequence for i64 left shifts. The basic algorithm
 903  * is to fill the bottom two word slots with zeros so that zeros are shifted
 904  * in as the entire quadword is shifted left.
 905  *
 906  * \note This code could also be used to implement v2i64 shl.
 907  *
 908  * @param Op The shl operand
 909  * @param OpVT Op's machine value value type (doesn't need to be passed, but
 910  * makes life easier.)
 911  * @return The SDNode with the entire instruction sequence
 912  */
 913 SDNode *
 914 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
 915   SDValue Op0 = N->getOperand(0);
 916   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
 917                                OpVT, (128 / OpVT.getSizeInBits()));
 918   SDValue ShiftAmt = N->getOperand(1);
 919   EVT ShiftAmtVT = ShiftAmt.getValueType();
 920   SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
 921   SDValue SelMaskVal;
 922   DebugLoc dl = N->getDebugLoc();
 923
 924   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
 925                                   Op0, getRC(MVT::v2i64) );
 926   SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
 927   SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
 928   ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
 929                                     CurDAG->getTargetConstant(0, OpVT));
 930   VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
 931                                   SDValue(ZeroFill, 0),
 932                                   SDValue(VecOp0, 0),
 933                                   SDValue(SelMask, 0));
 934
 935   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
 936     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
 937     unsigned bits = unsigned(CN->getZExtValue()) & 7;
 938
 939     if (bytes > 0) {
 940       Shift =
 941         CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
 942                                SDValue(VecOp0, 0),
 943                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
 944     }
 945
 946     if (bits > 0) {
 947       Shift =
 948         CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
 949                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
 950                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
 951     }
 952   } else {
 953     SDNode *Bytes =
 954       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
 955                              ShiftAmt,
 956                              CurDAG->getTargetConstant(3, ShiftAmtVT));
 957     SDNode *Bits =
 958       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
 959                              ShiftAmt,
 960                              CurDAG->getTargetConstant(7, ShiftAmtVT));
 961     Shift =
 962       CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
 963                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
 964     Shift =
 965       CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
 966                              SDValue(Shift, 0), SDValue(Bits, 0));
 967   }
 968
 969   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
 970                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
 971 }
 972
 973 /*!
 974  * Emit the instruction sequence for i64 logical right shifts.
 975  *
 976  * @param Op The shl operand
 977  * @param OpVT Op's machine value value type (doesn't need to be passed, but
 978  * makes life easier.)
 979  * @return The SDNode with the entire instruction sequence
 980  */
 981 SDNode *
 982 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
 983   SDValue Op0 = N->getOperand(0);
 984   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
 985                                OpVT, (128 / OpVT.getSizeInBits()));
 986   SDValue ShiftAmt = N->getOperand(1);
 987   EVT ShiftAmtVT = ShiftAmt.getValueType();
 988   SDNode *VecOp0, *Shift = 0;
 989   DebugLoc dl = N->getDebugLoc();
 990
 991   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
 992                                   Op0, getRC(MVT::v2i64) );
 993
 994   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
 995     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
 996     unsigned bits = unsigned(CN->getZExtValue()) & 7;
 997
 998     if (bytes > 0) {
 999       Shift =
1000         CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1001                                SDValue(VecOp0, 0),
1002                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1003     }
1004
1005     if (bits > 0) {
1006       Shift =
1007         CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1008                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
1009                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
1010     }
1011   } else {
1012     SDNode *Bytes =
1013       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1014                              ShiftAmt,
1015                              CurDAG->getTargetConstant(3, ShiftAmtVT));
1016     SDNode *Bits =
1017       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1018                              ShiftAmt,
1019                              CurDAG->getTargetConstant(7, ShiftAmtVT));
1020
1021     // Ensure that the shift amounts are negated!
1022     Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1023                                    SDValue(Bytes, 0),
1024                                    CurDAG->getTargetConstant(0, ShiftAmtVT));
1025
1026     Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1027                                   SDValue(Bits, 0),
1028                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
1029
1030     Shift =
1031       CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1032                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
1033     Shift =
1034       CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1035                              SDValue(Shift, 0), SDValue(Bits, 0));
1036   }
1037
1038   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1039                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1040 }
1041
1042 /*!
1043  * Emit the instruction sequence for i64 arithmetic right shifts.
1044  *
1045  * @param Op The shl operand
1046  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1047  * makes life easier.)
1048  * @return The SDNode with the entire instruction sequence
1049  */
1050 SDNode *
1051 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1052   // Promote Op0 to vector
1053   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1054                                OpVT, (128 / OpVT.getSizeInBits()));
1055   SDValue ShiftAmt = N->getOperand(1);
1056   EVT ShiftAmtVT = ShiftAmt.getValueType();
1057   DebugLoc dl = N->getDebugLoc();
1058
1059   SDNode *VecOp0 =
1060     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1061                            VecVT, N->getOperand(0), getRC(MVT::v2i64));
1062
1063   SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1064   SDNode *SignRot =
1065     CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1066                            SDValue(VecOp0, 0), SignRotAmt);
1067   SDNode *UpperHalfSign =
1068     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1069                            MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32));
1070
1071   SDNode *UpperHalfSignMask =
1072     CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1073   SDNode *UpperLowerMask =
1074     CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1075                            CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1076   SDNode *UpperLowerSelect =
1077     CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1078                            SDValue(UpperHalfSignMask, 0),
1079                            SDValue(VecOp0, 0),
1080                            SDValue(UpperLowerMask, 0));
1081
1082   SDNode *Shift = 0;
1083
1084   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1085     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1086     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1087
1088     if (bytes > 0) {
1089       bytes = 31 - bytes;
1090       Shift =
1091         CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1092                                SDValue(UpperLowerSelect, 0),
1093                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1094     }
1095
1096     if (bits > 0) {
1097       bits = 8 - bits;
1098       Shift =
1099         CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1100                                SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1101                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
1102     }
1103   } else {
1104     SDNode *NegShift =
1105       CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1106                              ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1107
1108     Shift =
1109       CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1110                              SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1111     Shift =
1112       CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1113                              SDValue(Shift, 0), SDValue(NegShift, 0));
1114   }
1115
1116   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1117                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1118 }
1119
1120 /*!
1121  Do the necessary magic necessary to load a i64 constant
1122  */
1123 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1124                                            DebugLoc dl) {
1125   ConstantSDNode *CN = cast<ConstantSDNode>(N);
1126   return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1127 }
1128
1129 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1130                                            DebugLoc dl) {
1131   EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1132   SDValue i64vec =
1133           SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1134
1135   // Here's where it gets interesting, because we have to parse out the
1136   // subtree handed back in i64vec:
1137
1138   if (i64vec.getOpcode() == ISD::BITCAST) {
1139     // The degenerate case where the upper and lower bits in the splat are
1140     // identical:
1141     SDValue Op0 = i64vec.getOperand(0);
1142
1143     ReplaceUses(i64vec, Op0);
1144     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1145                                   SDValue(emitBuildVector(Op0.getNode()), 0),
1146                                   getRC(MVT::i64));
1147   } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1148     SDValue lhs = i64vec.getOperand(0);
1149     SDValue rhs = i64vec.getOperand(1);
1150     SDValue shufmask = i64vec.getOperand(2);
1151
1152     if (lhs.getOpcode() == ISD::BITCAST) {
1153       ReplaceUses(lhs, lhs.getOperand(0));
1154       lhs = lhs.getOperand(0);
1155     }
1156
1157     SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1158                        ? lhs.getNode()
1159                        : emitBuildVector(lhs.getNode()));
1160
1161     if (rhs.getOpcode() == ISD::BITCAST) {
1162       ReplaceUses(rhs, rhs.getOperand(0));
1163       rhs = rhs.getOperand(0);
1164     }
1165
1166     SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1167                        ? rhs.getNode()
1168                        : emitBuildVector(rhs.getNode()));
1169
1170     if (shufmask.getOpcode() == ISD::BITCAST) {
1171       ReplaceUses(shufmask, shufmask.getOperand(0));
1172       shufmask = shufmask.getOperand(0);
1173     }
1174
1175     SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1176                             ? shufmask.getNode()
1177                             : emitBuildVector(shufmask.getNode()));
1178
1179    SDValue shufNode =
1180             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1181                                    SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1182                                    SDValue(shufMaskNode, 0));
1183     HandleSDNode Dummy(shufNode);
1184     SDNode *SN = SelectCode(Dummy.getValue().getNode());
1185     if (SN == 0) SN = Dummy.getValue().getNode();
1186
1187     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1188                                   OpVT, SDValue(SN, 0), getRC(MVT::i64));
1189   } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1190     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1191                                   SDValue(emitBuildVector(i64vec.getNode()), 0),
1192                                   getRC(MVT::i64));
1193   } else {
1194     report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1195                       "condition");
1196   }
1197 }
1198
1199 /// createSPUISelDag - This pass converts a legalized DAG into a
1200 /// SPU-specific DAG, ready for instruction scheduling.
1201 ///
1202 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1203   return new SPUDAGToDAGISel(TM);
1204 }