lib/Target/CellSPU/SPURegisterInfo.cpp

   1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Cell implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "reginfo"
  15 #include "SPU.h"
  16 #include "SPURegisterInfo.h"
  17 #include "SPURegisterNames.h"
  18 #include "SPUInstrBuilder.h"
  19 #include "SPUSubtarget.h"
  20 #include "SPUMachineFunction.h"
  21 #include "SPUFrameLowering.h"
  22 #include "llvm/Constants.h"
  23 #include "llvm/Type.h"
  24 #include "llvm/CodeGen/ValueTypes.h"
  25 #include "llvm/CodeGen/MachineInstrBuilder.h"
  26 #include "llvm/CodeGen/MachineModuleInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineFrameInfo.h"
  29 #include "llvm/CodeGen/MachineLocation.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/RegisterScavenging.h"
  32 #include "llvm/CodeGen/ValueTypes.h"
  33 #include "llvm/Target/TargetFrameLowering.h"
  34 #include "llvm/Target/TargetInstrInfo.h"
  35 #include "llvm/Target/TargetMachine.h"
  36 #include "llvm/Target/TargetOptions.h"
  37 #include "llvm/Support/CommandLine.h"
  38 #include "llvm/Support/Debug.h"
  39 #include "llvm/Support/ErrorHandling.h"
  40 #include "llvm/Support/MathExtras.h"
  41 #include "llvm/Support/raw_ostream.h"
  42 #include "llvm/ADT/BitVector.h"
  43 #include "llvm/ADT/STLExtras.h"
  44 #include <cstdlib>
  45
  46 #define GET_REGINFO_MC_DESC
  47 #define GET_REGINFO_TARGET_DESC
  48 #include "SPUGenRegisterInfo.inc"
  49
  50 using namespace llvm;
  51
  52 /// getRegisterNumbering - Given the enum value for some register, e.g.
  53 /// PPC::F14, return the number that it corresponds to (e.g. 14).
  54 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
  55   using namespace SPU;
  56   switch (RegEnum) {
  57   case SPU::R0: return 0;
  58   case SPU::R1: return 1;
  59   case SPU::R2: return 2;
  60   case SPU::R3: return 3;
  61   case SPU::R4: return 4;
  62   case SPU::R5: return 5;
  63   case SPU::R6: return 6;
  64   case SPU::R7: return 7;
  65   case SPU::R8: return 8;
  66   case SPU::R9: return 9;
  67   case SPU::R10: return 10;
  68   case SPU::R11: return 11;
  69   case SPU::R12: return 12;
  70   case SPU::R13: return 13;
  71   case SPU::R14: return 14;
  72   case SPU::R15: return 15;
  73   case SPU::R16: return 16;
  74   case SPU::R17: return 17;
  75   case SPU::R18: return 18;
  76   case SPU::R19: return 19;
  77   case SPU::R20: return 20;
  78   case SPU::R21: return 21;
  79   case SPU::R22: return 22;
  80   case SPU::R23: return 23;
  81   case SPU::R24: return 24;
  82   case SPU::R25: return 25;
  83   case SPU::R26: return 26;
  84   case SPU::R27: return 27;
  85   case SPU::R28: return 28;
  86   case SPU::R29: return 29;
  87   case SPU::R30: return 30;
  88   case SPU::R31: return 31;
  89   case SPU::R32: return 32;
  90   case SPU::R33: return 33;
  91   case SPU::R34: return 34;
  92   case SPU::R35: return 35;
  93   case SPU::R36: return 36;
  94   case SPU::R37: return 37;
  95   case SPU::R38: return 38;
  96   case SPU::R39: return 39;
  97   case SPU::R40: return 40;
  98   case SPU::R41: return 41;
  99   case SPU::R42: return 42;
 100   case SPU::R43: return 43;
 101   case SPU::R44: return 44;
 102   case SPU::R45: return 45;
 103   case SPU::R46: return 46;
 104   case SPU::R47: return 47;
 105   case SPU::R48: return 48;
 106   case SPU::R49: return 49;
 107   case SPU::R50: return 50;
 108   case SPU::R51: return 51;
 109   case SPU::R52: return 52;
 110   case SPU::R53: return 53;
 111   case SPU::R54: return 54;
 112   case SPU::R55: return 55;
 113   case SPU::R56: return 56;
 114   case SPU::R57: return 57;
 115   case SPU::R58: return 58;
 116   case SPU::R59: return 59;
 117   case SPU::R60: return 60;
 118   case SPU::R61: return 61;
 119   case SPU::R62: return 62;
 120   case SPU::R63: return 63;
 121   case SPU::R64: return 64;
 122   case SPU::R65: return 65;
 123   case SPU::R66: return 66;
 124   case SPU::R67: return 67;
 125   case SPU::R68: return 68;
 126   case SPU::R69: return 69;
 127   case SPU::R70: return 70;
 128   case SPU::R71: return 71;
 129   case SPU::R72: return 72;
 130   case SPU::R73: return 73;
 131   case SPU::R74: return 74;
 132   case SPU::R75: return 75;
 133   case SPU::R76: return 76;
 134   case SPU::R77: return 77;
 135   case SPU::R78: return 78;
 136   case SPU::R79: return 79;
 137   case SPU::R80: return 80;
 138   case SPU::R81: return 81;
 139   case SPU::R82: return 82;
 140   case SPU::R83: return 83;
 141   case SPU::R84: return 84;
 142   case SPU::R85: return 85;
 143   case SPU::R86: return 86;
 144   case SPU::R87: return 87;
 145   case SPU::R88: return 88;
 146   case SPU::R89: return 89;
 147   case SPU::R90: return 90;
 148   case SPU::R91: return 91;
 149   case SPU::R92: return 92;
 150   case SPU::R93: return 93;
 151   case SPU::R94: return 94;
 152   case SPU::R95: return 95;
 153   case SPU::R96: return 96;
 154   case SPU::R97: return 97;
 155   case SPU::R98: return 98;
 156   case SPU::R99: return 99;
 157   case SPU::R100: return 100;
 158   case SPU::R101: return 101;
 159   case SPU::R102: return 102;
 160   case SPU::R103: return 103;
 161   case SPU::R104: return 104;
 162   case SPU::R105: return 105;
 163   case SPU::R106: return 106;
 164   case SPU::R107: return 107;
 165   case SPU::R108: return 108;
 166   case SPU::R109: return 109;
 167   case SPU::R110: return 110;
 168   case SPU::R111: return 111;
 169   case SPU::R112: return 112;
 170   case SPU::R113: return 113;
 171   case SPU::R114: return 114;
 172   case SPU::R115: return 115;
 173   case SPU::R116: return 116;
 174   case SPU::R117: return 117;
 175   case SPU::R118: return 118;
 176   case SPU::R119: return 119;
 177   case SPU::R120: return 120;
 178   case SPU::R121: return 121;
 179   case SPU::R122: return 122;
 180   case SPU::R123: return 123;
 181   case SPU::R124: return 124;
 182   case SPU::R125: return 125;
 183   case SPU::R126: return 126;
 184   case SPU::R127: return 127;
 185   default:
 186     report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
 187   }
 188 }
 189
 190 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
 191                                  const TargetInstrInfo &tii) :
 192   SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii)
 193 {
 194 }
 195
 196 /// getPointerRegClass - Return the register class to use to hold pointers.
 197 /// This is used for addressing modes.
 198 const TargetRegisterClass *
 199 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
 200   return &SPU::R32CRegClass;
 201 }
 202
 203 const unsigned *
 204 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
 205 {
 206   // Cell ABI calling convention
 207   static const unsigned SPU_CalleeSaveRegs[] = {
 208     SPU::R80, SPU::R81, SPU::R82, SPU::R83,
 209     SPU::R84, SPU::R85, SPU::R86, SPU::R87,
 210     SPU::R88, SPU::R89, SPU::R90, SPU::R91,
 211     SPU::R92, SPU::R93, SPU::R94, SPU::R95,
 212     SPU::R96, SPU::R97, SPU::R98, SPU::R99,
 213     SPU::R100, SPU::R101, SPU::R102, SPU::R103,
 214     SPU::R104, SPU::R105, SPU::R106, SPU::R107,
 215     SPU::R108, SPU::R109, SPU::R110, SPU::R111,
 216     SPU::R112, SPU::R113, SPU::R114, SPU::R115,
 217     SPU::R116, SPU::R117, SPU::R118, SPU::R119,
 218     SPU::R120, SPU::R121, SPU::R122, SPU::R123,
 219     SPU::R124, SPU::R125, SPU::R126, SPU::R127,
 220     SPU::R2,    /* environment pointer */
 221     SPU::R1,    /* stack pointer */
 222     SPU::R0,    /* link register */
 223     0 /* end */
 224   };
 225
 226   return SPU_CalleeSaveRegs;
 227 }
 228
 229 /*!
 230  R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
 231  generally unused) are the Cell's reserved registers
 232  */
 233 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 234   BitVector Reserved(getNumRegs());
 235   Reserved.set(SPU::R0);                // LR
 236   Reserved.set(SPU::R1);                // SP
 237   Reserved.set(SPU::R2);                // environment pointer
 238   return Reserved;
 239 }
 240
 241 //===----------------------------------------------------------------------===//
 242 // Stack Frame Processing methods
 243 //===----------------------------------------------------------------------===//
 244
 245 //--------------------------------------------------------------------------
 246 void
 247 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
 248                                                MachineBasicBlock &MBB,
 249                                                MachineBasicBlock::iterator I)
 250   const
 251 {
 252   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
 253   MBB.erase(I);
 254 }
 255
 256 void
 257 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 258                                      RegScavenger *RS) const
 259 {
 260   unsigned i = 0;
 261   MachineInstr &MI = *II;
 262   MachineBasicBlock &MBB = *MI.getParent();
 263   MachineFunction &MF = *MBB.getParent();
 264   MachineFrameInfo *MFI = MF.getFrameInfo();
 265   DebugLoc dl = II->getDebugLoc();
 266
 267   while (!MI.getOperand(i).isFI()) {
 268     ++i;
 269     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 270   }
 271
 272   MachineOperand &SPOp = MI.getOperand(i);
 273   int FrameIndex = SPOp.getIndex();
 274
 275   // Now add the frame object offset to the offset from r1.
 276   int Offset = MFI->getObjectOffset(FrameIndex);
 277
 278   // Most instructions, except for generated FrameIndex additions using AIr32
 279   // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
 280   // immediate in operand 2.
 281   unsigned OpNo = 1;
 282   if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
 283     OpNo = 2;
 284
 285   MachineOperand &MO = MI.getOperand(OpNo);
 286
 287   // Offset is biased by $lr's slot at the bottom.
 288   Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize();
 289   assert((Offset & 0xf) == 0
 290          && "16-byte alignment violated in eliminateFrameIndex");
 291
 292   // Replace the FrameIndex with base register with $sp (aka $r1)
 293   SPOp.ChangeToRegister(SPU::R1, false);
 294
 295   // if 'Offset' doesn't fit to the D-form instruction's
 296   // immediate, convert the instruction to X-form
 297   // if the instruction is not an AI (which takes a s10 immediate), assume
 298   // it is a load/store that can take a s14 immediate
 299   if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
 300       || !isInt<14>(Offset)) {
 301     int newOpcode = convertDFormToXForm(MI.getOpcode());
 302     unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
 303     BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
 304         .addImm(Offset);
 305     BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
 306         .addReg(tmpReg, RegState::Kill)
 307         .addReg(SPU::R1);
 308     // remove the replaced D-form instruction
 309     MBB.erase(II);
 310   } else {
 311     MO.ChangeToImmediate(Offset);
 312   }
 313 }
 314
 315 unsigned
 316 SPURegisterInfo::getRARegister() const
 317 {
 318   return SPU::R0;
 319 }
 320
 321 unsigned
 322 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
 323 {
 324   return SPU::R1;
 325 }
 326
 327 int
 328 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 329   // FIXME: Most probably dwarf numbers differs for Linux and Darwin
 330   return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 331 }
 332
 333 int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
 334   return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
 335 }
 336
 337 int
 338 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
 339 {
 340   switch(dFormOpcode)
 341   {
 342     case SPU::AIr32:     return SPU::Ar32;
 343     case SPU::LQDr32:    return SPU::LQXr32;
 344     case SPU::LQDr128:   return SPU::LQXr128;
 345     case SPU::LQDv16i8:  return SPU::LQXv16i8;
 346     case SPU::LQDv4i32:  return SPU::LQXv4i32;
 347     case SPU::LQDv4f32:  return SPU::LQXv4f32;
 348     case SPU::STQDr32:   return SPU::STQXr32;
 349     case SPU::STQDr128:  return SPU::STQXr128;
 350     case SPU::STQDv16i8: return SPU::STQXv16i8;
 351     case SPU::STQDv4i32: return SPU::STQXv4i32;
 352     case SPU::STQDv4f32: return SPU::STQXv4f32;
 353
 354     default: assert( false && "Unhandled D to X-form conversion");
 355   }
 356   // default will assert, but need to return something to keep the
 357   // compiler happy.
 358   return dFormOpcode;
 359 }
 360
 361 // TODO this is already copied from PPC. Could this convenience function
 362 // be moved to the RegScavenger class?
 363 unsigned
 364 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
 365                                      RegScavenger *RS,
 366                                      const TargetRegisterClass *RC,
 367                                      int SPAdj) const
 368 {
 369   assert(RS && "Register scavenging must be on");
 370   unsigned Reg = RS->FindUnusedReg(RC);
 371   if (Reg == 0)
 372     Reg = RS->scavengeRegister(RC, II, SPAdj);
 373   assert( Reg && "Register scavenger failed");
 374   return Reg;
 375 }