lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp

   1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file includes code for rendering MCInst instances as AT&T-style
  11 // assembly.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "asm-printer"
  16 #include "X86IntelInstPrinter.h"
  17 #include "X86InstComments.h"
  18 #include "MCTargetDesc/X86MCTargetDesc.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCAsmInfo.h"
  21 #include "llvm/MC/MCExpr.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23 #include "llvm/Support/FormattedStream.h"
  24 #include <cctype>
  25 using namespace llvm;
  26
  27 // Include the auto-generated portion of the assembly writer.
  28 #define GET_INSTRUCTION_NAME
  29 #include "X86GenAsmWriter1.inc"
  30
  31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
  32   OS << getRegisterName(RegNo);
  33 }
  34
  35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
  36   printInstruction(MI, OS);
  37
  38   // If verbose assembly is enabled, we can print some informative comments.
  39   if (CommentStream)
  40     EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
  41 }
  42 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
  43   return getInstructionName(Opcode);
  44 }
  45
  46 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
  47                                      raw_ostream &O) {
  48   switch (MI->getOperand(Op).getImm()) {
  49   default: assert(0 && "Invalid ssecc argument!");
  50   case 0: O << "eq"; break;
  51   case 1: O << "lt"; break;
  52   case 2: O << "le"; break;
  53   case 3: O << "unord"; break;
  54   case 4: O << "neq"; break;
  55   case 5: O << "nlt"; break;
  56   case 6: O << "nle"; break;
  57   case 7: O << "ord"; break;
  58   }
  59 }
  60
  61 /// print_pcrel_imm - This is used to print an immediate value that ends up
  62 /// being encoded as a pc-relative value.
  63 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
  64                                           raw_ostream &O) {
  65   const MCOperand &Op = MI->getOperand(OpNo);
  66   if (Op.isImm())
  67     O << Op.getImm();
  68   else {
  69     assert(Op.isExpr() && "unknown pcrel immediate operand");
  70     O << *Op.getExpr();
  71   }
  72 }
  73
  74 static void PrintRegName(raw_ostream &O, StringRef RegName) {
  75   for (unsigned i = 0, e = RegName.size(); i != e; ++i)
  76     O << (char)toupper(RegName[i]);
  77 }
  78
  79 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
  80                                        raw_ostream &O) {
  81   const MCOperand &Op = MI->getOperand(OpNo);
  82   if (Op.isReg()) {
  83     PrintRegName(O, getRegisterName(Op.getReg()));
  84   } else if (Op.isImm()) {
  85     O << Op.getImm();
  86   } else {
  87     assert(Op.isExpr() && "unknown operand kind in printOperand");
  88     O << *Op.getExpr();
  89   }
  90 }
  91
  92 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
  93                                             raw_ostream &O) {
  94   const MCOperand &BaseReg  = MI->getOperand(Op);
  95   unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
  96   const MCOperand &IndexReg = MI->getOperand(Op+2);
  97   const MCOperand &DispSpec = MI->getOperand(Op+3);
  98   const MCOperand &SegReg   = MI->getOperand(Op+4);
  99
 100   // If this has a segment register, print it.
 101   if (SegReg.getReg()) {
 102     printOperand(MI, Op+4, O);
 103     O << ':';
 104   }
 105
 106   O << '[';
 107
 108   bool NeedPlus = false;
 109   if (BaseReg.getReg()) {
 110     printOperand(MI, Op, O);
 111     NeedPlus = true;
 112   }
 113
 114   if (IndexReg.getReg()) {
 115     if (NeedPlus) O << " + ";
 116     if (ScaleVal != 1)
 117       O << ScaleVal << '*';
 118     printOperand(MI, Op+2, O);
 119     NeedPlus = true;
 120   }
 121
 122
 123   if (!DispSpec.isImm()) {
 124     if (NeedPlus) O << " + ";
 125     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
 126     O << *DispSpec.getExpr();
 127   } else {
 128     int64_t DispVal = DispSpec.getImm();
 129     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
 130       if (NeedPlus) {
 131         if (DispVal > 0)
 132           O << " + ";
 133         else {
 134           O << " - ";
 135           DispVal = -DispVal;
 136         }
 137       }
 138       O << DispVal;
 139     }
 140   }
 141
 142   O << ']';
 143 }