lib/Target/X86/X86AsmBackend.cpp

   1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/Target/TargetAsmBackend.h"
  11 #include "X86.h"
  12 #include "X86FixupKinds.h"
  13 #include "llvm/ADT/Twine.h"
  14 #include "llvm/MC/MCAssembler.h"
  15 #include "llvm/MC/MCELFObjectWriter.h"
  16 #include "llvm/MC/MCExpr.h"
  17 #include "llvm/MC/MCFixupKindInfo.h"
  18 #include "llvm/MC/MCMachObjectWriter.h"
  19 #include "llvm/MC/MCObjectWriter.h"
  20 #include "llvm/MC/MCSectionCOFF.h"
  21 #include "llvm/MC/MCSectionELF.h"
  22 #include "llvm/MC/MCSectionMachO.h"
  23 #include "llvm/Object/MachOFormat.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/ELF.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/raw_ostream.h"
  28 #include "llvm/Target/TargetRegistry.h"
  29 #include "llvm/Target/TargetAsmBackend.h"
  30 using namespace llvm;
  31
  32 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
  33 // is useful when running bitwise comparison experiments on Darwin. We should be
  34 // able to remove this once PR9807 is resolved.
  35 static cl::opt<bool>
  36 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
  37          cl::desc("Disable relaxation of arithmetic instruction for X86"));
  38
  39 static unsigned getFixupKindLog2Size(unsigned Kind) {
  40   switch (Kind) {
  41   default: assert(0 && "invalid fixup kind!");
  42   case FK_PCRel_1:
  43   case FK_Data_1: return 0;
  44   case FK_PCRel_2:
  45   case FK_Data_2: return 1;
  46   case FK_PCRel_4:
  47   case X86::reloc_riprel_4byte:
  48   case X86::reloc_riprel_4byte_movq_load:
  49   case X86::reloc_signed_4byte:
  50   case X86::reloc_global_offset_table:
  51   case FK_Data_4: return 2;
  52   case FK_PCRel_8:
  53   case FK_Data_8: return 3;
  54   }
  55 }
  56
  57 namespace {
  58
  59 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
  60 public:
  61   X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
  62                      bool HasRelocationAddend)
  63     : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
  64 };
  65
  66 class X86AsmBackend : public TargetAsmBackend {
  67 public:
  68   X86AsmBackend(const Target &T)
  69     : TargetAsmBackend() {}
  70
  71   unsigned getNumFixupKinds() const {
  72     return X86::NumTargetFixupKinds;
  73   }
  74
  75   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
  76     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
  77       { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
  78       { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
  79       { "reloc_signed_4byte", 0, 4 * 8, 0},
  80       { "reloc_global_offset_table", 0, 4 * 8, 0}
  81     };
  82
  83     if (Kind < FirstTargetFixupKind)
  84       return TargetAsmBackend::getFixupKindInfo(Kind);
  85
  86     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
  87            "Invalid kind!");
  88     return Infos[Kind - FirstTargetFixupKind];
  89   }
  90
  91   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
  92                   uint64_t Value) const {
  93     unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
  94
  95     assert(Fixup.getOffset() + Size <= DataSize &&
  96            "Invalid fixup offset!");
  97     for (unsigned i = 0; i != Size; ++i)
  98       Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
  99   }
 100
 101   bool MayNeedRelaxation(const MCInst &Inst) const;
 102
 103   void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
 104
 105   bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
 106 };
 107 } // end anonymous namespace
 108
 109 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
 110   switch (Op) {
 111   default:
 112     return Op;
 113
 114   case X86::JAE_1: return X86::JAE_4;
 115   case X86::JA_1:  return X86::JA_4;
 116   case X86::JBE_1: return X86::JBE_4;
 117   case X86::JB_1:  return X86::JB_4;
 118   case X86::JE_1:  return X86::JE_4;
 119   case X86::JGE_1: return X86::JGE_4;
 120   case X86::JG_1:  return X86::JG_4;
 121   case X86::JLE_1: return X86::JLE_4;
 122   case X86::JL_1:  return X86::JL_4;
 123   case X86::JMP_1: return X86::JMP_4;
 124   case X86::JNE_1: return X86::JNE_4;
 125   case X86::JNO_1: return X86::JNO_4;
 126   case X86::JNP_1: return X86::JNP_4;
 127   case X86::JNS_1: return X86::JNS_4;
 128   case X86::JO_1:  return X86::JO_4;
 129   case X86::JP_1:  return X86::JP_4;
 130   case X86::JS_1:  return X86::JS_4;
 131   }
 132 }
 133
 134 static unsigned getRelaxedOpcodeArith(unsigned Op) {
 135   switch (Op) {
 136   default:
 137     return Op;
 138
 139     // IMUL
 140   case X86::IMUL16rri8: return X86::IMUL16rri;
 141   case X86::IMUL16rmi8: return X86::IMUL16rmi;
 142   case X86::IMUL32rri8: return X86::IMUL32rri;
 143   case X86::IMUL32rmi8: return X86::IMUL32rmi;
 144   case X86::IMUL64rri8: return X86::IMUL64rri32;
 145   case X86::IMUL64rmi8: return X86::IMUL64rmi32;
 146
 147     // AND
 148   case X86::AND16ri8: return X86::AND16ri;
 149   case X86::AND16mi8: return X86::AND16mi;
 150   case X86::AND32ri8: return X86::AND32ri;
 151   case X86::AND32mi8: return X86::AND32mi;
 152   case X86::AND64ri8: return X86::AND64ri32;
 153   case X86::AND64mi8: return X86::AND64mi32;
 154
 155     // OR
 156   case X86::OR16ri8: return X86::OR16ri;
 157   case X86::OR16mi8: return X86::OR16mi;
 158   case X86::OR32ri8: return X86::OR32ri;
 159   case X86::OR32mi8: return X86::OR32mi;
 160   case X86::OR64ri8: return X86::OR64ri32;
 161   case X86::OR64mi8: return X86::OR64mi32;
 162
 163     // XOR
 164   case X86::XOR16ri8: return X86::XOR16ri;
 165   case X86::XOR16mi8: return X86::XOR16mi;
 166   case X86::XOR32ri8: return X86::XOR32ri;
 167   case X86::XOR32mi8: return X86::XOR32mi;
 168   case X86::XOR64ri8: return X86::XOR64ri32;
 169   case X86::XOR64mi8: return X86::XOR64mi32;
 170
 171     // ADD
 172   case X86::ADD16ri8: return X86::ADD16ri;
 173   case X86::ADD16mi8: return X86::ADD16mi;
 174   case X86::ADD32ri8: return X86::ADD32ri;
 175   case X86::ADD32mi8: return X86::ADD32mi;
 176   case X86::ADD64ri8: return X86::ADD64ri32;
 177   case X86::ADD64mi8: return X86::ADD64mi32;
 178
 179     // SUB
 180   case X86::SUB16ri8: return X86::SUB16ri;
 181   case X86::SUB16mi8: return X86::SUB16mi;
 182   case X86::SUB32ri8: return X86::SUB32ri;
 183   case X86::SUB32mi8: return X86::SUB32mi;
 184   case X86::SUB64ri8: return X86::SUB64ri32;
 185   case X86::SUB64mi8: return X86::SUB64mi32;
 186
 187     // CMP
 188   case X86::CMP16ri8: return X86::CMP16ri;
 189   case X86::CMP16mi8: return X86::CMP16mi;
 190   case X86::CMP32ri8: return X86::CMP32ri;
 191   case X86::CMP32mi8: return X86::CMP32mi;
 192   case X86::CMP64ri8: return X86::CMP64ri32;
 193   case X86::CMP64mi8: return X86::CMP64mi32;
 194
 195     // PUSH
 196   case X86::PUSHi8: return X86::PUSHi32;
 197   }
 198 }
 199
 200 static unsigned getRelaxedOpcode(unsigned Op) {
 201   unsigned R = getRelaxedOpcodeArith(Op);
 202   if (R != Op)
 203     return R;
 204   return getRelaxedOpcodeBranch(Op);
 205 }
 206
 207 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
 208   // Branches can always be relaxed.
 209   if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
 210     return true;
 211
 212   if (MCDisableArithRelaxation)
 213     return false;
 214
 215   // Check if this instruction is ever relaxable.
 216   if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
 217     return false;
 218
 219
 220   // Check if it has an expression and is not RIP relative.
 221   bool hasExp = false;
 222   bool hasRIP = false;
 223   for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
 224     const MCOperand &Op = Inst.getOperand(i);
 225     if (Op.isExpr())
 226       hasExp = true;
 227
 228     if (Op.isReg() && Op.getReg() == X86::RIP)
 229       hasRIP = true;
 230   }
 231
 232   // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
 233   // how we do relaxations?
 234   return hasExp && !hasRIP;
 235 }
 236
 237 // FIXME: Can tblgen help at all here to verify there aren't other instructions
 238 // we can relax?
 239 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
 240   // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
 241   unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
 242
 243   if (RelaxedOp == Inst.getOpcode()) {
 244     SmallString<256> Tmp;
 245     raw_svector_ostream OS(Tmp);
 246     Inst.dump_pretty(OS);
 247     OS << "\n";
 248     report_fatal_error("unexpected instruction to relax: " + OS.str());
 249   }
 250
 251   Res = Inst;
 252   Res.setOpcode(RelaxedOp);
 253 }
 254
 255 /// WriteNopData - Write optimal nops to the output file for the \arg Count
 256 /// bytes.  This returns the number of bytes written.  It may return 0 if
 257 /// the \arg Count is more than the maximum optimal nops.
 258 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
 259   static const uint8_t Nops[10][10] = {
 260     // nop
 261     {0x90},
 262     // xchg %ax,%ax
 263     {0x66, 0x90},
 264     // nopl (%[re]ax)
 265     {0x0f, 0x1f, 0x00},
 266     // nopl 0(%[re]ax)
 267     {0x0f, 0x1f, 0x40, 0x00},
 268     // nopl 0(%[re]ax,%[re]ax,1)
 269     {0x0f, 0x1f, 0x44, 0x00, 0x00},
 270     // nopw 0(%[re]ax,%[re]ax,1)
 271     {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
 272     // nopl 0L(%[re]ax)
 273     {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
 274     // nopl 0L(%[re]ax,%[re]ax,1)
 275     {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 276     // nopw 0L(%[re]ax,%[re]ax,1)
 277     {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 278     // nopw %cs:0L(%[re]ax,%[re]ax,1)
 279     {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
 280   };
 281
 282   // Write an optimal sequence for the first 15 bytes.
 283   const uint64_t OptimalCount = (Count < 16) ? Count : 15;
 284   const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
 285   for (uint64_t i = 0, e = Prefixes; i != e; i++)
 286     OW->Write8(0x66);
 287   const uint64_t Rest = OptimalCount - Prefixes;
 288   for (uint64_t i = 0, e = Rest; i != e; i++)
 289     OW->Write8(Nops[Rest - 1][i]);
 290
 291   // Finish with single byte nops.
 292   for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
 293    OW->Write8(0x90);
 294
 295   return true;
 296 }
 297
 298 /* *** */
 299
 300 namespace {
 301 class ELFX86AsmBackend : public X86AsmBackend {
 302 public:
 303   Triple::OSType OSType;
 304   ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
 305     : X86AsmBackend(T), OSType(_OSType) {
 306     HasReliableSymbolDifference = true;
 307   }
 308
 309   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
 310     const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
 311     return ES.getFlags() & ELF::SHF_MERGE;
 312   }
 313 };
 314
 315 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
 316 public:
 317   ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
 318     : ELFX86AsmBackend(T, OSType) {}
 319
 320   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 321     return createELFObjectWriter(createELFObjectTargetWriter(),
 322                                  OS, /*IsLittleEndian*/ true);
 323   }
 324
 325   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
 326     return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
 327   }
 328 };
 329
 330 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 331 public:
 332   ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
 333     : ELFX86AsmBackend(T, OSType) {}
 334
 335   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 336     return createELFObjectWriter(createELFObjectTargetWriter(),
 337                                  OS, /*IsLittleEndian*/ true);
 338   }
 339
 340   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
 341     return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
 342   }
 343 };
 344
 345 class WindowsX86AsmBackend : public X86AsmBackend {
 346   bool Is64Bit;
 347
 348 public:
 349   WindowsX86AsmBackend(const Target &T, bool is64Bit)
 350     : X86AsmBackend(T)
 351     , Is64Bit(is64Bit) {
 352   }
 353
 354   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 355     return createWinCOFFObjectWriter(OS, Is64Bit);
 356   }
 357 };
 358
 359 class DarwinX86AsmBackend : public X86AsmBackend {
 360 public:
 361   DarwinX86AsmBackend(const Target &T)
 362     : X86AsmBackend(T) { }
 363 };
 364
 365 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
 366 public:
 367   DarwinX86_32AsmBackend(const Target &T)
 368     : DarwinX86AsmBackend(T) {}
 369
 370   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 371     return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
 372                                      object::mach::CTM_i386,
 373                                      object::mach::CSX86_ALL);
 374   }
 375 };
 376
 377 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
 378 public:
 379   DarwinX86_64AsmBackend(const Target &T)
 380     : DarwinX86AsmBackend(T) {
 381     HasReliableSymbolDifference = true;
 382   }
 383
 384   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 385     return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
 386                                      object::mach::CTM_x86_64,
 387                                      object::mach::CSX86_ALL);
 388   }
 389
 390   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
 391     // Temporary labels in the string literals sections require symbols. The
 392     // issue is that the x86_64 relocation format does not allow symbol +
 393     // offset, and so the linker does not have enough information to resolve the
 394     // access to the appropriate atom unless an external relocation is used. For
 395     // non-cstring sections, we expect the compiler to use a non-temporary label
 396     // for anything that could have an addend pointing outside the symbol.
 397     //
 398     // See <rdar://problem/4765733>.
 399     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
 400     return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
 401   }
 402
 403   virtual bool isSectionAtomizable(const MCSection &Section) const {
 404     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
 405     // Fixed sized data sections are uniqued, they cannot be diced into atoms.
 406     switch (SMO.getType()) {
 407     default:
 408       return true;
 409
 410     case MCSectionMachO::S_4BYTE_LITERALS:
 411     case MCSectionMachO::S_8BYTE_LITERALS:
 412     case MCSectionMachO::S_16BYTE_LITERALS:
 413     case MCSectionMachO::S_LITERAL_POINTERS:
 414     case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
 415     case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
 416     case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
 417     case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
 418     case MCSectionMachO::S_INTERPOSING:
 419       return false;
 420     }
 421   }
 422 };
 423
 424 } // end anonymous namespace
 425
 426 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
 427                                                const std::string &TT) {
 428   Triple TheTriple(TT);
 429
 430   if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
 431     return new DarwinX86_32AsmBackend(T);
 432
 433   if (TheTriple.isOSWindows())
 434     return new WindowsX86AsmBackend(T, false);
 435
 436   return new ELFX86_32AsmBackend(T, TheTriple.getOS());
 437 }
 438
 439 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
 440                                                const std::string &TT) {
 441   Triple TheTriple(TT);
 442
 443   if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
 444     return new DarwinX86_64AsmBackend(T);
 445
 446   if (TheTriple.isOSWindows())
 447     return new WindowsX86AsmBackend(T, true);
 448
 449   return new ELFX86_64AsmBackend(T, TheTriple.getOS());
 450 }