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the various ConstantExpr::get*Ty methods existed to work with issues around
[llvm/stm8.git] / lib / Target / X86 / X86InstrInfo.cpp
blob702331d8ed99345b913642a16b3ec512c0f73bfe
1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include <limits>
37
38 #define GET_INSTRINFO_CTOR
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
41
42 using namespace llvm;
43
44 static cl::opt<bool>
45 NoFusing("disable-spill-fusing",
46 cl::desc("Disable fusing of spill code into instructions"));
47 static cl::opt<bool>
48 PrintFailedFusing("print-failed-fuse-candidates",
49 cl::desc("Print instructions that the allocator wants to"
50 " fuse, but the X86 backend currently can't"),
51 cl::Hidden);
52 static cl::opt<bool>
53 ReMatPICStubLoad("remat-pic-stub-load",
54 cl::desc("Re-materialize load from stub in PIC mode"),
55 cl::init(false), cl::Hidden);
56
57 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
58 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
59 ? X86::ADJCALLSTACKDOWN64
60 : X86::ADJCALLSTACKDOWN32),
61 (tm.getSubtarget<X86Subtarget>().is64Bit()
62 ? X86::ADJCALLSTACKUP64
63 : X86::ADJCALLSTACKUP32)),
64 TM(tm), RI(tm, *this) {
65 enum {
66 TB_NOT_REVERSABLE = 1U << 31,
67 TB_FLAGS = TB_NOT_REVERSABLE
68 };
69
70 static const unsigned OpTbl2Addr[][2] = {
71 { X86::ADC32ri, X86::ADC32mi },
72 { X86::ADC32ri8, X86::ADC32mi8 },
73 { X86::ADC32rr, X86::ADC32mr },
74 { X86::ADC64ri32, X86::ADC64mi32 },
75 { X86::ADC64ri8, X86::ADC64mi8 },
76 { X86::ADC64rr, X86::ADC64mr },
77 { X86::ADD16ri, X86::ADD16mi },
78 { X86::ADD16ri8, X86::ADD16mi8 },
79 { X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE },
80 { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
81 { X86::ADD16rr, X86::ADD16mr },
82 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
83 { X86::ADD32ri, X86::ADD32mi },
84 { X86::ADD32ri8, X86::ADD32mi8 },
85 { X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE },
86 { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
87 { X86::ADD32rr, X86::ADD32mr },
88 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
89 { X86::ADD64ri32, X86::ADD64mi32 },
90 { X86::ADD64ri8, X86::ADD64mi8 },
91 { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
92 { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
93 { X86::ADD64rr, X86::ADD64mr },
94 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
95 { X86::ADD8ri, X86::ADD8mi },
96 { X86::ADD8rr, X86::ADD8mr },
97 { X86::AND16ri, X86::AND16mi },
98 { X86::AND16ri8, X86::AND16mi8 },
99 { X86::AND16rr, X86::AND16mr },
100 { X86::AND32ri, X86::AND32mi },
101 { X86::AND32ri8, X86::AND32mi8 },
102 { X86::AND32rr, X86::AND32mr },
103 { X86::AND64ri32, X86::AND64mi32 },
104 { X86::AND64ri8, X86::AND64mi8 },
105 { X86::AND64rr, X86::AND64mr },
106 { X86::AND8ri, X86::AND8mi },
107 { X86::AND8rr, X86::AND8mr },
108 { X86::DEC16r, X86::DEC16m },
109 { X86::DEC32r, X86::DEC32m },
110 { X86::DEC64_16r, X86::DEC64_16m },
111 { X86::DEC64_32r, X86::DEC64_32m },
112 { X86::DEC64r, X86::DEC64m },
113 { X86::DEC8r, X86::DEC8m },
114 { X86::INC16r, X86::INC16m },
115 { X86::INC32r, X86::INC32m },
116 { X86::INC64_16r, X86::INC64_16m },
117 { X86::INC64_32r, X86::INC64_32m },
118 { X86::INC64r, X86::INC64m },
119 { X86::INC8r, X86::INC8m },
120 { X86::NEG16r, X86::NEG16m },
121 { X86::NEG32r, X86::NEG32m },
122 { X86::NEG64r, X86::NEG64m },
123 { X86::NEG8r, X86::NEG8m },
124 { X86::NOT16r, X86::NOT16m },
125 { X86::NOT32r, X86::NOT32m },
126 { X86::NOT64r, X86::NOT64m },
127 { X86::NOT8r, X86::NOT8m },
128 { X86::OR16ri, X86::OR16mi },
129 { X86::OR16ri8, X86::OR16mi8 },
130 { X86::OR16rr, X86::OR16mr },
131 { X86::OR32ri, X86::OR32mi },
132 { X86::OR32ri8, X86::OR32mi8 },
133 { X86::OR32rr, X86::OR32mr },
134 { X86::OR64ri32, X86::OR64mi32 },
135 { X86::OR64ri8, X86::OR64mi8 },
136 { X86::OR64rr, X86::OR64mr },
137 { X86::OR8ri, X86::OR8mi },
138 { X86::OR8rr, X86::OR8mr },
139 { X86::ROL16r1, X86::ROL16m1 },
140 { X86::ROL16rCL, X86::ROL16mCL },
141 { X86::ROL16ri, X86::ROL16mi },
142 { X86::ROL32r1, X86::ROL32m1 },
143 { X86::ROL32rCL, X86::ROL32mCL },
144 { X86::ROL32ri, X86::ROL32mi },
145 { X86::ROL64r1, X86::ROL64m1 },
146 { X86::ROL64rCL, X86::ROL64mCL },
147 { X86::ROL64ri, X86::ROL64mi },
148 { X86::ROL8r1, X86::ROL8m1 },
149 { X86::ROL8rCL, X86::ROL8mCL },
150 { X86::ROL8ri, X86::ROL8mi },
151 { X86::ROR16r1, X86::ROR16m1 },
152 { X86::ROR16rCL, X86::ROR16mCL },
153 { X86::ROR16ri, X86::ROR16mi },
154 { X86::ROR32r1, X86::ROR32m1 },
155 { X86::ROR32rCL, X86::ROR32mCL },
156 { X86::ROR32ri, X86::ROR32mi },
157 { X86::ROR64r1, X86::ROR64m1 },
158 { X86::ROR64rCL, X86::ROR64mCL },
159 { X86::ROR64ri, X86::ROR64mi },
160 { X86::ROR8r1, X86::ROR8m1 },
161 { X86::ROR8rCL, X86::ROR8mCL },
162 { X86::ROR8ri, X86::ROR8mi },
163 { X86::SAR16r1, X86::SAR16m1 },
164 { X86::SAR16rCL, X86::SAR16mCL },
165 { X86::SAR16ri, X86::SAR16mi },
166 { X86::SAR32r1, X86::SAR32m1 },
167 { X86::SAR32rCL, X86::SAR32mCL },
168 { X86::SAR32ri, X86::SAR32mi },
169 { X86::SAR64r1, X86::SAR64m1 },
170 { X86::SAR64rCL, X86::SAR64mCL },
171 { X86::SAR64ri, X86::SAR64mi },
172 { X86::SAR8r1, X86::SAR8m1 },
173 { X86::SAR8rCL, X86::SAR8mCL },
174 { X86::SAR8ri, X86::SAR8mi },
175 { X86::SBB32ri, X86::SBB32mi },
176 { X86::SBB32ri8, X86::SBB32mi8 },
177 { X86::SBB32rr, X86::SBB32mr },
178 { X86::SBB64ri32, X86::SBB64mi32 },
179 { X86::SBB64ri8, X86::SBB64mi8 },
180 { X86::SBB64rr, X86::SBB64mr },
181 { X86::SHL16rCL, X86::SHL16mCL },
182 { X86::SHL16ri, X86::SHL16mi },
183 { X86::SHL32rCL, X86::SHL32mCL },
184 { X86::SHL32ri, X86::SHL32mi },
185 { X86::SHL64rCL, X86::SHL64mCL },
186 { X86::SHL64ri, X86::SHL64mi },
187 { X86::SHL8rCL, X86::SHL8mCL },
188 { X86::SHL8ri, X86::SHL8mi },
189 { X86::SHLD16rrCL, X86::SHLD16mrCL },
190 { X86::SHLD16rri8, X86::SHLD16mri8 },
191 { X86::SHLD32rrCL, X86::SHLD32mrCL },
192 { X86::SHLD32rri8, X86::SHLD32mri8 },
193 { X86::SHLD64rrCL, X86::SHLD64mrCL },
194 { X86::SHLD64rri8, X86::SHLD64mri8 },
195 { X86::SHR16r1, X86::SHR16m1 },
196 { X86::SHR16rCL, X86::SHR16mCL },
197 { X86::SHR16ri, X86::SHR16mi },
198 { X86::SHR32r1, X86::SHR32m1 },
199 { X86::SHR32rCL, X86::SHR32mCL },
200 { X86::SHR32ri, X86::SHR32mi },
201 { X86::SHR64r1, X86::SHR64m1 },
202 { X86::SHR64rCL, X86::SHR64mCL },
203 { X86::SHR64ri, X86::SHR64mi },
204 { X86::SHR8r1, X86::SHR8m1 },
205 { X86::SHR8rCL, X86::SHR8mCL },
206 { X86::SHR8ri, X86::SHR8mi },
207 { X86::SHRD16rrCL, X86::SHRD16mrCL },
208 { X86::SHRD16rri8, X86::SHRD16mri8 },
209 { X86::SHRD32rrCL, X86::SHRD32mrCL },
210 { X86::SHRD32rri8, X86::SHRD32mri8 },
211 { X86::SHRD64rrCL, X86::SHRD64mrCL },
212 { X86::SHRD64rri8, X86::SHRD64mri8 },
213 { X86::SUB16ri, X86::SUB16mi },
214 { X86::SUB16ri8, X86::SUB16mi8 },
215 { X86::SUB16rr, X86::SUB16mr },
216 { X86::SUB32ri, X86::SUB32mi },
217 { X86::SUB32ri8, X86::SUB32mi8 },
218 { X86::SUB32rr, X86::SUB32mr },
219 { X86::SUB64ri32, X86::SUB64mi32 },
220 { X86::SUB64ri8, X86::SUB64mi8 },
221 { X86::SUB64rr, X86::SUB64mr },
222 { X86::SUB8ri, X86::SUB8mi },
223 { X86::SUB8rr, X86::SUB8mr },
224 { X86::XOR16ri, X86::XOR16mi },
225 { X86::XOR16ri8, X86::XOR16mi8 },
226 { X86::XOR16rr, X86::XOR16mr },
227 { X86::XOR32ri, X86::XOR32mi },
228 { X86::XOR32ri8, X86::XOR32mi8 },
229 { X86::XOR32rr, X86::XOR32mr },
230 { X86::XOR64ri32, X86::XOR64mi32 },
231 { X86::XOR64ri8, X86::XOR64mi8 },
232 { X86::XOR64rr, X86::XOR64mr },
233 { X86::XOR8ri, X86::XOR8mi },
234 { X86::XOR8rr, X86::XOR8mr }
235 };
236
237 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
238 unsigned RegOp = OpTbl2Addr[i][0];
239 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
240 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
241 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
242
243 // If this is not a reversible operation (because there is a many->one)
244 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
245 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
246 continue;
247
248 // Index 0, folded load and store, no alignment requirement.
249 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
250
251 assert(!MemOp2RegOpTable.count(MemOp) &&
252 "Duplicated entries in unfolding maps?");
253 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
254 }
255
256 // If the third value is 1, then it's folding either a load or a store.
257 static const unsigned OpTbl0[][4] = {
258 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
259 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
260 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
261 { X86::CALL32r, X86::CALL32m, 1, 0 },
262 { X86::CALL64r, X86::CALL64m, 1, 0 },
263 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 },
264 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
265 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
266 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
267 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
268 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
269 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
270 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
271 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
272 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
273 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
274 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
275 { X86::DIV16r, X86::DIV16m, 1, 0 },
276 { X86::DIV32r, X86::DIV32m, 1, 0 },
277 { X86::DIV64r, X86::DIV64m, 1, 0 },
278 { X86::DIV8r, X86::DIV8m, 1, 0 },
279 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
280 { X86::FsMOVAPDrr, X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 },
281 { X86::FsMOVAPSrr, X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 },
282 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
283 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
284 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
285 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
286 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
287 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
288 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
289 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
290 { X86::JMP32r, X86::JMP32m, 1, 0 },
291 { X86::JMP64r, X86::JMP64m, 1, 0 },
292 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
293 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
294 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
295 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
296 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
297 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
298 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
299 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
300 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
301 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
302 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
303 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
304 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
305 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
306 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
307 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
308 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
309 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
310 { X86::MUL16r, X86::MUL16m, 1, 0 },
311 { X86::MUL32r, X86::MUL32m, 1, 0 },
312 { X86::MUL64r, X86::MUL64m, 1, 0 },
313 { X86::MUL8r, X86::MUL8m, 1, 0 },
314 { X86::SETAEr, X86::SETAEm, 0, 0 },
315 { X86::SETAr, X86::SETAm, 0, 0 },
316 { X86::SETBEr, X86::SETBEm, 0, 0 },
317 { X86::SETBr, X86::SETBm, 0, 0 },
318 { X86::SETEr, X86::SETEm, 0, 0 },
319 { X86::SETGEr, X86::SETGEm, 0, 0 },
320 { X86::SETGr, X86::SETGm, 0, 0 },
321 { X86::SETLEr, X86::SETLEm, 0, 0 },
322 { X86::SETLr, X86::SETLm, 0, 0 },
323 { X86::SETNEr, X86::SETNEm, 0, 0 },
324 { X86::SETNOr, X86::SETNOm, 0, 0 },
325 { X86::SETNPr, X86::SETNPm, 0, 0 },
326 { X86::SETNSr, X86::SETNSm, 0, 0 },
327 { X86::SETOr, X86::SETOm, 0, 0 },
328 { X86::SETPr, X86::SETPm, 0, 0 },
329 { X86::SETSr, X86::SETSm, 0, 0 },
330 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
331 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
332 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
333 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
334 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
335 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
336 };
337
338 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
339 unsigned RegOp = OpTbl0[i][0];
340 unsigned MemOp = OpTbl0[i][1] & ~TB_FLAGS;
341 unsigned FoldedLoad = OpTbl0[i][2];
342 unsigned Align = OpTbl0[i][3];
343 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
344 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
345
346 // If this is not a reversible operation (because there is a many->one)
347 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
348 if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
349 continue;
350
351 // Index 0, folded load or store.
352 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
353 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
354 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
355 }
356
357 static const unsigned OpTbl1[][3] = {
358 { X86::CMP16rr, X86::CMP16rm, 0 },
359 { X86::CMP32rr, X86::CMP32rm, 0 },
360 { X86::CMP64rr, X86::CMP64rm, 0 },
361 { X86::CMP8rr, X86::CMP8rm, 0 },
362 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
363 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
364 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
365 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
366 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
367 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
368 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
369 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
370 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
371 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
372 { X86::FsMOVAPDrr, X86::MOVSDrm | TB_NOT_REVERSABLE , 0 },
373 { X86::FsMOVAPSrr, X86::MOVSSrm | TB_NOT_REVERSABLE , 0 },
374 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
375 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
376 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
377 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
378 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
379 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
380 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
381 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
382 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
383 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
384 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
385 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
386 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
387 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
388 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
389 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
390 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
391 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
392 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
393 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
394 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
395 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
396 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
397 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
398 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 },
399 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 },
400 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
401 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
402 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
403 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
404 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
405 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
406 { X86::MOV16rr, X86::MOV16rm, 0 },
407 { X86::MOV32rr, X86::MOV32rm, 0 },
408 { X86::MOV64rr, X86::MOV64rm, 0 },
409 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
410 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
411 { X86::MOV8rr, X86::MOV8rm, 0 },
412 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
413 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
414 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
415 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
416 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
417 { X86::MOVDQArr, X86::MOVDQArm, 16 },
418 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
419 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
420 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
421 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
422 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
423 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
424 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
425 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
426 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
427 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
428 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
429 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
430 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
431 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
432 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
433 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
434 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
435 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
436 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
437 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
438 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
439 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
440 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
441 { X86::RCPPSr, X86::RCPPSm, 16 },
442 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
443 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
444 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
445 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
446 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
447 { X86::SQRTPDr, X86::SQRTPDm, 16 },
448 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
449 { X86::SQRTPSr, X86::SQRTPSm, 16 },
450 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
451 { X86::SQRTSDr, X86::SQRTSDm, 0 },
452 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
453 { X86::SQRTSSr, X86::SQRTSSm, 0 },
454 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
455 { X86::TEST16rr, X86::TEST16rm, 0 },
456 { X86::TEST32rr, X86::TEST32rm, 0 },
457 { X86::TEST64rr, X86::TEST64rm, 0 },
458 { X86::TEST8rr, X86::TEST8rm, 0 },
459 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
460 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
461 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
462 };
463
464 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
465 unsigned RegOp = OpTbl1[i][0];
466 unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS;
467 unsigned Align = OpTbl1[i][2];
468 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
469 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align);
470
471 // If this is not a reversible operation (because there is a many->one)
472 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
473 if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
474 continue;
475
476 // Index 1, folded load
477 unsigned AuxInfo = 1 | (1 << 4);
478 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
479 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
480 }
481
482 static const unsigned OpTbl2[][3] = {
483 { X86::ADC32rr, X86::ADC32rm, 0 },
484 { X86::ADC64rr, X86::ADC64rm, 0 },
485 { X86::ADD16rr, X86::ADD16rm, 0 },
486 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 },
487 { X86::ADD32rr, X86::ADD32rm, 0 },
488 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 },
489 { X86::ADD64rr, X86::ADD64rm, 0 },
490 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 },
491 { X86::ADD8rr, X86::ADD8rm, 0 },
492 { X86::ADDPDrr, X86::ADDPDrm, 16 },
493 { X86::ADDPSrr, X86::ADDPSrm, 16 },
494 { X86::ADDSDrr, X86::ADDSDrm, 0 },
495 { X86::ADDSSrr, X86::ADDSSrm, 0 },
496 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
497 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
498 { X86::AND16rr, X86::AND16rm, 0 },
499 { X86::AND32rr, X86::AND32rm, 0 },
500 { X86::AND64rr, X86::AND64rm, 0 },
501 { X86::AND8rr, X86::AND8rm, 0 },
502 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
503 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
504 { X86::ANDPDrr, X86::ANDPDrm, 16 },
505 { X86::ANDPSrr, X86::ANDPSrm, 16 },
506 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
507 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
508 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
509 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
510 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
511 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
512 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
513 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
514 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
515 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
516 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
517 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
518 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
519 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
520 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
521 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
522 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
523 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
524 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
525 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
526 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
527 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
528 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
529 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
530 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
531 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
532 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
533 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
534 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
535 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
536 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
537 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
538 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
539 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
540 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
541 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
542 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
543 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
544 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
545 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
546 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
547 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
548 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
549 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
550 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
551 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
552 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
553 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
554 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
555 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
556 { X86::CMPSDrr, X86::CMPSDrm, 0 },
557 { X86::CMPSSrr, X86::CMPSSrm, 0 },
558 { X86::DIVPDrr, X86::DIVPDrm, 16 },
559 { X86::DIVPSrr, X86::DIVPSrm, 16 },
560 { X86::DIVSDrr, X86::DIVSDrm, 0 },
561 { X86::DIVSSrr, X86::DIVSSrm, 0 },
562 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
563 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
564 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
565 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
566 { X86::FsORPDrr, X86::FsORPDrm, 16 },
567 { X86::FsORPSrr, X86::FsORPSrm, 16 },
568 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
569 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
570 { X86::HADDPDrr, X86::HADDPDrm, 16 },
571 { X86::HADDPSrr, X86::HADDPSrm, 16 },
572 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
573 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
574 { X86::IMUL16rr, X86::IMUL16rm, 0 },
575 { X86::IMUL32rr, X86::IMUL32rm, 0 },
576 { X86::IMUL64rr, X86::IMUL64rm, 0 },
577 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
578 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
579 { X86::MAXPDrr, X86::MAXPDrm, 16 },
580 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
581 { X86::MAXPSrr, X86::MAXPSrm, 16 },
582 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
583 { X86::MAXSDrr, X86::MAXSDrm, 0 },
584 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
585 { X86::MAXSSrr, X86::MAXSSrm, 0 },
586 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
587 { X86::MINPDrr, X86::MINPDrm, 16 },
588 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
589 { X86::MINPSrr, X86::MINPSrm, 16 },
590 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
591 { X86::MINSDrr, X86::MINSDrm, 0 },
592 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
593 { X86::MINSSrr, X86::MINSSrm, 0 },
594 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
595 { X86::MULPDrr, X86::MULPDrm, 16 },
596 { X86::MULPSrr, X86::MULPSrm, 16 },
597 { X86::MULSDrr, X86::MULSDrm, 0 },
598 { X86::MULSSrr, X86::MULSSrm, 0 },
599 { X86::OR16rr, X86::OR16rm, 0 },
600 { X86::OR32rr, X86::OR32rm, 0 },
601 { X86::OR64rr, X86::OR64rm, 0 },
602 { X86::OR8rr, X86::OR8rm, 0 },
603 { X86::ORPDrr, X86::ORPDrm, 16 },
604 { X86::ORPSrr, X86::ORPSrm, 16 },
605 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
606 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
607 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
608 { X86::PADDBrr, X86::PADDBrm, 16 },
609 { X86::PADDDrr, X86::PADDDrm, 16 },
610 { X86::PADDQrr, X86::PADDQrm, 16 },
611 { X86::PADDSBrr, X86::PADDSBrm, 16 },
612 { X86::PADDSWrr, X86::PADDSWrm, 16 },
613 { X86::PADDWrr, X86::PADDWrm, 16 },
614 { X86::PANDNrr, X86::PANDNrm, 16 },
615 { X86::PANDrr, X86::PANDrm, 16 },
616 { X86::PAVGBrr, X86::PAVGBrm, 16 },
617 { X86::PAVGWrr, X86::PAVGWrm, 16 },
618 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
619 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
620 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
621 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
622 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
623 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
624 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
625 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
626 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
627 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
628 { X86::PMINSWrr, X86::PMINSWrm, 16 },
629 { X86::PMINUBrr, X86::PMINUBrm, 16 },
630 { X86::PMULDQrr, X86::PMULDQrm, 16 },
631 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
632 { X86::PMULHWrr, X86::PMULHWrm, 16 },
633 { X86::PMULLDrr, X86::PMULLDrm, 16 },
634 { X86::PMULLWrr, X86::PMULLWrm, 16 },
635 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
636 { X86::PORrr, X86::PORrm, 16 },
637 { X86::PSADBWrr, X86::PSADBWrm, 16 },
638 { X86::PSLLDrr, X86::PSLLDrm, 16 },
639 { X86::PSLLQrr, X86::PSLLQrm, 16 },
640 { X86::PSLLWrr, X86::PSLLWrm, 16 },
641 { X86::PSRADrr, X86::PSRADrm, 16 },
642 { X86::PSRAWrr, X86::PSRAWrm, 16 },
643 { X86::PSRLDrr, X86::PSRLDrm, 16 },
644 { X86::PSRLQrr, X86::PSRLQrm, 16 },
645 { X86::PSRLWrr, X86::PSRLWrm, 16 },
646 { X86::PSUBBrr, X86::PSUBBrm, 16 },
647 { X86::PSUBDrr, X86::PSUBDrm, 16 },
648 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
649 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
650 { X86::PSUBWrr, X86::PSUBWrm, 16 },
651 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
652 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
653 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
654 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
655 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
656 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
657 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
658 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
659 { X86::PXORrr, X86::PXORrm, 16 },
660 { X86::SBB32rr, X86::SBB32rm, 0 },
661 { X86::SBB64rr, X86::SBB64rm, 0 },
662 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
663 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
664 { X86::SUB16rr, X86::SUB16rm, 0 },
665 { X86::SUB32rr, X86::SUB32rm, 0 },
666 { X86::SUB64rr, X86::SUB64rm, 0 },
667 { X86::SUB8rr, X86::SUB8rm, 0 },
668 { X86::SUBPDrr, X86::SUBPDrm, 16 },
669 { X86::SUBPSrr, X86::SUBPSrm, 16 },
670 { X86::SUBSDrr, X86::SUBSDrm, 0 },
671 { X86::SUBSSrr, X86::SUBSSrm, 0 },
672 // FIXME: TEST*rr -> swapped operand of TEST*mr.
673 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
674 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
675 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
676 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
677 { X86::XOR16rr, X86::XOR16rm, 0 },
678 { X86::XOR32rr, X86::XOR32rm, 0 },
679 { X86::XOR64rr, X86::XOR64rm, 0 },
680 { X86::XOR8rr, X86::XOR8rm, 0 },
681 { X86::XORPDrr, X86::XORPDrm, 16 },
682 { X86::XORPSrr, X86::XORPSrm, 16 }
683 };
684
685 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
686 unsigned RegOp = OpTbl2[i][0];
687 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
688 unsigned Align = OpTbl2[i][2];
689
690 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
691 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
692
693 // If this is not a reversible operation (because there is a many->one)
694 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
695 if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
696 continue;
697
698 // Index 2, folded load
699 unsigned AuxInfo = 2 | (1 << 4);
700 assert(!MemOp2RegOpTable.count(MemOp) &&
701 "Duplicated entries in unfolding maps?");
702 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
703 }
704 }
705
706 bool
707 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
708 unsigned &SrcReg, unsigned &DstReg,
709 unsigned &SubIdx) const {
710 switch (MI.getOpcode()) {
711 default: break;
712 case X86::MOVSX16rr8:
713 case X86::MOVZX16rr8:
714 case X86::MOVSX32rr8:
715 case X86::MOVZX32rr8:
716 case X86::MOVSX64rr8:
717 case X86::MOVZX64rr8:
718 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
719 // It's not always legal to reference the low 8-bit of the larger
720 // register in 32-bit mode.
721 return false;
722 case X86::MOVSX32rr16:
723 case X86::MOVZX32rr16:
724 case X86::MOVSX64rr16:
725 case X86::MOVZX64rr16:
726 case X86::MOVSX64rr32:
727 case X86::MOVZX64rr32: {
728 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
729 // Be conservative.
730 return false;
731 SrcReg = MI.getOperand(1).getReg();
732 DstReg = MI.getOperand(0).getReg();
733 switch (MI.getOpcode()) {
734 default:
735 llvm_unreachable(0);
736 break;
737 case X86::MOVSX16rr8:
738 case X86::MOVZX16rr8:
739 case X86::MOVSX32rr8:
740 case X86::MOVZX32rr8:
741 case X86::MOVSX64rr8:
742 case X86::MOVZX64rr8:
743 SubIdx = X86::sub_8bit;
744 break;
745 case X86::MOVSX32rr16:
746 case X86::MOVZX32rr16:
747 case X86::MOVSX64rr16:
748 case X86::MOVZX64rr16:
749 SubIdx = X86::sub_16bit;
750 break;
751 case X86::MOVSX64rr32:
752 case X86::MOVZX64rr32:
753 SubIdx = X86::sub_32bit;
754 break;
755 }
756 return true;
757 }
758 }
759 return false;
760 }
761
762 /// isFrameOperand - Return true and the FrameIndex if the specified
763 /// operand and follow operands form a reference to the stack frame.
764 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
765 int &FrameIndex) const {
766 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
767 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
768 MI->getOperand(Op+1).getImm() == 1 &&
769 MI->getOperand(Op+2).getReg() == 0 &&
770 MI->getOperand(Op+3).getImm() == 0) {
771 FrameIndex = MI->getOperand(Op).getIndex();
772 return true;
773 }
774 return false;
775 }
776
777 static bool isFrameLoadOpcode(int Opcode) {
778 switch (Opcode) {
779 default: break;
780 case X86::MOV8rm:
781 case X86::MOV16rm:
782 case X86::MOV32rm:
783 case X86::MOV64rm:
784 case X86::LD_Fp64m:
785 case X86::MOVSSrm:
786 case X86::MOVSDrm:
787 case X86::MOVAPSrm:
788 case X86::MOVAPDrm:
789 case X86::MOVDQArm:
790 case X86::MMX_MOVD64rm:
791 case X86::MMX_MOVQ64rm:
792 return true;
793 break;
794 }
795 return false;
796 }
797
798 static bool isFrameStoreOpcode(int Opcode) {
799 switch (Opcode) {
800 default: break;
801 case X86::MOV8mr:
802 case X86::MOV16mr:
803 case X86::MOV32mr:
804 case X86::MOV64mr:
805 case X86::ST_FpP64m:
806 case X86::MOVSSmr:
807 case X86::MOVSDmr:
808 case X86::MOVAPSmr:
809 case X86::MOVAPDmr:
810 case X86::MOVDQAmr:
811 case X86::MMX_MOVD64mr:
812 case X86::MMX_MOVQ64mr:
813 case X86::MMX_MOVNTQmr:
814 return true;
815 }
816 return false;
817 }
818
819 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
820 int &FrameIndex) const {
821 if (isFrameLoadOpcode(MI->getOpcode()))
822 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
823 return MI->getOperand(0).getReg();
824 return 0;
825 }
826
827 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
828 int &FrameIndex) const {
829 if (isFrameLoadOpcode(MI->getOpcode())) {
830 unsigned Reg;
831 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
832 return Reg;
833 // Check for post-frame index elimination operations
834 const MachineMemOperand *Dummy;
835 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
836 }
837 return 0;
838 }
839
840 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
841 const MachineMemOperand *&MMO,
842 int &FrameIndex) const {
843 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
844 oe = MI->memoperands_end();
845 o != oe;
846 ++o) {
847 if ((*o)->isLoad() && (*o)->getValue())
848 if (const FixedStackPseudoSourceValue *Value =
849 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
850 FrameIndex = Value->getFrameIndex();
851 MMO = *o;
852 return true;
853 }
854 }
855 return false;
856 }
857
858 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
859 int &FrameIndex) const {
860 if (isFrameStoreOpcode(MI->getOpcode()))
861 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
862 isFrameOperand(MI, 0, FrameIndex))
863 return MI->getOperand(X86::AddrNumOperands).getReg();
864 return 0;
865 }
866
867 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
868 int &FrameIndex) const {
869 if (isFrameStoreOpcode(MI->getOpcode())) {
870 unsigned Reg;
871 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
872 return Reg;
873 // Check for post-frame index elimination operations
874 const MachineMemOperand *Dummy;
875 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
876 }
877 return 0;
878 }
879
880 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
881 const MachineMemOperand *&MMO,
882 int &FrameIndex) const {
883 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
884 oe = MI->memoperands_end();
885 o != oe;
886 ++o) {
887 if ((*o)->isStore() && (*o)->getValue())
888 if (const FixedStackPseudoSourceValue *Value =
889 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
890 FrameIndex = Value->getFrameIndex();
891 MMO = *o;
892 return true;
893 }
894 }
895 return false;
896 }
897
898 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
899 /// X86::MOVPC32r.
900 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
901 bool isPICBase = false;
902 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
903 E = MRI.def_end(); I != E; ++I) {
904 MachineInstr *DefMI = I.getOperand().getParent();
905 if (DefMI->getOpcode() != X86::MOVPC32r)
906 return false;
907 assert(!isPICBase && "More than one PIC base?");
908 isPICBase = true;
909 }
910 return isPICBase;
911 }
912
913 bool
914 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
915 AliasAnalysis *AA) const {
916 switch (MI->getOpcode()) {
917 default: break;
918 case X86::MOV8rm:
919 case X86::MOV16rm:
920 case X86::MOV32rm:
921 case X86::MOV64rm:
922 case X86::LD_Fp64m:
923 case X86::MOVSSrm:
924 case X86::MOVSDrm:
925 case X86::MOVAPSrm:
926 case X86::MOVUPSrm:
927 case X86::MOVAPDrm:
928 case X86::MOVDQArm:
929 case X86::MMX_MOVD64rm:
930 case X86::MMX_MOVQ64rm:
931 case X86::FsMOVAPSrm:
932 case X86::FsMOVAPDrm: {
933 // Loads from constant pools are trivially rematerializable.
934 if (MI->getOperand(1).isReg() &&
935 MI->getOperand(2).isImm() &&
936 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
937 MI->isInvariantLoad(AA)) {
938 unsigned BaseReg = MI->getOperand(1).getReg();
939 if (BaseReg == 0 || BaseReg == X86::RIP)
940 return true;
941 // Allow re-materialization of PIC load.
942 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
943 return false;
944 const MachineFunction &MF = *MI->getParent()->getParent();
945 const MachineRegisterInfo &MRI = MF.getRegInfo();
946 bool isPICBase = false;
947 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
948 E = MRI.def_end(); I != E; ++I) {
949 MachineInstr *DefMI = I.getOperand().getParent();
950 if (DefMI->getOpcode() != X86::MOVPC32r)
951 return false;
952 assert(!isPICBase && "More than one PIC base?");
953 isPICBase = true;
954 }
955 return isPICBase;
956 }
957 return false;
958 }
959
960 case X86::LEA32r:
961 case X86::LEA64r: {
962 if (MI->getOperand(2).isImm() &&
963 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
964 !MI->getOperand(4).isReg()) {
965 // lea fi#, lea GV, etc. are all rematerializable.
966 if (!MI->getOperand(1).isReg())
967 return true;
968 unsigned BaseReg = MI->getOperand(1).getReg();
969 if (BaseReg == 0)
970 return true;
971 // Allow re-materialization of lea PICBase + x.
972 const MachineFunction &MF = *MI->getParent()->getParent();
973 const MachineRegisterInfo &MRI = MF.getRegInfo();
974 return regIsPICBase(BaseReg, MRI);
975 }
976 return false;
977 }
978 }
979
980 // All other instructions marked M_REMATERIALIZABLE are always trivially
981 // rematerializable.
982 return true;
983 }
984
985 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
986 /// would clobber the EFLAGS condition register. Note the result may be
987 /// conservative. If it cannot definitely determine the safety after visiting
988 /// a few instructions in each direction it assumes it's not safe.
989 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
990 MachineBasicBlock::iterator I) {
991 MachineBasicBlock::iterator E = MBB.end();
992
993 // It's always safe to clobber EFLAGS at the end of a block.
994 if (I == E)
995 return true;
996
997 // For compile time consideration, if we are not able to determine the
998 // safety after visiting 4 instructions in each direction, we will assume
999 // it's not safe.
1000 MachineBasicBlock::iterator Iter = I;
1001 for (unsigned i = 0; i < 4; ++i) {
1002 bool SeenDef = false;
1003 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1004 MachineOperand &MO = Iter->getOperand(j);
1005 if (!MO.isReg())
1006 continue;
1007 if (MO.getReg() == X86::EFLAGS) {
1008 if (MO.isUse())
1009 return false;
1010 SeenDef = true;
1011 }
1012 }
1013
1014 if (SeenDef)
1015 // This instruction defines EFLAGS, no need to look any further.
1016 return true;
1017 ++Iter;
1018 // Skip over DBG_VALUE.
1019 while (Iter != E && Iter->isDebugValue())
1020 ++Iter;
1021
1022 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1023 if (Iter == E)
1024 return true;
1025 }
1026
1027 MachineBasicBlock::iterator B = MBB.begin();
1028 Iter = I;
1029 for (unsigned i = 0; i < 4; ++i) {
1030 // If we make it to the beginning of the block, it's safe to clobber
1031 // EFLAGS iff EFLAGS is not live-in.
1032 if (Iter == B)
1033 return !MBB.isLiveIn(X86::EFLAGS);
1034
1035 --Iter;
1036 // Skip over DBG_VALUE.
1037 while (Iter != B && Iter->isDebugValue())
1038 --Iter;
1039
1040 bool SawKill = false;
1041 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1042 MachineOperand &MO = Iter->getOperand(j);
1043 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1044 if (MO.isDef()) return MO.isDead();
1045 if (MO.isKill()) SawKill = true;
1046 }
1047 }
1048
1049 if (SawKill)
1050 // This instruction kills EFLAGS and doesn't redefine it, so
1051 // there's no need to look further.
1052 return true;
1053 }
1054
1055 // Conservative answer.
1056 return false;
1057 }
1058
1059 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1060 MachineBasicBlock::iterator I,
1061 unsigned DestReg, unsigned SubIdx,
1062 const MachineInstr *Orig,
1063 const TargetRegisterInfo &TRI) const {
1064 DebugLoc DL = Orig->getDebugLoc();
1065
1066 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1067 // Re-materialize them as movri instructions to avoid side effects.
1068 bool Clone = true;
1069 unsigned Opc = Orig->getOpcode();
1070 switch (Opc) {
1071 default: break;
1072 case X86::MOV8r0:
1073 case X86::MOV16r0:
1074 case X86::MOV32r0:
1075 case X86::MOV64r0: {
1076 if (!isSafeToClobberEFLAGS(MBB, I)) {
1077 switch (Opc) {
1078 default: break;
1079 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1080 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1081 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1082 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1083 }
1084 Clone = false;
1085 }
1086 break;
1087 }
1088 }
1089
1090 if (Clone) {
1091 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1092 MBB.insert(I, MI);
1093 } else {
1094 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1095 }
1096
1097 MachineInstr *NewMI = prior(I);
1098 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1099 }
1100
1101 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1102 /// is not marked dead.
1103 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1104 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1105 MachineOperand &MO = MI->getOperand(i);
1106 if (MO.isReg() && MO.isDef() &&
1107 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1108 return true;
1109 }
1110 }
1111 return false;
1112 }
1113
1114 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1115 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1116 /// to a 32-bit superregister and then truncating back down to a 16-bit
1117 /// subregister.
1118 MachineInstr *
1119 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1120 MachineFunction::iterator &MFI,
1121 MachineBasicBlock::iterator &MBBI,
1122 LiveVariables *LV) const {
1123 MachineInstr *MI = MBBI;
1124 unsigned Dest = MI->getOperand(0).getReg();
1125 unsigned Src = MI->getOperand(1).getReg();
1126 bool isDead = MI->getOperand(0).isDead();
1127 bool isKill = MI->getOperand(1).isKill();
1128
1129 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1130 ? X86::LEA64_32r : X86::LEA32r;
1131 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1132 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1133 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1134
1135 // Build and insert into an implicit UNDEF value. This is OK because
1136 // well be shifting and then extracting the lower 16-bits.
1137 // This has the potential to cause partial register stall. e.g.
1138 // movw (%rbp,%rcx,2), %dx
1139 // leal -65(%rdx), %esi
1140 // But testing has shown this *does* help performance in 64-bit mode (at
1141 // least on modern x86 machines).
1142 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1143 MachineInstr *InsMI =
1144 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1145 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1146 .addReg(Src, getKillRegState(isKill));
1147
1148 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1149 get(Opc), leaOutReg);
1150 switch (MIOpc) {
1151 default:
1152 llvm_unreachable(0);
1153 break;
1154 case X86::SHL16ri: {
1155 unsigned ShAmt = MI->getOperand(2).getImm();
1156 MIB.addReg(0).addImm(1 << ShAmt)
1157 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1158 break;
1159 }
1160 case X86::INC16r:
1161 case X86::INC64_16r:
1162 addRegOffset(MIB, leaInReg, true, 1);
1163 break;
1164 case X86::DEC16r:
1165 case X86::DEC64_16r:
1166 addRegOffset(MIB, leaInReg, true, -1);
1167 break;
1168 case X86::ADD16ri:
1169 case X86::ADD16ri8:
1170 case X86::ADD16ri_DB:
1171 case X86::ADD16ri8_DB:
1172 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1173 break;
1174 case X86::ADD16rr:
1175 case X86::ADD16rr_DB: {
1176 unsigned Src2 = MI->getOperand(2).getReg();
1177 bool isKill2 = MI->getOperand(2).isKill();
1178 unsigned leaInReg2 = 0;
1179 MachineInstr *InsMI2 = 0;
1180 if (Src == Src2) {
1181 // ADD16rr %reg1028<kill>, %reg1028
1182 // just a single insert_subreg.
1183 addRegReg(MIB, leaInReg, true, leaInReg, false);
1184 } else {
1185 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1186 // Build and insert into an implicit UNDEF value. This is OK because
1187 // well be shifting and then extracting the lower 16-bits.
1188 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1189 InsMI2 =
1190 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1191 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1192 .addReg(Src2, getKillRegState(isKill2));
1193 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1194 }
1195 if (LV && isKill2 && InsMI2)
1196 LV->replaceKillInstruction(Src2, MI, InsMI2);
1197 break;
1198 }
1199 }
1200
1201 MachineInstr *NewMI = MIB;
1202 MachineInstr *ExtMI =
1203 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1204 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1205 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1206
1207 if (LV) {
1208 // Update live variables
1209 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1210 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1211 if (isKill)
1212 LV->replaceKillInstruction(Src, MI, InsMI);
1213 if (isDead)
1214 LV->replaceKillInstruction(Dest, MI, ExtMI);
1215 }
1216
1217 return ExtMI;
1218 }
1219
1220 /// convertToThreeAddress - This method must be implemented by targets that
1221 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1222 /// may be able to convert a two-address instruction into a true
1223 /// three-address instruction on demand. This allows the X86 target (for
1224 /// example) to convert ADD and SHL instructions into LEA instructions if they
1225 /// would require register copies due to two-addressness.
1226 ///
1227 /// This method returns a null pointer if the transformation cannot be
1228 /// performed, otherwise it returns the new instruction.
1229 ///
1230 MachineInstr *
1231 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1232 MachineBasicBlock::iterator &MBBI,
1233 LiveVariables *LV) const {
1234 MachineInstr *MI = MBBI;
1235 MachineFunction &MF = *MI->getParent()->getParent();
1236 // All instructions input are two-addr instructions. Get the known operands.
1237 unsigned Dest = MI->getOperand(0).getReg();
1238 unsigned Src = MI->getOperand(1).getReg();
1239 bool isDead = MI->getOperand(0).isDead();
1240 bool isKill = MI->getOperand(1).isKill();
1241
1242 MachineInstr *NewMI = NULL;
1243 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1244 // we have better subtarget support, enable the 16-bit LEA generation here.
1245 // 16-bit LEA is also slow on Core2.
1246 bool DisableLEA16 = true;
1247 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1248
1249 unsigned MIOpc = MI->getOpcode();
1250 switch (MIOpc) {
1251 case X86::SHUFPSrri: {
1252 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1253 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1254
1255 unsigned B = MI->getOperand(1).getReg();
1256 unsigned C = MI->getOperand(2).getReg();
1257 if (B != C) return 0;
1258 unsigned A = MI->getOperand(0).getReg();
1259 unsigned M = MI->getOperand(3).getImm();
1260 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1261 .addReg(A, RegState::Define | getDeadRegState(isDead))
1262 .addReg(B, getKillRegState(isKill)).addImm(M);
1263 break;
1264 }
1265 case X86::SHL64ri: {
1266 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1267 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1268 // the flags produced by a shift yet, so this is safe.
1269 unsigned ShAmt = MI->getOperand(2).getImm();
1270 if (ShAmt == 0 || ShAmt >= 4) return 0;
1271
1272 // LEA can't handle RSP.
1273 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1274 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1275 return 0;
1276
1277 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1278 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1279 .addReg(0).addImm(1 << ShAmt)
1280 .addReg(Src, getKillRegState(isKill))
1281 .addImm(0).addReg(0);
1282 break;
1283 }
1284 case X86::SHL32ri: {
1285 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1286 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1287 // the flags produced by a shift yet, so this is safe.
1288 unsigned ShAmt = MI->getOperand(2).getImm();
1289 if (ShAmt == 0 || ShAmt >= 4) return 0;
1290
1291 // LEA can't handle ESP.
1292 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1293 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1294 return 0;
1295
1296 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1297 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1298 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299 .addReg(0).addImm(1 << ShAmt)
1300 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1301 break;
1302 }
1303 case X86::SHL16ri: {
1304 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1305 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1306 // the flags produced by a shift yet, so this is safe.
1307 unsigned ShAmt = MI->getOperand(2).getImm();
1308 if (ShAmt == 0 || ShAmt >= 4) return 0;
1309
1310 if (DisableLEA16)
1311 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1312 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1313 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1314 .addReg(0).addImm(1 << ShAmt)
1315 .addReg(Src, getKillRegState(isKill))
1316 .addImm(0).addReg(0);
1317 break;
1318 }
1319 default: {
1320 // The following opcodes also sets the condition code register(s). Only
1321 // convert them to equivalent lea if the condition code register def's
1322 // are dead!
1323 if (hasLiveCondCodeDef(MI))
1324 return 0;
1325
1326 switch (MIOpc) {
1327 default: return 0;
1328 case X86::INC64r:
1329 case X86::INC32r:
1330 case X86::INC64_32r: {
1331 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1332 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1333 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1334
1335 // LEA can't handle RSP.
1336 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1337 !MF.getRegInfo().constrainRegClass(Src,
1338 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1339 X86::GR32_NOSPRegisterClass))
1340 return 0;
1341
1342 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1343 .addReg(Dest, RegState::Define |
1344 getDeadRegState(isDead)),
1345 Src, isKill, 1);
1346 break;
1347 }
1348 case X86::INC16r:
1349 case X86::INC64_16r:
1350 if (DisableLEA16)
1351 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1352 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1353 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1354 .addReg(Dest, RegState::Define |
1355 getDeadRegState(isDead)),
1356 Src, isKill, 1);
1357 break;
1358 case X86::DEC64r:
1359 case X86::DEC32r:
1360 case X86::DEC64_32r: {
1361 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1362 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1363 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1364 // LEA can't handle RSP.
1365 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1366 !MF.getRegInfo().constrainRegClass(Src,
1367 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1368 X86::GR32_NOSPRegisterClass))
1369 return 0;
1370
1371 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1372 .addReg(Dest, RegState::Define |
1373 getDeadRegState(isDead)),
1374 Src, isKill, -1);
1375 break;
1376 }
1377 case X86::DEC16r:
1378 case X86::DEC64_16r:
1379 if (DisableLEA16)
1380 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1381 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1382 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1383 .addReg(Dest, RegState::Define |
1384 getDeadRegState(isDead)),
1385 Src, isKill, -1);
1386 break;
1387 case X86::ADD64rr:
1388 case X86::ADD64rr_DB:
1389 case X86::ADD32rr:
1390 case X86::ADD32rr_DB: {
1391 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1392 unsigned Opc;
1393 TargetRegisterClass *RC;
1394 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1395 Opc = X86::LEA64r;
1396 RC = X86::GR64_NOSPRegisterClass;
1397 } else {
1398 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1399 RC = X86::GR32_NOSPRegisterClass;
1400 }
1401
1402
1403 unsigned Src2 = MI->getOperand(2).getReg();
1404 bool isKill2 = MI->getOperand(2).isKill();
1405
1406 // LEA can't handle RSP.
1407 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1408 !MF.getRegInfo().constrainRegClass(Src2, RC))
1409 return 0;
1410
1411 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1412 .addReg(Dest, RegState::Define |
1413 getDeadRegState(isDead)),
1414 Src, isKill, Src2, isKill2);
1415 if (LV && isKill2)
1416 LV->replaceKillInstruction(Src2, MI, NewMI);
1417 break;
1418 }
1419 case X86::ADD16rr:
1420 case X86::ADD16rr_DB: {
1421 if (DisableLEA16)
1422 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1423 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1424 unsigned Src2 = MI->getOperand(2).getReg();
1425 bool isKill2 = MI->getOperand(2).isKill();
1426 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1427 .addReg(Dest, RegState::Define |
1428 getDeadRegState(isDead)),
1429 Src, isKill, Src2, isKill2);
1430 if (LV && isKill2)
1431 LV->replaceKillInstruction(Src2, MI, NewMI);
1432 break;
1433 }
1434 case X86::ADD64ri32:
1435 case X86::ADD64ri8:
1436 case X86::ADD64ri32_DB:
1437 case X86::ADD64ri8_DB:
1438 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1439 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1440 .addReg(Dest, RegState::Define |
1441 getDeadRegState(isDead)),
1442 Src, isKill, MI->getOperand(2).getImm());
1443 break;
1444 case X86::ADD32ri:
1445 case X86::ADD32ri8:
1446 case X86::ADD32ri_DB:
1447 case X86::ADD32ri8_DB: {
1448 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1449 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1450 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1451 .addReg(Dest, RegState::Define |
1452 getDeadRegState(isDead)),
1453 Src, isKill, MI->getOperand(2).getImm());
1454 break;
1455 }
1456 case X86::ADD16ri:
1457 case X86::ADD16ri8:
1458 case X86::ADD16ri_DB:
1459 case X86::ADD16ri8_DB:
1460 if (DisableLEA16)
1461 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1462 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1463 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1464 .addReg(Dest, RegState::Define |
1465 getDeadRegState(isDead)),
1466 Src, isKill, MI->getOperand(2).getImm());
1467 break;
1468 }
1469 }
1470 }
1471
1472 if (!NewMI) return 0;
1473
1474 if (LV) { // Update live variables
1475 if (isKill)
1476 LV->replaceKillInstruction(Src, MI, NewMI);
1477 if (isDead)
1478 LV->replaceKillInstruction(Dest, MI, NewMI);
1479 }
1480
1481 MFI->insert(MBBI, NewMI); // Insert the new inst
1482 return NewMI;
1483 }
1484
1485 /// commuteInstruction - We have a few instructions that must be hacked on to
1486 /// commute them.
1487 ///
1488 MachineInstr *
1489 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1490 switch (MI->getOpcode()) {
1491 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1492 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1493 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1494 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1495 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1496 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1497 unsigned Opc;
1498 unsigned Size;
1499 switch (MI->getOpcode()) {
1500 default: llvm_unreachable("Unreachable!");
1501 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1502 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1503 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1504 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1505 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1506 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1507 }
1508 unsigned Amt = MI->getOperand(3).getImm();
1509 if (NewMI) {
1510 MachineFunction &MF = *MI->getParent()->getParent();
1511 MI = MF.CloneMachineInstr(MI);
1512 NewMI = false;
1513 }
1514 MI->setDesc(get(Opc));
1515 MI->getOperand(3).setImm(Size-Amt);
1516 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1517 }
1518 case X86::CMOVB16rr:
1519 case X86::CMOVB32rr:
1520 case X86::CMOVB64rr:
1521 case X86::CMOVAE16rr:
1522 case X86::CMOVAE32rr:
1523 case X86::CMOVAE64rr:
1524 case X86::CMOVE16rr:
1525 case X86::CMOVE32rr:
1526 case X86::CMOVE64rr:
1527 case X86::CMOVNE16rr:
1528 case X86::CMOVNE32rr:
1529 case X86::CMOVNE64rr:
1530 case X86::CMOVBE16rr:
1531 case X86::CMOVBE32rr:
1532 case X86::CMOVBE64rr:
1533 case X86::CMOVA16rr:
1534 case X86::CMOVA32rr:
1535 case X86::CMOVA64rr:
1536 case X86::CMOVL16rr:
1537 case X86::CMOVL32rr:
1538 case X86::CMOVL64rr:
1539 case X86::CMOVGE16rr:
1540 case X86::CMOVGE32rr:
1541 case X86::CMOVGE64rr:
1542 case X86::CMOVLE16rr:
1543 case X86::CMOVLE32rr:
1544 case X86::CMOVLE64rr:
1545 case X86::CMOVG16rr:
1546 case X86::CMOVG32rr:
1547 case X86::CMOVG64rr:
1548 case X86::CMOVS16rr:
1549 case X86::CMOVS32rr:
1550 case X86::CMOVS64rr:
1551 case X86::CMOVNS16rr:
1552 case X86::CMOVNS32rr:
1553 case X86::CMOVNS64rr:
1554 case X86::CMOVP16rr:
1555 case X86::CMOVP32rr:
1556 case X86::CMOVP64rr:
1557 case X86::CMOVNP16rr:
1558 case X86::CMOVNP32rr:
1559 case X86::CMOVNP64rr:
1560 case X86::CMOVO16rr:
1561 case X86::CMOVO32rr:
1562 case X86::CMOVO64rr:
1563 case X86::CMOVNO16rr:
1564 case X86::CMOVNO32rr:
1565 case X86::CMOVNO64rr: {
1566 unsigned Opc = 0;
1567 switch (MI->getOpcode()) {
1568 default: break;
1569 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1570 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1571 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1572 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1573 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1574 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1575 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1576 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1577 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1578 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1579 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1580 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1581 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1582 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1583 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1584 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1585 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1586 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1587 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1588 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1589 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1590 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1591 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1592 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1593 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1594 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1595 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1596 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1597 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1598 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1599 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1600 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1601 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1602 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1603 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1604 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1605 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1606 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1607 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1608 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1609 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1610 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1611 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1612 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1613 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1614 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1615 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1616 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1617 }
1618 if (NewMI) {
1619 MachineFunction &MF = *MI->getParent()->getParent();
1620 MI = MF.CloneMachineInstr(MI);
1621 NewMI = false;
1622 }
1623 MI->setDesc(get(Opc));
1624 // Fallthrough intended.
1625 }
1626 default:
1627 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1628 }
1629 }
1630
1631 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1632 switch (BrOpc) {
1633 default: return X86::COND_INVALID;
1634 case X86::JE_4: return X86::COND_E;
1635 case X86::JNE_4: return X86::COND_NE;
1636 case X86::JL_4: return X86::COND_L;
1637 case X86::JLE_4: return X86::COND_LE;
1638 case X86::JG_4: return X86::COND_G;
1639 case X86::JGE_4: return X86::COND_GE;
1640 case X86::JB_4: return X86::COND_B;
1641 case X86::JBE_4: return X86::COND_BE;
1642 case X86::JA_4: return X86::COND_A;
1643 case X86::JAE_4: return X86::COND_AE;
1644 case X86::JS_4: return X86::COND_S;
1645 case X86::JNS_4: return X86::COND_NS;
1646 case X86::JP_4: return X86::COND_P;
1647 case X86::JNP_4: return X86::COND_NP;
1648 case X86::JO_4: return X86::COND_O;
1649 case X86::JNO_4: return X86::COND_NO;
1650 }
1651 }
1652
1653 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1654 switch (CC) {
1655 default: llvm_unreachable("Illegal condition code!");
1656 case X86::COND_E: return X86::JE_4;
1657 case X86::COND_NE: return X86::JNE_4;
1658 case X86::COND_L: return X86::JL_4;
1659 case X86::COND_LE: return X86::JLE_4;
1660 case X86::COND_G: return X86::JG_4;
1661 case X86::COND_GE: return X86::JGE_4;
1662 case X86::COND_B: return X86::JB_4;
1663 case X86::COND_BE: return X86::JBE_4;
1664 case X86::COND_A: return X86::JA_4;
1665 case X86::COND_AE: return X86::JAE_4;
1666 case X86::COND_S: return X86::JS_4;
1667 case X86::COND_NS: return X86::JNS_4;
1668 case X86::COND_P: return X86::JP_4;
1669 case X86::COND_NP: return X86::JNP_4;
1670 case X86::COND_O: return X86::JO_4;
1671 case X86::COND_NO: return X86::JNO_4;
1672 }
1673 }
1674
1675 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1676 /// e.g. turning COND_E to COND_NE.
1677 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1678 switch (CC) {
1679 default: llvm_unreachable("Illegal condition code!");
1680 case X86::COND_E: return X86::COND_NE;
1681 case X86::COND_NE: return X86::COND_E;
1682 case X86::COND_L: return X86::COND_GE;
1683 case X86::COND_LE: return X86::COND_G;
1684 case X86::COND_G: return X86::COND_LE;
1685 case X86::COND_GE: return X86::COND_L;
1686 case X86::COND_B: return X86::COND_AE;
1687 case X86::COND_BE: return X86::COND_A;
1688 case X86::COND_A: return X86::COND_BE;
1689 case X86::COND_AE: return X86::COND_B;
1690 case X86::COND_S: return X86::COND_NS;
1691 case X86::COND_NS: return X86::COND_S;
1692 case X86::COND_P: return X86::COND_NP;
1693 case X86::COND_NP: return X86::COND_P;
1694 case X86::COND_O: return X86::COND_NO;
1695 case X86::COND_NO: return X86::COND_O;
1696 }
1697 }
1698
1699 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1700 const MCInstrDesc &MCID = MI->getDesc();
1701 if (!MCID.isTerminator()) return false;
1702
1703 // Conditional branch is a special case.
1704 if (MCID.isBranch() && !MCID.isBarrier())
1705 return true;
1706 if (!MCID.isPredicable())
1707 return true;
1708 return !isPredicated(MI);
1709 }
1710
1711 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1712 MachineBasicBlock *&TBB,
1713 MachineBasicBlock *&FBB,
1714 SmallVectorImpl<MachineOperand> &Cond,
1715 bool AllowModify) const {
1716 // Start from the bottom of the block and work up, examining the
1717 // terminator instructions.
1718 MachineBasicBlock::iterator I = MBB.end();
1719 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1720 while (I != MBB.begin()) {
1721 --I;
1722 if (I->isDebugValue())
1723 continue;
1724
1725 // Working from the bottom, when we see a non-terminator instruction, we're
1726 // done.
1727 if (!isUnpredicatedTerminator(I))
1728 break;
1729
1730 // A terminator that isn't a branch can't easily be handled by this
1731 // analysis.
1732 if (!I->getDesc().isBranch())
1733 return true;
1734
1735 // Handle unconditional branches.
1736 if (I->getOpcode() == X86::JMP_4) {
1737 UnCondBrIter = I;
1738
1739 if (!AllowModify) {
1740 TBB = I->getOperand(0).getMBB();
1741 continue;
1742 }
1743
1744 // If the block has any instructions after a JMP, delete them.
1745 while (llvm::next(I) != MBB.end())
1746 llvm::next(I)->eraseFromParent();
1747
1748 Cond.clear();
1749 FBB = 0;
1750
1751 // Delete the JMP if it's equivalent to a fall-through.
1752 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1753 TBB = 0;
1754 I->eraseFromParent();
1755 I = MBB.end();
1756 UnCondBrIter = MBB.end();
1757 continue;
1758 }
1759
1760 // TBB is used to indicate the unconditional destination.
1761 TBB = I->getOperand(0).getMBB();
1762 continue;
1763 }
1764
1765 // Handle conditional branches.
1766 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1767 if (BranchCode == X86::COND_INVALID)
1768 return true; // Can't handle indirect branch.
1769
1770 // Working from the bottom, handle the first conditional branch.
1771 if (Cond.empty()) {
1772 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1773 if (AllowModify && UnCondBrIter != MBB.end() &&
1774 MBB.isLayoutSuccessor(TargetBB)) {
1775 // If we can modify the code and it ends in something like:
1776 //
1777 // jCC L1
1778 // jmp L2
1779 // L1:
1780 // ...
1781 // L2:
1782 //
1783 // Then we can change this to:
1784 //
1785 // jnCC L2
1786 // L1:
1787 // ...
1788 // L2:
1789 //
1790 // Which is a bit more efficient.
1791 // We conditionally jump to the fall-through block.
1792 BranchCode = GetOppositeBranchCondition(BranchCode);
1793 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1794 MachineBasicBlock::iterator OldInst = I;
1795
1796 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1797 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1798 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1799 .addMBB(TargetBB);
1800
1801 OldInst->eraseFromParent();
1802 UnCondBrIter->eraseFromParent();
1803
1804 // Restart the analysis.
1805 UnCondBrIter = MBB.end();
1806 I = MBB.end();
1807 continue;
1808 }
1809
1810 FBB = TBB;
1811 TBB = I->getOperand(0).getMBB();
1812 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1813 continue;
1814 }
1815
1816 // Handle subsequent conditional branches. Only handle the case where all
1817 // conditional branches branch to the same destination and their condition
1818 // opcodes fit one of the special multi-branch idioms.
1819 assert(Cond.size() == 1);
1820 assert(TBB);
1821
1822 // Only handle the case where all conditional branches branch to the same
1823 // destination.
1824 if (TBB != I->getOperand(0).getMBB())
1825 return true;
1826
1827 // If the conditions are the same, we can leave them alone.
1828 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1829 if (OldBranchCode == BranchCode)
1830 continue;
1831
1832 // If they differ, see if they fit one of the known patterns. Theoretically,
1833 // we could handle more patterns here, but we shouldn't expect to see them
1834 // if instruction selection has done a reasonable job.
1835 if ((OldBranchCode == X86::COND_NP &&
1836 BranchCode == X86::COND_E) ||
1837 (OldBranchCode == X86::COND_E &&
1838 BranchCode == X86::COND_NP))
1839 BranchCode = X86::COND_NP_OR_E;
1840 else if ((OldBranchCode == X86::COND_P &&
1841 BranchCode == X86::COND_NE) ||
1842 (OldBranchCode == X86::COND_NE &&
1843 BranchCode == X86::COND_P))
1844 BranchCode = X86::COND_NE_OR_P;
1845 else
1846 return true;
1847
1848 // Update the MachineOperand.
1849 Cond[0].setImm(BranchCode);
1850 }
1851
1852 return false;
1853 }
1854
1855 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1856 MachineBasicBlock::iterator I = MBB.end();
1857 unsigned Count = 0;
1858
1859 while (I != MBB.begin()) {
1860 --I;
1861 if (I->isDebugValue())
1862 continue;
1863 if (I->getOpcode() != X86::JMP_4 &&
1864 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1865 break;
1866 // Remove the branch.
1867 I->eraseFromParent();
1868 I = MBB.end();
1869 ++Count;
1870 }
1871
1872 return Count;
1873 }
1874
1875 unsigned
1876 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1877 MachineBasicBlock *FBB,
1878 const SmallVectorImpl<MachineOperand> &Cond,
1879 DebugLoc DL) const {
1880 // Shouldn't be a fall through.
1881 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1882 assert((Cond.size() == 1 || Cond.size() == 0) &&
1883 "X86 branch conditions have one component!");
1884
1885 if (Cond.empty()) {
1886 // Unconditional branch?
1887 assert(!FBB && "Unconditional branch with multiple successors!");
1888 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1889 return 1;
1890 }
1891
1892 // Conditional branch.
1893 unsigned Count = 0;
1894 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1895 switch (CC) {
1896 case X86::COND_NP_OR_E:
1897 // Synthesize NP_OR_E with two branches.
1898 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1899 ++Count;
1900 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1901 ++Count;
1902 break;
1903 case X86::COND_NE_OR_P:
1904 // Synthesize NE_OR_P with two branches.
1905 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1906 ++Count;
1907 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1908 ++Count;
1909 break;
1910 default: {
1911 unsigned Opc = GetCondBranchFromCond(CC);
1912 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1913 ++Count;
1914 }
1915 }
1916 if (FBB) {
1917 // Two-way Conditional branch. Insert the second branch.
1918 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1919 ++Count;
1920 }
1921 return Count;
1922 }
1923
1924 /// isHReg - Test if the given register is a physical h register.
1925 static bool isHReg(unsigned Reg) {
1926 return X86::GR8_ABCD_HRegClass.contains(Reg);
1927 }
1928
1929 // Try and copy between VR128/VR64 and GR64 registers.
1930 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg) {
1931 // SrcReg(VR128) -> DestReg(GR64)
1932 // SrcReg(VR64) -> DestReg(GR64)
1933 // SrcReg(GR64) -> DestReg(VR128)
1934 // SrcReg(GR64) -> DestReg(VR64)
1935
1936 if (X86::GR64RegClass.contains(DestReg)) {
1937 if (X86::VR128RegClass.contains(SrcReg)) {
1938 // Copy from a VR128 register to a GR64 register.
1939 return X86::MOVPQIto64rr;
1940 } else if (X86::VR64RegClass.contains(SrcReg)) {
1941 // Copy from a VR64 register to a GR64 register.
1942 return X86::MOVSDto64rr;
1943 }
1944 } else if (X86::GR64RegClass.contains(SrcReg)) {
1945 // Copy from a GR64 register to a VR128 register.
1946 if (X86::VR128RegClass.contains(DestReg))
1947 return X86::MOV64toPQIrr;
1948 // Copy from a GR64 register to a VR64 register.
1949 else if (X86::VR64RegClass.contains(DestReg))
1950 return X86::MOV64toSDrr;
1951 }
1952
1953 return 0;
1954 }
1955
1956 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1957 MachineBasicBlock::iterator MI, DebugLoc DL,
1958 unsigned DestReg, unsigned SrcReg,
1959 bool KillSrc) const {
1960 // First deal with the normal symmetric copies.
1961 unsigned Opc = 0;
1962 if (X86::GR64RegClass.contains(DestReg, SrcReg))
1963 Opc = X86::MOV64rr;
1964 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
1965 Opc = X86::MOV32rr;
1966 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
1967 Opc = X86::MOV16rr;
1968 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
1969 // Copying to or from a physical H register on x86-64 requires a NOREX
1970 // move. Otherwise use a normal move.
1971 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1972 TM.getSubtarget<X86Subtarget>().is64Bit())
1973 Opc = X86::MOV8rr_NOREX;
1974 else
1975 Opc = X86::MOV8rr;
1976 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
1977 Opc = X86::MOVAPSrr;
1978 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
1979 Opc = X86::MMX_MOVQ64rr;
1980 else
1981 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg);
1982
1983 if (Opc) {
1984 BuildMI(MBB, MI, DL, get(Opc), DestReg)
1985 .addReg(SrcReg, getKillRegState(KillSrc));
1986 return;
1987 }
1988
1989 // Moving EFLAGS to / from another register requires a push and a pop.
1990 if (SrcReg == X86::EFLAGS) {
1991 if (X86::GR64RegClass.contains(DestReg)) {
1992 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1993 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1994 return;
1995 } else if (X86::GR32RegClass.contains(DestReg)) {
1996 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
1997 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1998 return;
1999 }
2000 }
2001 if (DestReg == X86::EFLAGS) {
2002 if (X86::GR64RegClass.contains(SrcReg)) {
2003 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2004 .addReg(SrcReg, getKillRegState(KillSrc));
2005 BuildMI(MBB, MI, DL, get(X86::POPF64));
2006 return;
2007 } else if (X86::GR32RegClass.contains(SrcReg)) {
2008 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2009 .addReg(SrcReg, getKillRegState(KillSrc));
2010 BuildMI(MBB, MI, DL, get(X86::POPF32));
2011 return;
2012 }
2013 }
2014
2015 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2016 << " to " << RI.getName(DestReg) << '\n');
2017 llvm_unreachable("Cannot emit physreg copy instruction");
2018 }
2019
2020 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2021 const TargetRegisterClass *RC,
2022 bool isStackAligned,
2023 const TargetMachine &TM,
2024 bool load) {
2025 switch (RC->getSize()) {
2026 default:
2027 llvm_unreachable("Unknown spill size");
2028 case 1:
2029 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2030 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2031 // Copying to or from a physical H register on x86-64 requires a NOREX
2032 // move. Otherwise use a normal move.
2033 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2034 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2035 return load ? X86::MOV8rm : X86::MOV8mr;
2036 case 2:
2037 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2038 return load ? X86::MOV16rm : X86::MOV16mr;
2039 case 4:
2040 if (X86::GR32RegClass.hasSubClassEq(RC))
2041 return load ? X86::MOV32rm : X86::MOV32mr;
2042 if (X86::FR32RegClass.hasSubClassEq(RC))
2043 return load ? X86::MOVSSrm : X86::MOVSSmr;
2044 if (X86::RFP32RegClass.hasSubClassEq(RC))
2045 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2046 llvm_unreachable("Unknown 4-byte regclass");
2047 case 8:
2048 if (X86::GR64RegClass.hasSubClassEq(RC))
2049 return load ? X86::MOV64rm : X86::MOV64mr;
2050 if (X86::FR64RegClass.hasSubClassEq(RC))
2051 return load ? X86::MOVSDrm : X86::MOVSDmr;
2052 if (X86::VR64RegClass.hasSubClassEq(RC))
2053 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2054 if (X86::RFP64RegClass.hasSubClassEq(RC))
2055 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2056 llvm_unreachable("Unknown 8-byte regclass");
2057 case 10:
2058 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2059 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2060 case 16:
2061 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2062 // If stack is realigned we can use aligned stores.
2063 if (isStackAligned)
2064 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
2065 else
2066 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
2067 }
2068 }
2069
2070 static unsigned getStoreRegOpcode(unsigned SrcReg,
2071 const TargetRegisterClass *RC,
2072 bool isStackAligned,
2073 TargetMachine &TM) {
2074 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2075 }
2076
2077
2078 static unsigned getLoadRegOpcode(unsigned DestReg,
2079 const TargetRegisterClass *RC,
2080 bool isStackAligned,
2081 const TargetMachine &TM) {
2082 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2083 }
2084
2085 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2086 MachineBasicBlock::iterator MI,
2087 unsigned SrcReg, bool isKill, int FrameIdx,
2088 const TargetRegisterClass *RC,
2089 const TargetRegisterInfo *TRI) const {
2090 const MachineFunction &MF = *MBB.getParent();
2091 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2092 "Stack slot too small for store");
2093 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
2094 RI.canRealignStack(MF);
2095 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2096 DebugLoc DL = MBB.findDebugLoc(MI);
2097 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2098 .addReg(SrcReg, getKillRegState(isKill));
2099 }
2100
2101 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2102 bool isKill,
2103 SmallVectorImpl<MachineOperand> &Addr,
2104 const TargetRegisterClass *RC,
2105 MachineInstr::mmo_iterator MMOBegin,
2106 MachineInstr::mmo_iterator MMOEnd,
2107 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2108 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2109 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2110 DebugLoc DL;
2111 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2112 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2113 MIB.addOperand(Addr[i]);
2114 MIB.addReg(SrcReg, getKillRegState(isKill));
2115 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2116 NewMIs.push_back(MIB);
2117 }
2118
2119
2120 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2121 MachineBasicBlock::iterator MI,
2122 unsigned DestReg, int FrameIdx,
2123 const TargetRegisterClass *RC,
2124 const TargetRegisterInfo *TRI) const {
2125 const MachineFunction &MF = *MBB.getParent();
2126 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
2127 RI.canRealignStack(MF);
2128 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2129 DebugLoc DL = MBB.findDebugLoc(MI);
2130 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2131 }
2132
2133 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2134 SmallVectorImpl<MachineOperand> &Addr,
2135 const TargetRegisterClass *RC,
2136 MachineInstr::mmo_iterator MMOBegin,
2137 MachineInstr::mmo_iterator MMOEnd,
2138 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2139 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2140 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2141 DebugLoc DL;
2142 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2143 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2144 MIB.addOperand(Addr[i]);
2145 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2146 NewMIs.push_back(MIB);
2147 }
2148
2149 MachineInstr*
2150 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2151 int FrameIx, uint64_t Offset,
2152 const MDNode *MDPtr,
2153 DebugLoc DL) const {
2154 X86AddressMode AM;
2155 AM.BaseType = X86AddressMode::FrameIndexBase;
2156 AM.Base.FrameIndex = FrameIx;
2157 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2158 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2159 return &*MIB;
2160 }
2161
2162 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2163 const SmallVectorImpl<MachineOperand> &MOs,
2164 MachineInstr *MI,
2165 const TargetInstrInfo &TII) {
2166 // Create the base instruction with the memory operand as the first part.
2167 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2168 MI->getDebugLoc(), true);
2169 MachineInstrBuilder MIB(NewMI);
2170 unsigned NumAddrOps = MOs.size();
2171 for (unsigned i = 0; i != NumAddrOps; ++i)
2172 MIB.addOperand(MOs[i]);
2173 if (NumAddrOps < 4) // FrameIndex only
2174 addOffset(MIB, 0);
2175
2176 // Loop over the rest of the ri operands, converting them over.
2177 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2178 for (unsigned i = 0; i != NumOps; ++i) {
2179 MachineOperand &MO = MI->getOperand(i+2);
2180 MIB.addOperand(MO);
2181 }
2182 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2183 MachineOperand &MO = MI->getOperand(i);
2184 MIB.addOperand(MO);
2185 }
2186 return MIB;
2187 }
2188
2189 static MachineInstr *FuseInst(MachineFunction &MF,
2190 unsigned Opcode, unsigned OpNo,
2191 const SmallVectorImpl<MachineOperand> &MOs,
2192 MachineInstr *MI, const TargetInstrInfo &TII) {
2193 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2194 MI->getDebugLoc(), true);
2195 MachineInstrBuilder MIB(NewMI);
2196
2197 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2198 MachineOperand &MO = MI->getOperand(i);
2199 if (i == OpNo) {
2200 assert(MO.isReg() && "Expected to fold into reg operand!");
2201 unsigned NumAddrOps = MOs.size();
2202 for (unsigned i = 0; i != NumAddrOps; ++i)
2203 MIB.addOperand(MOs[i]);
2204 if (NumAddrOps < 4) // FrameIndex only
2205 addOffset(MIB, 0);
2206 } else {
2207 MIB.addOperand(MO);
2208 }
2209 }
2210 return MIB;
2211 }
2212
2213 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2214 const SmallVectorImpl<MachineOperand> &MOs,
2215 MachineInstr *MI) {
2216 MachineFunction &MF = *MI->getParent()->getParent();
2217 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2218
2219 unsigned NumAddrOps = MOs.size();
2220 for (unsigned i = 0; i != NumAddrOps; ++i)
2221 MIB.addOperand(MOs[i]);
2222 if (NumAddrOps < 4) // FrameIndex only
2223 addOffset(MIB, 0);
2224 return MIB.addImm(0);
2225 }
2226
2227 MachineInstr*
2228 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2229 MachineInstr *MI, unsigned i,
2230 const SmallVectorImpl<MachineOperand> &MOs,
2231 unsigned Size, unsigned Align) const {
2232 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2233 bool isTwoAddrFold = false;
2234 unsigned NumOps = MI->getDesc().getNumOperands();
2235 bool isTwoAddr = NumOps > 1 &&
2236 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2237
2238 // FIXME: AsmPrinter doesn't know how to handle
2239 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2240 if (MI->getOpcode() == X86::ADD32ri &&
2241 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2242 return NULL;
2243
2244 MachineInstr *NewMI = NULL;
2245 // Folding a memory location into the two-address part of a two-address
2246 // instruction is different than folding it other places. It requires
2247 // replacing the *two* registers with the memory location.
2248 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2249 MI->getOperand(0).isReg() &&
2250 MI->getOperand(1).isReg() &&
2251 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2252 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2253 isTwoAddrFold = true;
2254 } else if (i == 0) { // If operand 0
2255 if (MI->getOpcode() == X86::MOV64r0)
2256 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2257 else if (MI->getOpcode() == X86::MOV32r0)
2258 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2259 else if (MI->getOpcode() == X86::MOV16r0)
2260 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2261 else if (MI->getOpcode() == X86::MOV8r0)
2262 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2263 if (NewMI)
2264 return NewMI;
2265
2266 OpcodeTablePtr = &RegOp2MemOpTable0;
2267 } else if (i == 1) {
2268 OpcodeTablePtr = &RegOp2MemOpTable1;
2269 } else if (i == 2) {
2270 OpcodeTablePtr = &RegOp2MemOpTable2;
2271 }
2272
2273 // If table selected...
2274 if (OpcodeTablePtr) {
2275 // Find the Opcode to fuse
2276 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2277 OpcodeTablePtr->find(MI->getOpcode());
2278 if (I != OpcodeTablePtr->end()) {
2279 unsigned Opcode = I->second.first;
2280 unsigned MinAlign = I->second.second;
2281 if (Align < MinAlign)
2282 return NULL;
2283 bool NarrowToMOV32rm = false;
2284 if (Size) {
2285 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2286 if (Size < RCSize) {
2287 // Check if it's safe to fold the load. If the size of the object is
2288 // narrower than the load width, then it's not.
2289 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2290 return NULL;
2291 // If this is a 64-bit load, but the spill slot is 32, then we can do
2292 // a 32-bit load which is implicitly zero-extended. This likely is due
2293 // to liveintervalanalysis remat'ing a load from stack slot.
2294 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2295 return NULL;
2296 Opcode = X86::MOV32rm;
2297 NarrowToMOV32rm = true;
2298 }
2299 }
2300
2301 if (isTwoAddrFold)
2302 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2303 else
2304 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2305
2306 if (NarrowToMOV32rm) {
2307 // If this is the special case where we use a MOV32rm to load a 32-bit
2308 // value and zero-extend the top bits. Change the destination register
2309 // to a 32-bit one.
2310 unsigned DstReg = NewMI->getOperand(0).getReg();
2311 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2312 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2313 X86::sub_32bit));
2314 else
2315 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2316 }
2317 return NewMI;
2318 }
2319 }
2320
2321 // No fusion
2322 if (PrintFailedFusing && !MI->isCopy())
2323 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2324 return NULL;
2325 }
2326
2327
2328 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2329 MachineInstr *MI,
2330 const SmallVectorImpl<unsigned> &Ops,
2331 int FrameIndex) const {
2332 // Check switch flag
2333 if (NoFusing) return NULL;
2334
2335 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2336 switch (MI->getOpcode()) {
2337 case X86::CVTSD2SSrr:
2338 case X86::Int_CVTSD2SSrr:
2339 case X86::CVTSS2SDrr:
2340 case X86::Int_CVTSS2SDrr:
2341 case X86::RCPSSr:
2342 case X86::RCPSSr_Int:
2343 case X86::ROUNDSDr:
2344 case X86::ROUNDSSr:
2345 case X86::RSQRTSSr:
2346 case X86::RSQRTSSr_Int:
2347 case X86::SQRTSSr:
2348 case X86::SQRTSSr_Int:
2349 return 0;
2350 }
2351
2352 const MachineFrameInfo *MFI = MF.getFrameInfo();
2353 unsigned Size = MFI->getObjectSize(FrameIndex);
2354 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2355 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2356 unsigned NewOpc = 0;
2357 unsigned RCSize = 0;
2358 switch (MI->getOpcode()) {
2359 default: return NULL;
2360 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2361 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2362 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2363 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2364 }
2365 // Check if it's safe to fold the load. If the size of the object is
2366 // narrower than the load width, then it's not.
2367 if (Size < RCSize)
2368 return NULL;
2369 // Change to CMPXXri r, 0 first.
2370 MI->setDesc(get(NewOpc));
2371 MI->getOperand(1).ChangeToImmediate(0);
2372 } else if (Ops.size() != 1)
2373 return NULL;
2374
2375 SmallVector<MachineOperand,4> MOs;
2376 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2377 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2378 }
2379
2380 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2381 MachineInstr *MI,
2382 const SmallVectorImpl<unsigned> &Ops,
2383 MachineInstr *LoadMI) const {
2384 // Check switch flag
2385 if (NoFusing) return NULL;
2386
2387 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2388 switch (MI->getOpcode()) {
2389 case X86::CVTSD2SSrr:
2390 case X86::Int_CVTSD2SSrr:
2391 case X86::CVTSS2SDrr:
2392 case X86::Int_CVTSS2SDrr:
2393 case X86::RCPSSr:
2394 case X86::RCPSSr_Int:
2395 case X86::ROUNDSDr:
2396 case X86::ROUNDSSr:
2397 case X86::RSQRTSSr:
2398 case X86::RSQRTSSr_Int:
2399 case X86::SQRTSSr:
2400 case X86::SQRTSSr_Int:
2401 return 0;
2402 }
2403
2404 // Determine the alignment of the load.
2405 unsigned Alignment = 0;
2406 if (LoadMI->hasOneMemOperand())
2407 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2408 else
2409 switch (LoadMI->getOpcode()) {
2410 case X86::AVX_SET0PSY:
2411 case X86::AVX_SET0PDY:
2412 Alignment = 32;
2413 break;
2414 case X86::V_SET0PS:
2415 case X86::V_SET0PD:
2416 case X86::V_SET0PI:
2417 case X86::V_SETALLONES:
2418 case X86::AVX_SET0PS:
2419 case X86::AVX_SET0PD:
2420 case X86::AVX_SET0PI:
2421 Alignment = 16;
2422 break;
2423 case X86::FsFLD0SD:
2424 case X86::VFsFLD0SD:
2425 Alignment = 8;
2426 break;
2427 case X86::FsFLD0SS:
2428 case X86::VFsFLD0SS:
2429 Alignment = 4;
2430 break;
2431 default:
2432 return 0;
2433 }
2434 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2435 unsigned NewOpc = 0;
2436 switch (MI->getOpcode()) {
2437 default: return NULL;
2438 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2439 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2440 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2441 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2442 }
2443 // Change to CMPXXri r, 0 first.
2444 MI->setDesc(get(NewOpc));
2445 MI->getOperand(1).ChangeToImmediate(0);
2446 } else if (Ops.size() != 1)
2447 return NULL;
2448
2449 // Make sure the subregisters match.
2450 // Otherwise we risk changing the size of the load.
2451 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2452 return NULL;
2453
2454 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2455 switch (LoadMI->getOpcode()) {
2456 case X86::V_SET0PS:
2457 case X86::V_SET0PD:
2458 case X86::V_SET0PI:
2459 case X86::V_SETALLONES:
2460 case X86::AVX_SET0PS:
2461 case X86::AVX_SET0PD:
2462 case X86::AVX_SET0PI:
2463 case X86::AVX_SET0PSY:
2464 case X86::AVX_SET0PDY:
2465 case X86::FsFLD0SD:
2466 case X86::FsFLD0SS: {
2467 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2468 // Create a constant-pool entry and operands to load from it.
2469
2470 // Medium and large mode can't fold loads this way.
2471 if (TM.getCodeModel() != CodeModel::Small &&
2472 TM.getCodeModel() != CodeModel::Kernel)
2473 return NULL;
2474
2475 // x86-32 PIC requires a PIC base register for constant pools.
2476 unsigned PICBase = 0;
2477 if (TM.getRelocationModel() == Reloc::PIC_) {
2478 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2479 PICBase = X86::RIP;
2480 else
2481 // FIXME: PICBase = getGlobalBaseReg(&MF);
2482 // This doesn't work for several reasons.
2483 // 1. GlobalBaseReg may have been spilled.
2484 // 2. It may not be live at MI.
2485 return NULL;
2486 }
2487
2488 // Create a constant-pool entry.
2489 MachineConstantPool &MCP = *MF.getConstantPool();
2490 const Type *Ty;
2491 unsigned Opc = LoadMI->getOpcode();
2492 if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS)
2493 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2494 else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD)
2495 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2496 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2497 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2498 else
2499 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2500 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2501 Constant::getAllOnesValue(Ty) :
2502 Constant::getNullValue(Ty);
2503 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2504
2505 // Create operands to load from the constant pool entry.
2506 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2507 MOs.push_back(MachineOperand::CreateImm(1));
2508 MOs.push_back(MachineOperand::CreateReg(0, false));
2509 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2510 MOs.push_back(MachineOperand::CreateReg(0, false));
2511 break;
2512 }
2513 default: {
2514 // Folding a normal load. Just copy the load's address operands.
2515 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2516 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2517 MOs.push_back(LoadMI->getOperand(i));
2518 break;
2519 }
2520 }
2521 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2522 }
2523
2524
2525 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2526 const SmallVectorImpl<unsigned> &Ops) const {
2527 // Check switch flag
2528 if (NoFusing) return 0;
2529
2530 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2531 switch (MI->getOpcode()) {
2532 default: return false;
2533 case X86::TEST8rr:
2534 case X86::TEST16rr:
2535 case X86::TEST32rr:
2536 case X86::TEST64rr:
2537 return true;
2538 case X86::ADD32ri:
2539 // FIXME: AsmPrinter doesn't know how to handle
2540 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2541 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2542 return false;
2543 break;
2544 }
2545 }
2546
2547 if (Ops.size() != 1)
2548 return false;
2549
2550 unsigned OpNum = Ops[0];
2551 unsigned Opc = MI->getOpcode();
2552 unsigned NumOps = MI->getDesc().getNumOperands();
2553 bool isTwoAddr = NumOps > 1 &&
2554 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2555
2556 // Folding a memory location into the two-address part of a two-address
2557 // instruction is different than folding it other places. It requires
2558 // replacing the *two* registers with the memory location.
2559 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2560 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2561 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2562 } else if (OpNum == 0) { // If operand 0
2563 switch (Opc) {
2564 case X86::MOV8r0:
2565 case X86::MOV16r0:
2566 case X86::MOV32r0:
2567 case X86::MOV64r0: return true;
2568 default: break;
2569 }
2570 OpcodeTablePtr = &RegOp2MemOpTable0;
2571 } else if (OpNum == 1) {
2572 OpcodeTablePtr = &RegOp2MemOpTable1;
2573 } else if (OpNum == 2) {
2574 OpcodeTablePtr = &RegOp2MemOpTable2;
2575 }
2576
2577 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2578 return true;
2579 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2580 }
2581
2582 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2583 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2584 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2585 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2586 MemOp2RegOpTable.find(MI->getOpcode());
2587 if (I == MemOp2RegOpTable.end())
2588 return false;
2589 unsigned Opc = I->second.first;
2590 unsigned Index = I->second.second & 0xf;
2591 bool FoldedLoad = I->second.second & (1 << 4);
2592 bool FoldedStore = I->second.second & (1 << 5);
2593 if (UnfoldLoad && !FoldedLoad)
2594 return false;
2595 UnfoldLoad &= FoldedLoad;
2596 if (UnfoldStore && !FoldedStore)
2597 return false;
2598 UnfoldStore &= FoldedStore;
2599
2600 const MCInstrDesc &MCID = get(Opc);
2601 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2602 if (!MI->hasOneMemOperand() &&
2603 RC == &X86::VR128RegClass &&
2604 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2605 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2606 // conservatively assume the address is unaligned. That's bad for
2607 // performance.
2608 return false;
2609 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2610 SmallVector<MachineOperand,2> BeforeOps;
2611 SmallVector<MachineOperand,2> AfterOps;
2612 SmallVector<MachineOperand,4> ImpOps;
2613 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2614 MachineOperand &Op = MI->getOperand(i);
2615 if (i >= Index && i < Index + X86::AddrNumOperands)
2616 AddrOps.push_back(Op);
2617 else if (Op.isReg() && Op.isImplicit())
2618 ImpOps.push_back(Op);
2619 else if (i < Index)
2620 BeforeOps.push_back(Op);
2621 else if (i > Index)
2622 AfterOps.push_back(Op);
2623 }
2624
2625 // Emit the load instruction.
2626 if (UnfoldLoad) {
2627 std::pair<MachineInstr::mmo_iterator,
2628 MachineInstr::mmo_iterator> MMOs =
2629 MF.extractLoadMemRefs(MI->memoperands_begin(),
2630 MI->memoperands_end());
2631 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2632 if (UnfoldStore) {
2633 // Address operands cannot be marked isKill.
2634 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2635 MachineOperand &MO = NewMIs[0]->getOperand(i);
2636 if (MO.isReg())
2637 MO.setIsKill(false);
2638 }
2639 }
2640 }
2641
2642 // Emit the data processing instruction.
2643 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
2644 MachineInstrBuilder MIB(DataMI);
2645
2646 if (FoldedStore)
2647 MIB.addReg(Reg, RegState::Define);
2648 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2649 MIB.addOperand(BeforeOps[i]);
2650 if (FoldedLoad)
2651 MIB.addReg(Reg);
2652 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2653 MIB.addOperand(AfterOps[i]);
2654 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2655 MachineOperand &MO = ImpOps[i];
2656 MIB.addReg(MO.getReg(),
2657 getDefRegState(MO.isDef()) |
2658 RegState::Implicit |
2659 getKillRegState(MO.isKill()) |
2660 getDeadRegState(MO.isDead()) |
2661 getUndefRegState(MO.isUndef()));
2662 }
2663 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2664 unsigned NewOpc = 0;
2665 switch (DataMI->getOpcode()) {
2666 default: break;
2667 case X86::CMP64ri32:
2668 case X86::CMP64ri8:
2669 case X86::CMP32ri:
2670 case X86::CMP32ri8:
2671 case X86::CMP16ri:
2672 case X86::CMP16ri8:
2673 case X86::CMP8ri: {
2674 MachineOperand &MO0 = DataMI->getOperand(0);
2675 MachineOperand &MO1 = DataMI->getOperand(1);
2676 if (MO1.getImm() == 0) {
2677 switch (DataMI->getOpcode()) {
2678 default: break;
2679 case X86::CMP64ri8:
2680 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2681 case X86::CMP32ri8:
2682 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2683 case X86::CMP16ri8:
2684 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2685 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2686 }
2687 DataMI->setDesc(get(NewOpc));
2688 MO1.ChangeToRegister(MO0.getReg(), false);
2689 }
2690 }
2691 }
2692 NewMIs.push_back(DataMI);
2693
2694 // Emit the store instruction.
2695 if (UnfoldStore) {
2696 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
2697 std::pair<MachineInstr::mmo_iterator,
2698 MachineInstr::mmo_iterator> MMOs =
2699 MF.extractStoreMemRefs(MI->memoperands_begin(),
2700 MI->memoperands_end());
2701 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2702 }
2703
2704 return true;
2705 }
2706
2707 bool
2708 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2709 SmallVectorImpl<SDNode*> &NewNodes) const {
2710 if (!N->isMachineOpcode())
2711 return false;
2712
2713 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2714 MemOp2RegOpTable.find(N->getMachineOpcode());
2715 if (I == MemOp2RegOpTable.end())
2716 return false;
2717 unsigned Opc = I->second.first;
2718 unsigned Index = I->second.second & 0xf;
2719 bool FoldedLoad = I->second.second & (1 << 4);
2720 bool FoldedStore = I->second.second & (1 << 5);
2721 const MCInstrDesc &MCID = get(Opc);
2722 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2723 unsigned NumDefs = MCID.NumDefs;
2724 std::vector<SDValue> AddrOps;
2725 std::vector<SDValue> BeforeOps;
2726 std::vector<SDValue> AfterOps;
2727 DebugLoc dl = N->getDebugLoc();
2728 unsigned NumOps = N->getNumOperands();
2729 for (unsigned i = 0; i != NumOps-1; ++i) {
2730 SDValue Op = N->getOperand(i);
2731 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2732 AddrOps.push_back(Op);
2733 else if (i < Index-NumDefs)
2734 BeforeOps.push_back(Op);
2735 else if (i > Index-NumDefs)
2736 AfterOps.push_back(Op);
2737 }
2738 SDValue Chain = N->getOperand(NumOps-1);
2739 AddrOps.push_back(Chain);
2740
2741 // Emit the load instruction.
2742 SDNode *Load = 0;
2743 MachineFunction &MF = DAG.getMachineFunction();
2744 if (FoldedLoad) {
2745 EVT VT = *RC->vt_begin();
2746 std::pair<MachineInstr::mmo_iterator,
2747 MachineInstr::mmo_iterator> MMOs =
2748 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2749 cast<MachineSDNode>(N)->memoperands_end());
2750 if (!(*MMOs.first) &&
2751 RC == &X86::VR128RegClass &&
2752 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2753 // Do not introduce a slow unaligned load.
2754 return false;
2755 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2756 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2757 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2758 NewNodes.push_back(Load);
2759
2760 // Preserve memory reference information.
2761 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2762 }
2763
2764 // Emit the data processing instruction.
2765 std::vector<EVT> VTs;
2766 const TargetRegisterClass *DstRC = 0;
2767 if (MCID.getNumDefs() > 0) {
2768 DstRC = getRegClass(MCID, 0, &RI);
2769 VTs.push_back(*DstRC->vt_begin());
2770 }
2771 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2772 EVT VT = N->getValueType(i);
2773 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
2774 VTs.push_back(VT);
2775 }
2776 if (Load)
2777 BeforeOps.push_back(SDValue(Load, 0));
2778 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2779 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2780 BeforeOps.size());
2781 NewNodes.push_back(NewNode);
2782
2783 // Emit the store instruction.
2784 if (FoldedStore) {
2785 AddrOps.pop_back();
2786 AddrOps.push_back(SDValue(NewNode, 0));
2787 AddrOps.push_back(Chain);
2788 std::pair<MachineInstr::mmo_iterator,
2789 MachineInstr::mmo_iterator> MMOs =
2790 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2791 cast<MachineSDNode>(N)->memoperands_end());
2792 if (!(*MMOs.first) &&
2793 RC == &X86::VR128RegClass &&
2794 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2795 // Do not introduce a slow unaligned store.
2796 return false;
2797 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2798 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2799 isAligned, TM),
2800 dl, MVT::Other,
2801 &AddrOps[0], AddrOps.size());
2802 NewNodes.push_back(Store);
2803
2804 // Preserve memory reference information.
2805 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2806 }
2807
2808 return true;
2809 }
2810
2811 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2812 bool UnfoldLoad, bool UnfoldStore,
2813 unsigned *LoadRegIndex) const {
2814 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2815 MemOp2RegOpTable.find(Opc);
2816 if (I == MemOp2RegOpTable.end())
2817 return 0;
2818 bool FoldedLoad = I->second.second & (1 << 4);
2819 bool FoldedStore = I->second.second & (1 << 5);
2820 if (UnfoldLoad && !FoldedLoad)
2821 return 0;
2822 if (UnfoldStore && !FoldedStore)
2823 return 0;
2824 if (LoadRegIndex)
2825 *LoadRegIndex = I->second.second & 0xf;
2826 return I->second.first;
2827 }
2828
2829 bool
2830 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2831 int64_t &Offset1, int64_t &Offset2) const {
2832 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2833 return false;
2834 unsigned Opc1 = Load1->getMachineOpcode();
2835 unsigned Opc2 = Load2->getMachineOpcode();
2836 switch (Opc1) {
2837 default: return false;
2838 case X86::MOV8rm:
2839 case X86::MOV16rm:
2840 case X86::MOV32rm:
2841 case X86::MOV64rm:
2842 case X86::LD_Fp32m:
2843 case X86::LD_Fp64m:
2844 case X86::LD_Fp80m:
2845 case X86::MOVSSrm:
2846 case X86::MOVSDrm:
2847 case X86::MMX_MOVD64rm:
2848 case X86::MMX_MOVQ64rm:
2849 case X86::FsMOVAPSrm:
2850 case X86::FsMOVAPDrm:
2851 case X86::MOVAPSrm:
2852 case X86::MOVUPSrm:
2853 case X86::MOVAPDrm:
2854 case X86::MOVDQArm:
2855 case X86::MOVDQUrm:
2856 break;
2857 }
2858 switch (Opc2) {
2859 default: return false;
2860 case X86::MOV8rm:
2861 case X86::MOV16rm:
2862 case X86::MOV32rm:
2863 case X86::MOV64rm:
2864 case X86::LD_Fp32m:
2865 case X86::LD_Fp64m:
2866 case X86::LD_Fp80m:
2867 case X86::MOVSSrm:
2868 case X86::MOVSDrm:
2869 case X86::MMX_MOVD64rm:
2870 case X86::MMX_MOVQ64rm:
2871 case X86::FsMOVAPSrm:
2872 case X86::FsMOVAPDrm:
2873 case X86::MOVAPSrm:
2874 case X86::MOVUPSrm:
2875 case X86::MOVAPDrm:
2876 case X86::MOVDQArm:
2877 case X86::MOVDQUrm:
2878 break;
2879 }
2880
2881 // Check if chain operands and base addresses match.
2882 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2883 Load1->getOperand(5) != Load2->getOperand(5))
2884 return false;
2885 // Segment operands should match as well.
2886 if (Load1->getOperand(4) != Load2->getOperand(4))
2887 return false;
2888 // Scale should be 1, Index should be Reg0.
2889 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2890 Load1->getOperand(2) == Load2->getOperand(2)) {
2891 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2892 return false;
2893
2894 // Now let's examine the displacements.
2895 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2896 isa<ConstantSDNode>(Load2->getOperand(3))) {
2897 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2898 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2899 return true;
2900 }
2901 }
2902 return false;
2903 }
2904
2905 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2906 int64_t Offset1, int64_t Offset2,
2907 unsigned NumLoads) const {
2908 assert(Offset2 > Offset1);
2909 if ((Offset2 - Offset1) / 8 > 64)
2910 return false;
2911
2912 unsigned Opc1 = Load1->getMachineOpcode();
2913 unsigned Opc2 = Load2->getMachineOpcode();
2914 if (Opc1 != Opc2)
2915 return false; // FIXME: overly conservative?
2916
2917 switch (Opc1) {
2918 default: break;
2919 case X86::LD_Fp32m:
2920 case X86::LD_Fp64m:
2921 case X86::LD_Fp80m:
2922 case X86::MMX_MOVD64rm:
2923 case X86::MMX_MOVQ64rm:
2924 return false;
2925 }
2926
2927 EVT VT = Load1->getValueType(0);
2928 switch (VT.getSimpleVT().SimpleTy) {
2929 default:
2930 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2931 // have 16 of them to play with.
2932 if (TM.getSubtargetImpl()->is64Bit()) {
2933 if (NumLoads >= 3)
2934 return false;
2935 } else if (NumLoads) {
2936 return false;
2937 }
2938 break;
2939 case MVT::i8:
2940 case MVT::i16:
2941 case MVT::i32:
2942 case MVT::i64:
2943 case MVT::f32:
2944 case MVT::f64:
2945 if (NumLoads)
2946 return false;
2947 break;
2948 }
2949
2950 return true;
2951 }
2952
2953
2954 bool X86InstrInfo::
2955 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2956 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2957 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2958 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2959 return true;
2960 Cond[0].setImm(GetOppositeBranchCondition(CC));
2961 return false;
2962 }
2963
2964 bool X86InstrInfo::
2965 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2966 // FIXME: Return false for x87 stack register classes for now. We can't
2967 // allow any loads of these registers before FpGet_ST0_80.
2968 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2969 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2970 }
2971
2972
2973 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
2974 /// register? e.g. r8, xmm8, xmm13, etc.
2975 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
2976 switch (RegNo) {
2977 default: break;
2978 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2979 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2980 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2981 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2982 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2983 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2984 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2985 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2986 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2987 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2988 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
2989 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
2990 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
2991 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
2992 return true;
2993 }
2994 return false;
2995 }
2996
2997 /// getGlobalBaseReg - Return a virtual register initialized with the
2998 /// the global base register value. Output instructions required to
2999 /// initialize the register in the function entry block, if necessary.
3000 ///
3001 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3002 ///
3003 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3004 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3005 "X86-64 PIC uses RIP relative addressing");
3006
3007 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3008 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3009 if (GlobalBaseReg != 0)
3010 return GlobalBaseReg;
3011
3012 // Create the register. The code to initialize it is inserted
3013 // later, by the CGBR pass (below).
3014 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3015 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3016 X86FI->setGlobalBaseReg(GlobalBaseReg);
3017 return GlobalBaseReg;
3018 }
3019
3020 // These are the replaceable SSE instructions. Some of these have Int variants
3021 // that we don't include here. We don't want to replace instructions selected
3022 // by intrinsics.
3023 static const unsigned ReplaceableInstrs[][3] = {
3024 //PackedSingle PackedDouble PackedInt
3025 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3026 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3027 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3028 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3029 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3030 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3031 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3032 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3033 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3034 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3035 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3036 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3037 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3038 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3039 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3040 // AVX 128-bit support
3041 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3042 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3043 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3044 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3045 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3046 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3047 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3048 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3049 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3050 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3051 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3052 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3053 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3054 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3055 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3056 };
3057
3058 // FIXME: Some shuffle and unpack instructions have equivalents in different
3059 // domains, but they require a bit more work than just switching opcodes.
3060
3061 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3062 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3063 if (ReplaceableInstrs[i][domain-1] == opcode)
3064 return ReplaceableInstrs[i];
3065 return 0;
3066 }
3067
3068 std::pair<uint16_t, uint16_t>
3069 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3070 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3071 return std::make_pair(domain,
3072 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3073 }
3074
3075 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3076 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3077 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3078 assert(dom && "Not an SSE instruction");
3079 const unsigned *table = lookup(MI->getOpcode(), dom);
3080 assert(table && "Cannot change domain");
3081 MI->setDesc(get(table[Domain-1]));
3082 }
3083
3084 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3085 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3086 NopInst.setOpcode(X86::NOOP);
3087 }
3088
3089 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3090 switch (opc) {
3091 default: return false;
3092 case X86::DIVSDrm:
3093 case X86::DIVSDrm_Int:
3094 case X86::DIVSDrr:
3095 case X86::DIVSDrr_Int:
3096 case X86::DIVSSrm:
3097 case X86::DIVSSrm_Int:
3098 case X86::DIVSSrr:
3099 case X86::DIVSSrr_Int:
3100 case X86::SQRTPDm:
3101 case X86::SQRTPDm_Int:
3102 case X86::SQRTPDr:
3103 case X86::SQRTPDr_Int:
3104 case X86::SQRTPSm:
3105 case X86::SQRTPSm_Int:
3106 case X86::SQRTPSr:
3107 case X86::SQRTPSr_Int:
3108 case X86::SQRTSDm:
3109 case X86::SQRTSDm_Int:
3110 case X86::SQRTSDr:
3111 case X86::SQRTSDr_Int:
3112 case X86::SQRTSSm:
3113 case X86::SQRTSSm_Int:
3114 case X86::SQRTSSr:
3115 case X86::SQRTSSr_Int:
3116 return true;
3117 }
3118 }
3119
3120 bool X86InstrInfo::
3121 hasHighOperandLatency(const InstrItineraryData *ItinData,
3122 const MachineRegisterInfo *MRI,
3123 const MachineInstr *DefMI, unsigned DefIdx,
3124 const MachineInstr *UseMI, unsigned UseIdx) const {
3125 return isHighLatencyDef(DefMI->getOpcode());
3126 }
3127
3128 namespace {
3129 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3130 /// global base register for x86-32.
3131 struct CGBR : public MachineFunctionPass {
3132 static char ID;
3133 CGBR() : MachineFunctionPass(ID) {}
3134
3135 virtual bool runOnMachineFunction(MachineFunction &MF) {
3136 const X86TargetMachine *TM =
3137 static_cast<const X86TargetMachine *>(&MF.getTarget());
3138
3139 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3140 "X86-64 PIC uses RIP relative addressing");
3141
3142 // Only emit a global base reg in PIC mode.
3143 if (TM->getRelocationModel() != Reloc::PIC_)
3144 return false;
3145
3146 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3147 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3148
3149 // If we didn't need a GlobalBaseReg, don't insert code.
3150 if (GlobalBaseReg == 0)
3151 return false;
3152
3153 // Insert the set of GlobalBaseReg into the first MBB of the function
3154 MachineBasicBlock &FirstMBB = MF.front();
3155 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3156 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3157 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3158 const X86InstrInfo *TII = TM->getInstrInfo();
3159
3160 unsigned PC;
3161 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3162 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3163 else
3164 PC = GlobalBaseReg;
3165
3166 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3167 // only used in JIT code emission as displacement to pc.
3168 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3169
3170 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3171 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3172 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3173 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3174 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3175 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3176 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3177 }
3178
3179 return true;
3180 }
3181
3182 virtual const char *getPassName() const {
3183 return "X86 PIC Global Base Reg Initialization";
3184 }
3185
3186 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3187 AU.setPreservesCFG();
3188 MachineFunctionPass::getAnalysisUsage(AU);
3189 }
3190 };
3191 }
3192
3193 char CGBR::ID = 0;
3194 FunctionPass*
3195 llvm::createGlobalBaseRegPass() { return new CGBR(); }
STM8 backend for LLVM