lib/Target/X86/X86RegisterInfo.h

   1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef X86REGISTERINFO_H
  15 #define X86REGISTERINFO_H
  16
  17 #include "llvm/Target/TargetRegisterInfo.h"
  18
  19 #define GET_REGINFO_HEADER
  20 #include "X86GenRegisterInfo.inc"
  21
  22 namespace llvm {
  23   class Type;
  24   class TargetInstrInfo;
  25   class X86TargetMachine;
  26
  27 /// N86 namespace - Native X86 register numbers
  28 ///
  29 namespace N86 {
  30   enum {
  31     EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
  32   };
  33 }
  34
  35 /// DWARFFlavour - Flavour of dwarf regnumbers
  36 ///
  37 namespace DWARFFlavour {
  38   enum {
  39     X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
  40   };
  41 }
  42
  43 class X86RegisterInfo : public X86GenRegisterInfo {
  44 public:
  45   X86TargetMachine &TM;
  46   const TargetInstrInfo &TII;
  47
  48 private:
  49   /// Is64Bit - Is the target 64-bits.
  50   ///
  51   bool Is64Bit;
  52
  53   /// IsWin64 - Is the target on of win64 flavours
  54   ///
  55   bool IsWin64;
  56
  57   /// SlotSize - Stack slot size in bytes.
  58   ///
  59   unsigned SlotSize;
  60
  61   /// StackPtr - X86 physical register used as stack ptr.
  62   ///
  63   unsigned StackPtr;
  64
  65   /// FramePtr - X86 physical register used as frame ptr.
  66   ///
  67   unsigned FramePtr;
  68
  69 public:
  70   X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
  71
  72   /// getX86RegNum - Returns the native X86 register number for the given LLVM
  73   /// register identifier.
  74   static unsigned getX86RegNum(unsigned RegNo);
  75
  76   /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
  77   /// (created by TableGen) for target dependencies.
  78   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
  79   int getLLVMRegNum(unsigned RegNum, bool isEH) const;
  80
  81   // FIXME: This should be tablegen'd like getDwarfRegNum is
  82   int getSEHRegNum(unsigned i) const;
  83
  84   /// getCompactUnwindRegNum - This function maps the register to the number for
  85   /// compact unwind encoding. Return -1 if the register isn't valid.
  86   int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
  87
  88   /// Code Generation virtual methods...
  89   ///
  90
  91   /// getMatchingSuperRegClass - Return a subclass of the specified register
  92   /// class A so that each register in it has a sub-register of the
  93   /// specified sub-register index which is in the specified register class B.
  94   virtual const TargetRegisterClass *
  95   getMatchingSuperRegClass(const TargetRegisterClass *A,
  96                            const TargetRegisterClass *B, unsigned Idx) const;
  97
  98   const TargetRegisterClass*
  99   getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
 100
 101   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
 102   /// values.
 103   const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
 104
 105   /// getCrossCopyRegClass - Returns a legal register class to copy a register
 106   /// in the specified class to or from. Returns NULL if it is possible to copy
 107   /// between a two registers of the specified class.
 108   const TargetRegisterClass *
 109   getCrossCopyRegClass(const TargetRegisterClass *RC) const;
 110
 111   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
 112                                MachineFunction &MF) const;
 113
 114   /// getCalleeSavedRegs - Return a null-terminated list of all of the
 115   /// callee-save registers on this target.
 116   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 117
 118   /// getReservedRegs - Returns a bitset indexed by physical register number
 119   /// indicating if a register is a special register that has particular uses and
 120   /// should be considered unavailable at all times, e.g. SP, RA. This is used by
 121   /// register scavenger to determine what registers are free.
 122   BitVector getReservedRegs(const MachineFunction &MF) const;
 123
 124   bool canRealignStack(const MachineFunction &MF) const;
 125
 126   bool needsStackRealignment(const MachineFunction &MF) const;
 127
 128   bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
 129                             int &FrameIdx) const;
 130
 131   void eliminateCallFramePseudoInstr(MachineFunction &MF,
 132                                      MachineBasicBlock &MBB,
 133                                      MachineBasicBlock::iterator MI) const;
 134
 135   void eliminateFrameIndex(MachineBasicBlock::iterator MI,
 136                            int SPAdj, RegScavenger *RS = NULL) const;
 137
 138   // Debug information queries.
 139   unsigned getRARegister() const;
 140   unsigned getFrameRegister(const MachineFunction &MF) const;
 141   unsigned getStackRegister() const { return StackPtr; }
 142   // FIXME: Move to FrameInfok
 143   unsigned getSlotSize() const { return SlotSize; }
 144
 145   // Exception handling queries.
 146   unsigned getEHExceptionRegister() const;
 147   unsigned getEHHandlerRegister() const;
 148 };
 149
 150 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
 151 // register of a specific X86 register.
 152 // e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX
 153 unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false);
 154
 155 } // End llvm namespace
 156
 157 #endif