lib/CodeGen/RegAllocBase.h

   1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RegAllocBase class, which is the skeleton of a basic
  11 // register allocation algorithm and interface for extending it. It provides the
  12 // building blocks on which to construct other experimental allocators and test
  13 // the validity of two principles:
  14 //
  15 // - If virtual and physical register liveness is modeled using intervals, then
  16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
  17 // lazily cached and reused.
  18 //
  19 // - Register allocation complexity, and generated code performance is
  20 // determined by the effectiveness of live range splitting rather than optimal
  21 // coloring.
  22 //
  23 // Following the first principle, interfering checking revolves around the
  24 // LiveIntervalUnion data structure.
  25 //
  26 // To fulfill the second principle, the basic allocator provides a driver for
  27 // incremental splitting. It essentially punts on the problem of register
  28 // coloring, instead driving the assignment of virtual to physical registers by
  29 // the cost of splitting. The basic allocator allows for heuristic reassignment
  30 // of registers, if a more sophisticated allocator chooses to do that.
  31 //
  32 // This framework provides a way to engineer the compile time vs. code
  33 // quality trade-off without relying on a particular theoretical solver.
  34 //
  35 //===----------------------------------------------------------------------===//
  36
  37 #ifndef LLVM_CODEGEN_REGALLOCBASE
  38 #define LLVM_CODEGEN_REGALLOCBASE
  39
  40 #include "llvm/ADT/OwningPtr.h"
  41 #include "LiveIntervalUnion.h"
  42 #include "RegisterClassInfo.h"
  43
  44 namespace llvm {
  45
  46 template<typename T> class SmallVectorImpl;
  47 class TargetRegisterInfo;
  48 class VirtRegMap;
  49 class LiveIntervals;
  50 class Spiller;
  51
  52 // Forward declare a priority queue of live virtual registers. If an
  53 // implementation needs to prioritize by anything other than spill weight, then
  54 // this will become an abstract base class with virtual calls to push/get.
  55 class LiveVirtRegQueue;
  56
  57 /// RegAllocBase provides the register allocation driver and interface that can
  58 /// be extended to add interesting heuristics.
  59 ///
  60 /// Register allocators must override the selectOrSplit() method to implement
  61 /// live range splitting. They must also override enqueue/dequeue to provide an
  62 /// assignment order.
  63 class RegAllocBase {
  64   LiveIntervalUnion::Allocator UnionAllocator;
  65
  66   // Cache tag for PhysReg2LiveUnion entries. Increment whenever virtual
  67   // registers may have changed.
  68   unsigned UserTag;
  69
  70 protected:
  71   // Array of LiveIntervalUnions indexed by physical register.
  72   class LiveUnionArray {
  73     unsigned NumRegs;
  74     LiveIntervalUnion *Array;
  75   public:
  76     LiveUnionArray(): NumRegs(0), Array(0) {}
  77     ~LiveUnionArray() { clear(); }
  78
  79     unsigned numRegs() const { return NumRegs; }
  80
  81     void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
  82
  83     void clear();
  84
  85     LiveIntervalUnion& operator[](unsigned PhysReg) {
  86       assert(PhysReg <  NumRegs && "physReg out of bounds");
  87       return Array[PhysReg];
  88     }
  89   };
  90
  91   const TargetRegisterInfo *TRI;
  92   MachineRegisterInfo *MRI;
  93   VirtRegMap *VRM;
  94   LiveIntervals *LIS;
  95   RegisterClassInfo RegClassInfo;
  96   LiveUnionArray PhysReg2LiveUnion;
  97
  98   // Current queries, one per physreg. They must be reinitialized each time we
  99   // query on a new live virtual register.
 100   OwningArrayPtr<LiveIntervalUnion::Query> Queries;
 101
 102   RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
 103
 104   virtual ~RegAllocBase() {}
 105
 106   // A RegAlloc pass should call this before allocatePhysRegs.
 107   void init(VirtRegMap &vrm, LiveIntervals &lis);
 108
 109   // Get an initialized query to check interferences between lvr and preg.  Note
 110   // that Query::init must be called at least once for each physical register
 111   // before querying a new live virtual register. This ties Queries and
 112   // PhysReg2LiveUnion together.
 113   LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
 114     Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
 115     return Queries[PhysReg];
 116   }
 117
 118   // Invalidate all cached information about virtual registers - live ranges may
 119   // have changed.
 120   void invalidateVirtRegs() { ++UserTag; }
 121
 122   // The top-level driver. The output is a VirtRegMap that us updated with
 123   // physical register assignments.
 124   //
 125   // If an implementation wants to override the LiveInterval comparator, we
 126   // should modify this interface to allow passing in an instance derived from
 127   // LiveVirtRegQueue.
 128   void allocatePhysRegs();
 129
 130   // Get a temporary reference to a Spiller instance.
 131   virtual Spiller &spiller() = 0;
 132
 133   /// enqueue - Add VirtReg to the priority queue of unassigned registers.
 134   virtual void enqueue(LiveInterval *LI) = 0;
 135
 136   /// dequeue - Return the next unassigned register, or NULL.
 137   virtual LiveInterval *dequeue() = 0;
 138
 139   // A RegAlloc pass should override this to provide the allocation heuristics.
 140   // Each call must guarantee forward progess by returning an available PhysReg
 141   // or new set of split live virtual registers. It is up to the splitter to
 142   // converge quickly toward fully spilled live ranges.
 143   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
 144                                  SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
 145
 146   // A RegAlloc pass should call this when PassManager releases its memory.
 147   virtual void releaseMemory();
 148
 149   // Helper for checking interference between a live virtual register and a
 150   // physical register, including all its register aliases. If an interference
 151   // exists, return the interfering register, which may be preg or an alias.
 152   unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
 153
 154   /// assign - Assign VirtReg to PhysReg.
 155   /// This should not be called from selectOrSplit for the current register.
 156   void assign(LiveInterval &VirtReg, unsigned PhysReg);
 157
 158   /// unassign - Undo a previous assignment of VirtReg to PhysReg.
 159   /// This can be invoked from selectOrSplit, but be careful to guarantee that
 160   /// allocation is making progress.
 161   void unassign(LiveInterval &VirtReg, unsigned PhysReg);
 162
 163   // Helper for spilling all live virtual registers currently unified under preg
 164   // that interfere with the most recently queried lvr.  Return true if spilling
 165   // was successful, and append any new spilled/split intervals to splitLVRs.
 166   bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
 167                           SmallVectorImpl<LiveInterval*> &SplitVRegs);
 168
 169   /// addMBBLiveIns - Add physreg liveins to basic blocks.
 170   void addMBBLiveIns(MachineFunction *);
 171
 172 #ifndef NDEBUG
 173   // Verify each LiveIntervalUnion.
 174   void verify();
 175 #endif
 176
 177   // Use this group name for NamedRegionTimer.
 178   static const char *TimerGroupName;
 179
 180 public:
 181   /// VerifyEnabled - True when -verify-regalloc is given.
 182   static bool VerifyEnabled;
 183
 184 private:
 185   void seedLiveRegs();
 186
 187   void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
 188                 SmallVectorImpl<LiveInterval*> &SplitVRegs);
 189 };
 190
 191 } // end namespace llvm
 192
 193 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)