lib/MC/MCDisassembler/EDOperand.cpp

   1 //===-- EDOperand.cpp - LLVM Enhanced Disassembler ------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the Enhanced Disassembly library's operand class.  The
  11 // operand is responsible for allowing evaluation given a particular register
  12 // context.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "EDOperand.h"
  17 #include "EDDisassembler.h"
  18 #include "EDInst.h"
  19 #include "llvm/MC/EDInstInfo.h"
  20 #include "llvm/MC/MCInst.h"
  21 using namespace llvm;
  22
  23 EDOperand::EDOperand(const EDDisassembler &disassembler,
  24                      const EDInst &inst,
  25                      unsigned int opIndex,
  26                      unsigned int &mcOpIndex) :
  27   Disassembler(disassembler),
  28   Inst(inst),
  29   OpIndex(opIndex),
  30   MCOpIndex(mcOpIndex) {
  31   unsigned int numMCOperands = 0;
  32
  33   if (Disassembler.Key.Arch == Triple::x86 ||
  34       Disassembler.Key.Arch == Triple::x86_64) {
  35     uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
  36
  37     switch (operandType) {
  38     default:
  39       break;
  40     case kOperandTypeImmediate:
  41       numMCOperands = 1;
  42       break;
  43     case kOperandTypeRegister:
  44       numMCOperands = 1;
  45       break;
  46     case kOperandTypeX86Memory:
  47       numMCOperands = 5;
  48       break;
  49     case kOperandTypeX86EffectiveAddress:
  50       numMCOperands = 4;
  51       break;
  52     case kOperandTypeX86PCRelative:
  53       numMCOperands = 1;
  54       break;
  55     }
  56   }
  57   else if (Disassembler.Key.Arch == Triple::arm ||
  58            Disassembler.Key.Arch == Triple::thumb) {
  59     uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
  60
  61     switch (operandType) {
  62     default:
  63     case kOperandTypeARMRegisterList:
  64       break;
  65     case kOperandTypeImmediate:
  66     case kOperandTypeRegister:
  67     case kOperandTypeARMBranchTarget:
  68     case kOperandTypeARMSoImm:
  69     case kOperandTypeThumb2SoImm:
  70     case kOperandTypeARMSoImm2Part:
  71     case kOperandTypeARMPredicate:
  72     case kOperandTypeThumbITMask:
  73     case kOperandTypeThumb2AddrModeImm8Offset:
  74     case kOperandTypeARMTBAddrMode:
  75     case kOperandTypeThumb2AddrModeImm8s4Offset:
  76     case kOperandTypeARMAddrMode7:
  77     case kOperandTypeThumb2AddrModeReg:
  78       numMCOperands = 1;
  79       break;
  80     case kOperandTypeThumb2SoReg:
  81     case kOperandTypeARMAddrMode2Offset:
  82     case kOperandTypeARMAddrMode3Offset:
  83     case kOperandTypeARMAddrMode4:
  84     case kOperandTypeARMAddrMode5:
  85     case kOperandTypeARMAddrModePC:
  86     case kOperandTypeThumb2AddrModeImm8:
  87     case kOperandTypeThumb2AddrModeImm12:
  88     case kOperandTypeThumb2AddrModeImm8s4:
  89     case kOperandTypeThumbAddrModeRR:
  90     case kOperandTypeThumbAddrModeSP:
  91       numMCOperands = 2;
  92       break;
  93     case kOperandTypeARMSoReg:
  94     case kOperandTypeARMAddrMode2:
  95     case kOperandTypeARMAddrMode3:
  96     case kOperandTypeThumb2AddrModeSoReg:
  97     case kOperandTypeThumbAddrModeS1:
  98     case kOperandTypeThumbAddrModeS2:
  99     case kOperandTypeThumbAddrModeS4:
 100     case kOperandTypeARMAddrMode6Offset:
 101       numMCOperands = 3;
 102       break;
 103     case kOperandTypeARMAddrMode6:
 104       numMCOperands = 4;
 105       break;
 106     }
 107   }
 108
 109   mcOpIndex += numMCOperands;
 110 }
 111
 112 EDOperand::~EDOperand() {
 113 }
 114
 115 int EDOperand::evaluate(uint64_t &result,
 116                         EDRegisterReaderCallback callback,
 117                         void *arg) {
 118   uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
 119
 120   switch (Disassembler.Key.Arch) {
 121   default:
 122     return -1;
 123   case Triple::x86:
 124   case Triple::x86_64:
 125     switch (operandType) {
 126     default:
 127       return -1;
 128     case kOperandTypeImmediate:
 129       result = Inst.Inst->getOperand(MCOpIndex).getImm();
 130       return 0;
 131     case kOperandTypeRegister:
 132     {
 133       unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
 134       return callback(&result, reg, arg);
 135     }
 136     case kOperandTypeX86PCRelative:
 137     {
 138       int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
 139
 140       uint64_t ripVal;
 141
 142       // TODO fix how we do this
 143
 144       if (callback(&ripVal, Disassembler.registerIDWithName("RIP"), arg))
 145         return -1;
 146
 147       result = ripVal + displacement;
 148       return 0;
 149     }
 150     case kOperandTypeX86Memory:
 151     case kOperandTypeX86EffectiveAddress:
 152     {
 153       unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
 154       uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
 155       unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
 156       int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
 157
 158       uint64_t addr = 0;
 159
 160       unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
 161
 162       if (segmentReg != 0 && Disassembler.Key.Arch == Triple::x86_64) {
 163         unsigned fsID = Disassembler.registerIDWithName("FS");
 164         unsigned gsID = Disassembler.registerIDWithName("GS");
 165
 166         if (segmentReg == fsID ||
 167             segmentReg == gsID) {
 168           uint64_t segmentBase;
 169           if (!callback(&segmentBase, segmentReg, arg))
 170             addr += segmentBase;
 171         }
 172       }
 173
 174       if (baseReg) {
 175         uint64_t baseVal;
 176         if (callback(&baseVal, baseReg, arg))
 177           return -1;
 178         addr += baseVal;
 179       }
 180
 181       if (indexReg) {
 182         uint64_t indexVal;
 183         if (callback(&indexVal, indexReg, arg))
 184           return -1;
 185         addr += (scaleAmount * indexVal);
 186       }
 187
 188       addr += displacement;
 189
 190       result = addr;
 191       return 0;
 192     }
 193     } // switch (operandType)
 194     break;
 195   case Triple::arm:
 196   case Triple::thumb:
 197     switch (operandType) {
 198     default:
 199       return -1;
 200     case kOperandTypeImmediate:
 201       if (!Inst.Inst->getOperand(MCOpIndex).isImm())
 202         return -1;
 203
 204       result = Inst.Inst->getOperand(MCOpIndex).getImm();
 205       return 0;
 206     case kOperandTypeRegister:
 207     {
 208       if (!Inst.Inst->getOperand(MCOpIndex).isReg())
 209         return -1;
 210
 211       unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
 212       return callback(&result, reg, arg);
 213     }
 214     case kOperandTypeARMBranchTarget:
 215     {
 216       if (!Inst.Inst->getOperand(MCOpIndex).isImm())
 217         return -1;
 218
 219       int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
 220
 221       uint64_t pcVal;
 222
 223       if (callback(&pcVal, Disassembler.registerIDWithName("PC"), arg))
 224         return -1;
 225
 226       result = pcVal + displacement;
 227       return 0;
 228     }
 229     }
 230     break;
 231   }
 232
 233   return -1;
 234 }
 235
 236 int EDOperand::isRegister() {
 237   return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeRegister);
 238 }
 239
 240 unsigned EDOperand::regVal() {
 241   return Inst.Inst->getOperand(MCOpIndex).getReg();
 242 }
 243
 244 int EDOperand::isImmediate() {
 245   return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeImmediate);
 246 }
 247
 248 uint64_t EDOperand::immediateVal() {
 249   return Inst.Inst->getOperand(MCOpIndex).getImm();
 250 }
 251
 252 int EDOperand::isMemory() {
 253   uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
 254
 255   switch (operandType) {
 256   default:
 257     return 0;
 258   case kOperandTypeX86Memory:
 259   case kOperandTypeX86PCRelative:
 260   case kOperandTypeX86EffectiveAddress:
 261   case kOperandTypeARMSoReg:
 262   case kOperandTypeARMSoImm:
 263   case kOperandTypeARMAddrMode2:
 264   case kOperandTypeARMAddrMode2Offset:
 265   case kOperandTypeARMAddrMode3:
 266   case kOperandTypeARMAddrMode3Offset:
 267   case kOperandTypeARMAddrMode4:
 268   case kOperandTypeARMAddrMode5:
 269   case kOperandTypeARMAddrMode6:
 270   case kOperandTypeARMAddrMode7:
 271   case kOperandTypeARMAddrModePC:
 272   case kOperandTypeARMBranchTarget:
 273   case kOperandTypeThumbAddrModeS1:
 274   case kOperandTypeThumbAddrModeS2:
 275   case kOperandTypeThumbAddrModeS4:
 276   case kOperandTypeThumbAddrModeRR:
 277   case kOperandTypeThumbAddrModeSP:
 278   case kOperandTypeThumb2SoImm:
 279   case kOperandTypeThumb2AddrModeImm8:
 280   case kOperandTypeThumb2AddrModeImm8Offset:
 281   case kOperandTypeThumb2AddrModeImm12:
 282   case kOperandTypeThumb2AddrModeSoReg:
 283   case kOperandTypeThumb2AddrModeImm8s4:
 284   case kOperandTypeThumb2AddrModeReg:
 285     return 1;
 286   }
 287 }
 288
 289 #ifdef __BLOCKS__
 290 namespace {
 291   struct RegisterReaderWrapper {
 292     EDOperand::EDRegisterBlock_t regBlock;
 293   };
 294 }
 295
 296 static int readerWrapperCallback(uint64_t *value, unsigned regID, void *arg) {
 297   RegisterReaderWrapper *wrapper = (RegisterReaderWrapper *)arg;
 298   return wrapper->regBlock(value, regID);
 299 }
 300
 301 int EDOperand::evaluate(uint64_t &result, EDRegisterBlock_t regBlock) {
 302   RegisterReaderWrapper wrapper;
 303   wrapper.regBlock = regBlock;
 304   return evaluate(result, readerWrapperCallback, (void*)&wrapper);
 305 }
 306 #endif