?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Use BranchProbability instead of floating points in IfConverter.
[llvm/stm8.git] / lib / Target / ARM / ARMAsmBackend.cpp
blob5e438a9767324df4c12d89da636c0f846fd4feaa
1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "ARM.h"
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Object/MachOFormat.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetAsmBackend.h"
27 #include "llvm/Target/TargetRegistry.h"
28 using namespace llvm;
29
30 namespace {
31 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
32 public:
33 ARMELFObjectWriter(Triple::OSType OSType)
34 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM,
35 /*HasRelocationAddend*/ false) {}
36 };
37
38 class ARMAsmBackend : public TargetAsmBackend {
39 bool isThumbMode; // Currently emitting Thumb code.
40 public:
41 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
42
43 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
44
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
46 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
47 // This table *must* be in the order that the fixup_* kinds are defined in
48 // ARMFixupKinds.h.
49 //
50 // Name Offset (bits) Size (bits) Flags
51 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
52 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
53 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
54 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
55 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
56 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
57 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
58 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
59 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
60 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
61 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
62 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
63 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
72 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
73 { "fixup_arm_movt_hi16", 0, 20, 0 },
74 { "fixup_arm_movw_lo16", 0, 20, 0 },
75 { "fixup_t2_movt_hi16", 0, 20, 0 },
76 { "fixup_t2_movw_lo16", 0, 20, 0 },
77 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
81 };
82
83 if (Kind < FirstTargetFixupKind)
84 return TargetAsmBackend::getFixupKindInfo(Kind);
85
86 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
87 "Invalid kind!");
88 return Infos[Kind - FirstTargetFixupKind];
89 }
90
91 bool MayNeedRelaxation(const MCInst &Inst) const;
92
93 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
94
95 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
96
97 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
98 switch (Flag) {
99 default: break;
100 case MCAF_Code16:
101 setIsThumb(true);
102 break;
103 case MCAF_Code32:
104 setIsThumb(false);
105 break;
106 }
107 }
108
109 unsigned getPointerSize() const { return 4; }
110 bool isThumb() const { return isThumbMode; }
111 void setIsThumb(bool it) { isThumbMode = it; }
112 };
113 } // end anonymous namespace
114
115 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
116 // FIXME: Thumb targets, different move constant targets..
117 return false;
118 }
119
120 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
121 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
122 return;
123 }
124
125 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
126 if (isThumb()) {
127 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
128 // use 0x46c0 (which is a 'mov r8, r8' insn).
129 uint64_t NumNops = Count / 2;
130 for (uint64_t i = 0; i != NumNops; ++i)
131 OW->Write16(0xbf00);
132 if (Count & 1)
133 OW->Write8(0);
134 return true;
135 }
136 // ARM mode
137 uint64_t NumNops = Count / 4;
138 for (uint64_t i = 0; i != NumNops; ++i)
139 OW->Write32(0xe1a00000);
140 switch (Count % 4) {
141 default: break; // No leftover bytes to write
142 case 1: OW->Write8(0); break;
143 case 2: OW->Write16(0); break;
144 case 3: OW->Write16(0); OW->Write8(0xa0); break;
145 }
146
147 return true;
148 }
149
150 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
151 switch (Kind) {
152 default:
153 llvm_unreachable("Unknown fixup kind!");
154 case FK_Data_1:
155 case FK_Data_2:
156 case FK_Data_4:
157 return Value;
158 case ARM::fixup_arm_movt_hi16:
159 Value >>= 16;
160 // Fallthrough
161 case ARM::fixup_arm_movw_lo16:
162 case ARM::fixup_arm_movt_hi16_pcrel:
163 case ARM::fixup_arm_movw_lo16_pcrel: {
164 unsigned Hi4 = (Value & 0xF000) >> 12;
165 unsigned Lo12 = Value & 0x0FFF;
166 assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
167 "Out of range pc-relative fixup value!");
168 // inst{19-16} = Hi4;
169 // inst{11-0} = Lo12;
170 Value = (Hi4 << 16) | (Lo12);
171 return Value;
172 }
173 case ARM::fixup_t2_movt_hi16:
174 Value >>= 16;
175 // Fallthrough
176 case ARM::fixup_t2_movw_lo16:
177 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
178 // the other hi16 fixup?
179 case ARM::fixup_t2_movw_lo16_pcrel: {
180 unsigned Hi4 = (Value & 0xF000) >> 12;
181 unsigned i = (Value & 0x800) >> 11;
182 unsigned Mid3 = (Value & 0x700) >> 8;
183 unsigned Lo8 = Value & 0x0FF;
184 // inst{19-16} = Hi4;
185 // inst{26} = i;
186 // inst{14-12} = Mid3;
187 // inst{7-0} = Lo8;
188 // The value comes in as the whole thing, not just the portion required
189 // for this fixup, so we need to mask off the bits not handled by this
190 // portion (lo vs. hi).
191 Value &= 0xffff;
192 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
193 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
194 swapped |= (Value & 0x0000FFFF) << 16;
195 return swapped;
196 }
197 case ARM::fixup_arm_ldst_pcrel_12:
198 // ARM PC-relative values are offset by 8.
199 Value -= 4;
200 // FALLTHROUGH
201 case ARM::fixup_t2_ldst_pcrel_12: {
202 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
203 Value -= 4;
204 bool isAdd = true;
205 if ((int64_t)Value < 0) {
206 Value = -Value;
207 isAdd = false;
208 }
209 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
210 Value |= isAdd << 23;
211
212 // Same addressing mode as fixup_arm_pcrel_10,
213 // but with 16-bit halfwords swapped.
214 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
215 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
216 swapped |= (Value & 0x0000FFFF) << 16;
217 return swapped;
218 }
219
220 return Value;
221 }
222 case ARM::fixup_thumb_adr_pcrel_10:
223 return ((Value - 4) >> 2) & 0xff;
224 case ARM::fixup_arm_adr_pcrel_12: {
225 // ARM PC-relative values are offset by 8.
226 Value -= 8;
227 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
228 if ((int64_t)Value < 0) {
229 Value = -Value;
230 opc = 2; // 0b0010
231 }
232 assert(ARM_AM::getSOImmVal(Value) != -1 &&
233 "Out of range pc-relative fixup value!");
234 // Encode the immediate and shift the opcode into place.
235 return ARM_AM::getSOImmVal(Value) | (opc << 21);
236 }
237
238 case ARM::fixup_t2_adr_pcrel_12: {
239 Value -= 4;
240 unsigned opc = 0;
241 if ((int64_t)Value < 0) {
242 Value = -Value;
243 opc = 5;
244 }
245
246 uint32_t out = (opc << 21);
247 out |= (Value & 0x800) << 15;
248 out |= (Value & 0x700) << 4;
249 out |= (Value & 0x0FF);
250
251 uint64_t swapped = (out & 0xFFFF0000) >> 16;
252 swapped |= (out & 0x0000FFFF) << 16;
253 return swapped;
254 }
255
256 case ARM::fixup_arm_condbranch:
257 case ARM::fixup_arm_uncondbranch:
258 // These values don't encode the low two bits since they're always zero.
259 // Offset by 8 just as above.
260 return 0xffffff & ((Value - 8) >> 2);
261 case ARM::fixup_t2_uncondbranch: {
262 Value = Value - 4;
263 Value >>= 1; // Low bit is not encoded.
264
265 uint32_t out = 0;
266 bool I = Value & 0x800000;
267 bool J1 = Value & 0x400000;
268 bool J2 = Value & 0x200000;
269 J1 ^= I;
270 J2 ^= I;
271
272 out |= I << 26; // S bit
273 out |= !J1 << 13; // J1 bit
274 out |= !J2 << 11; // J2 bit
275 out |= (Value & 0x1FF800) << 5; // imm6 field
276 out |= (Value & 0x0007FF); // imm11 field
277
278 uint64_t swapped = (out & 0xFFFF0000) >> 16;
279 swapped |= (out & 0x0000FFFF) << 16;
280 return swapped;
281 }
282 case ARM::fixup_t2_condbranch: {
283 Value = Value - 4;
284 Value >>= 1; // Low bit is not encoded.
285
286 uint64_t out = 0;
287 out |= (Value & 0x80000) << 7; // S bit
288 out |= (Value & 0x40000) >> 7; // J2 bit
289 out |= (Value & 0x20000) >> 4; // J1 bit
290 out |= (Value & 0x1F800) << 5; // imm6 field
291 out |= (Value & 0x007FF); // imm11 field
292
293 uint32_t swapped = (out & 0xFFFF0000) >> 16;
294 swapped |= (out & 0x0000FFFF) << 16;
295 return swapped;
296 }
297 case ARM::fixup_arm_thumb_bl: {
298 // The value doesn't encode the low bit (always zero) and is offset by
299 // four. The value is encoded into disjoint bit positions in the destination
300 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
301 //
302 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
303 //
304 // Note that the halfwords are stored high first, low second; so we need
305 // to transpose the fixup value here to map properly.
306 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
307 uint32_t Binary = 0;
308 Value = 0x3fffff & ((Value - 4) >> 1);
309 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
310 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
311 Binary |= isNeg << 10; // Sign bit.
312 return Binary;
313 }
314 case ARM::fixup_arm_thumb_blx: {
315 // The value doesn't encode the low two bits (always zero) and is offset by
316 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
317 // positions in the destination opcode. x = unchanged, I = immediate value
318 // bit, S = sign extension bit, 0 = zero.
319 //
320 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
321 //
322 // Note that the halfwords are stored high first, low second; so we need
323 // to transpose the fixup value here to map properly.
324 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
325 uint32_t Binary = 0;
326 Value = 0xfffff & ((Value - 2) >> 2);
327 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
328 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
329 Binary |= isNeg << 10; // Sign bit.
330 return Binary;
331 }
332 case ARM::fixup_arm_thumb_cp:
333 // Offset by 4, and don't encode the low two bits. Two bytes of that
334 // 'off by 4' is implicitly handled by the half-word ordering of the
335 // Thumb encoding, so we only need to adjust by 2 here.
336 return ((Value - 2) >> 2) & 0xff;
337 case ARM::fixup_arm_thumb_cb: {
338 // Offset by 4 and don't encode the lower bit, which is always 0.
339 uint32_t Binary = (Value - 4) >> 1;
340 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
341 }
342 case ARM::fixup_arm_thumb_br:
343 // Offset by 4 and don't encode the lower bit, which is always 0.
344 return ((Value - 4) >> 1) & 0x7ff;
345 case ARM::fixup_arm_thumb_bcc:
346 // Offset by 4 and don't encode the lower bit, which is always 0.
347 return ((Value - 4) >> 1) & 0xff;
348 case ARM::fixup_arm_pcrel_10:
349 Value = Value - 4; // ARM fixups offset by an additional word and don't
350 // need to adjust for the half-word ordering.
351 // Fall through.
352 case ARM::fixup_t2_pcrel_10: {
353 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
354 Value = Value - 4;
355 bool isAdd = true;
356 if ((int64_t)Value < 0) {
357 Value = -Value;
358 isAdd = false;
359 }
360 // These values don't encode the low two bits since they're always zero.
361 Value >>= 2;
362 assert ((Value < 256) && "Out of range pc-relative fixup value!");
363 Value |= isAdd << 23;
364
365 // Same addressing mode as fixup_arm_pcrel_10,
366 // but with 16-bit halfwords swapped.
367 if (Kind == ARM::fixup_t2_pcrel_10) {
368 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
369 swapped |= (Value & 0x0000FFFF) << 16;
370 return swapped;
371 }
372
373 return Value;
374 }
375 }
376 }
377
378 namespace {
379
380 // FIXME: This should be in a separate file.
381 // ELF is an ELF of course...
382 class ELFARMAsmBackend : public ARMAsmBackend {
383 public:
384 Triple::OSType OSType;
385 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
386 : ARMAsmBackend(T), OSType(_OSType) { }
387
388 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
389 uint64_t Value) const;
390
391 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
392 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS,
393 /*IsLittleEndian*/ true);
394 }
395 };
396
397 // FIXME: Raise this to share code between Darwin and ELF.
398 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
399 unsigned DataSize, uint64_t Value) const {
400 unsigned NumBytes = 4; // FIXME: 2 for Thumb
401 Value = adjustFixupValue(Fixup.getKind(), Value);
402 if (!Value) return; // Doesn't change encoding.
403
404 unsigned Offset = Fixup.getOffset();
405
406 // For each byte of the fragment that the fixup touches, mask in the bits from
407 // the fixup value. The Value has been "split up" into the appropriate
408 // bitfields above.
409 for (unsigned i = 0; i != NumBytes; ++i)
410 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
411 }
412
413 // FIXME: This should be in a separate file.
414 class DarwinARMAsmBackend : public ARMAsmBackend {
415 public:
416 const object::mach::CPUSubtypeARM Subtype;
417 DarwinARMAsmBackend(const Target &T, object::mach::CPUSubtypeARM st)
418 : ARMAsmBackend(T), Subtype(st) { }
419
420 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
421 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
422 object::mach::CTM_ARM,
423 Subtype);
424 }
425
426 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
427 uint64_t Value) const;
428
429 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
430 return false;
431 }
432 };
433
434 /// getFixupKindNumBytes - The number of bytes the fixup may change.
435 static unsigned getFixupKindNumBytes(unsigned Kind) {
436 switch (Kind) {
437 default:
438 llvm_unreachable("Unknown fixup kind!");
439
440 case FK_Data_1:
441 case ARM::fixup_arm_thumb_bcc:
442 case ARM::fixup_arm_thumb_cp:
443 case ARM::fixup_thumb_adr_pcrel_10:
444 return 1;
445
446 case FK_Data_2:
447 case ARM::fixup_arm_thumb_br:
448 case ARM::fixup_arm_thumb_cb:
449 return 2;
450
451 case ARM::fixup_arm_ldst_pcrel_12:
452 case ARM::fixup_arm_pcrel_10:
453 case ARM::fixup_arm_adr_pcrel_12:
454 case ARM::fixup_arm_condbranch:
455 case ARM::fixup_arm_uncondbranch:
456 return 3;
457
458 case FK_Data_4:
459 case ARM::fixup_t2_ldst_pcrel_12:
460 case ARM::fixup_t2_condbranch:
461 case ARM::fixup_t2_uncondbranch:
462 case ARM::fixup_t2_pcrel_10:
463 case ARM::fixup_t2_adr_pcrel_12:
464 case ARM::fixup_arm_thumb_bl:
465 case ARM::fixup_arm_thumb_blx:
466 case ARM::fixup_arm_movt_hi16:
467 case ARM::fixup_arm_movw_lo16:
468 case ARM::fixup_arm_movt_hi16_pcrel:
469 case ARM::fixup_arm_movw_lo16_pcrel:
470 case ARM::fixup_t2_movt_hi16:
471 case ARM::fixup_t2_movw_lo16:
472 case ARM::fixup_t2_movt_hi16_pcrel:
473 case ARM::fixup_t2_movw_lo16_pcrel:
474 return 4;
475 }
476 }
477
478 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
479 unsigned DataSize, uint64_t Value) const {
480 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
481 Value = adjustFixupValue(Fixup.getKind(), Value);
482 if (!Value) return; // Doesn't change encoding.
483
484 unsigned Offset = Fixup.getOffset();
485 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
486
487 // For each byte of the fragment that the fixup touches, mask in the
488 // bits from the fixup value.
489 for (unsigned i = 0; i != NumBytes; ++i)
490 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
491 }
492
493 } // end anonymous namespace
494
495 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
496 const std::string &TT) {
497 Triple TheTriple(TT);
498
499 if (TheTriple.isOSDarwin()) {
500 if (TheTriple.getArchName() == "armv4t" ||
501 TheTriple.getArchName() == "thumbv4t")
502 return new DarwinARMAsmBackend(T, object::mach::CSARM_V4T);
503 else if (TheTriple.getArchName() == "armv5e" ||
504 TheTriple.getArchName() == "thumbv5e")
505 return new DarwinARMAsmBackend(T, object::mach::CSARM_V5TEJ);
506 else if (TheTriple.getArchName() == "armv6" ||
507 TheTriple.getArchName() == "thumbv6")
508 return new DarwinARMAsmBackend(T, object::mach::CSARM_V6);
509 return new DarwinARMAsmBackend(T, object::mach::CSARM_V7);
510 }
511
512 if (TheTriple.isOSWindows())
513 assert(0 && "Windows not supported on ARM");
514
515 return new ELFARMAsmBackend(T, Triple(TT).getOS());
516 }
STM8 backend for LLVM